Kinetis KE1xF Sub-Family Reference
Manual
Supports: MKE1xF512VLL16, MKE1xF512VLH16, MKE1xF256VLL16,
MKE1xF256VLH16
Document Number: KE1xFP100M168SF0RM
Rev. 4, 06/2019
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Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 47
1.2 Organization..................................................................................................................................................................47
1.3 Module descriptions......................................................................................................................................................47
1.3.1 Example: chip-specific information that supersedes content in the same chapter.......................................48
1.3.2 Example: chip-specific information that refers to a different chapter......................................................... 49
1.4 Register descriptions.....................................................................................................................................................50
1.5 Conventions.................................................................................................................................................................. 51
1.5.1 Numbering systems......................................................................................................................................51
1.5.2 Typographic notation................................................................................................................................... 51
1.5.3 Special terms................................................................................................................................................52
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................53
2.2 Block Diagram..............................................................................................................................................................53
2.3 Module Functional Categories......................................................................................................................................54
Chapter 3
Core Overview
3.1 ARM Cortex-M4 ..........................................................................................................................................................57
3.2 Core Buses and Interfaces.............................................................................................................................................58
3.3 Core Component Configuration....................................................................................................................................59
3.4 SysTick Clock Configuration....................................................................................................................................... 59
Chapter 4
Interrupts
4.1 Introduction...................................................................................................................................................................61
4.2 NVIC configuration...................................................................................................................................................... 61
4.2.1 Interrupt priority levels................................................................................................................................ 61
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4.2.2 Non-maskable interrupt................................................................................................................................62
4.3 Interrupt channel assignments.......................................................................................................................................62
4.3.1 Determining the bitfield and register location for configuring a particular interrupt.................................. 66
Chapter 5
System Integration Module (SIM)
5.1 Introduction...................................................................................................................................................................67
5.1.1 Features........................................................................................................................................................ 67
5.2 Memory map and register definition.............................................................................................................................67
5.2.1 Chip Control register (SIM_CHIPCTL)...................................................................................................... 68
5.2.2 FTM Option Register 0 (SIM_FTMOPT0)................................................................................................. 70
5.2.3 ADC Options Register (SIM_ADCOPT).................................................................................................... 72
5.2.4 FTM Option Register 1 (SIM_FTMOPT1)................................................................................................. 74
5.2.5 System Device Identification Register (SIM_SDID)...................................................................................76
5.2.6 Platform Clock Gating Control Register (SIM_PLATCGC).......................................................................77
5.2.7 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 78
5.2.8 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 81
5.2.9 Unique Identification Register High (SIM_UIDH)..................................................................................... 82
5.2.10 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................82
5.2.11 Unique Identification Register Mid Low (SIM_UIDML)........................................................................... 83
5.2.12 Unique Identification Register Low (SIM_UIDL)...................................................................................... 83
5.2.13 System Clock Divider Register 4 (SIM_CLKDIV4)...................................................................................84
5.2.14 Miscellaneous Control register (SIM_MISCTRL)...................................................................................... 85
Chapter 6
Miscellaneous Control Module (MCM)
6.1 Introduction...................................................................................................................................................................87
6.1.1 Features........................................................................................................................................................ 87
6.2 Memory map/register descriptions............................................................................................................................... 87
6.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................88
6.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 89
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6.2.3 Core Platform Control Register (MCM_CPCR)..........................................................................................89
6.2.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................. 91
6.2.5 Store Buffer Fault address register (MCM_FADR).................................................................................... 94
6.2.6 Store Buffer Fault Attributes register (MCM_FATR).................................................................................94
6.2.7 Store Buffer Fault Data Register (MCM_FDR).......................................................................................... 96
6.2.8 Process ID register (MCM_PID)................................................................................................................. 97
6.2.9 Compute Operation Control Register (MCM_CPO)................................................................................... 98
6.2.10
Local Memory Descriptor Register (MCM_LMDRn).................................................................................99
6.2.11 LMEM Parity & ECC Control Register (MCM_LMPECR)....................................................................... 103
6.2.12 LMEM Parity & ECC Interrupt Register (MCM_LMPEIR).......................................................................104
6.2.13 LMEM Fault Address Register (MCM_LMFAR).......................................................................................105
6.2.14 LMEM Fault Attribute Register (MCM_LMFATR)...................................................................................106
6.2.15 LMEM Fault Data High Register (MCM_LMFDHR)................................................................................ 107
6.2.16 LMEM Fault Data Low Register (MCM_LMFDLR)..................................................................................107
6.3 Functional description...................................................................................................................................................108
6.3.1 Interrupts...................................................................................................................................................... 108
Chapter 7
Crossbar Switch Lite (AXBS-Lite)
7.1 Chip-specific information for this module....................................................................................................................109
7.1.1 Instantiation Information..............................................................................................................................109
7.2 Introduction...................................................................................................................................................................110
7.2.1 Features........................................................................................................................................................ 110
7.3 Memory Map / Register Definition...............................................................................................................................110
7.4 Functional Description..................................................................................................................................................110
7.4.1 General operation.........................................................................................................................................111
7.4.2 Arbitration....................................................................................................................................................111
7.5 Initialization/application information........................................................................................................................... 113
Chapter 8
Memory Protection Unit (MPU)
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8.1 Chip-specific information for this module....................................................................................................................115
8.1.1 Instantiation Information..............................................................................................................................115
8.2 Introduction...................................................................................................................................................................116
8.3 Overview.......................................................................................................................................................................116
8.3.1 Block diagram..............................................................................................................................................116
8.3.2 Features........................................................................................................................................................ 117
8.4 Memory map/register definition................................................................................................................................... 118
8.4.1 Control/Error Status Register (MPU_CESR).............................................................................................. 120
8.4.2
Error Address Register, slave port n (MPU_EARn)....................................................................................121
8.4.3
Error Detail Register, slave port n (MPU_EDRn)....................................................................................... 122
8.4.4
Region Descriptor n, Word 0 (MPU_RGDn_WORD0).............................................................................. 123
8.4.5
Region Descriptor n, Word 1 (MPU_RGDn_WORD1).............................................................................. 124
8.4.6
Region Descriptor n, Word 2 (MPU_RGDn_WORD2).............................................................................. 124
8.4.7
Region Descriptor n, Word 3 (MPU_RGDn_WORD3).............................................................................. 127
8.4.8
Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................128
8.5 Functional description...................................................................................................................................................130
8.5.1 Access evaluation macro..............................................................................................................................130
8.5.2 Putting it all together and error terminations............................................................................................... 132
8.5.3 Power management......................................................................................................................................133
8.6 Initialization information.............................................................................................................................................. 133
8.7 Application information................................................................................................................................................133
8.8 Usage Guide..................................................................................................................................................................135
8.8.1 MPU Access Violation Indications..............................................................................................................135
8.8.2 Reset Values for RGD0 Registers................................................................................................................136
8.8.3 Write Access Restrictions for RGD0 Registers........................................................................................... 136
Chapter 9
Peripheral Bridge (AIPS-Lite)
9.1 Chip-specific information for this module....................................................................................................................139
9.1.1 Peripheral slot assignment........................................................................................................................... 139
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9.2 Introduction...................................................................................................................................................................139
9.2.1 Features........................................................................................................................................................ 139
9.2.2 General operation.........................................................................................................................................140
9.3 Memory map/register definition................................................................................................................................... 140
9.3.1 Master Privilege Register A (AIPS_MPRA)............................................................................................... 141
9.3.2
Peripheral Access Control Register (AIPS_PACRn)...................................................................................144
9.3.3
Off-Platform Peripheral Access Control Register (AIPS_OPACRn)..........................................................149
9.3.4 Peripheral Access Control Register (AIPS_PACRU)..................................................................................154
9.4 Functional description...................................................................................................................................................155
9.4.1 Access support............................................................................................................................................. 155
Chapter 10
Trigger MUX Control (TRGMUX)
10.1 Chip-specific information for this module....................................................................................................................157
10.1.1 Module Interconnectivity.............................................................................................................................157
10.2 Introduction...................................................................................................................................................................162
10.2.1 Features........................................................................................................................................................ 162
10.3 Functional description...................................................................................................................................................162
10.4 Memory map and register definition.............................................................................................................................162
10.4.1 TRGMUX0 Register Descriptions...............................................................................................................162
10.4.2 TRGMUX1 Register Descriptions...............................................................................................................201
10.5 Usage Guide..................................................................................................................................................................207
10.5.1 ADC Trigger Source.................................................................................................................................... 207
10.5.2 CMP Window/Sample Input .......................................................................................................................208
10.5.3 FTM Fault Detection Input / Hardware Triggers and Synchronization.......................................................208
Chapter 11
Direct Memory Access Multiplexer (DMAMUX)
11.1 Chip-specific information for this module....................................................................................................................209
11.1.1 Instantiation Information..............................................................................................................................209
11.2 Introduction...................................................................................................................................................................212
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11.2.1 Overview......................................................................................................................................................212
11.2.2 Features........................................................................................................................................................ 212
11.2.3 Modes of operation...................................................................................................................................... 213
11.3 External signal description............................................................................................................................................213
11.4 Memory map/register definition................................................................................................................................... 213
11.4.1
Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 214
11.5 Functional description...................................................................................................................................................215
11.5.1 DMA channels with periodic triggering capability......................................................................................215
11.5.2 DMA channels with no triggering capability...............................................................................................218
11.5.3 Always-enabled DMA sources.................................................................................................................... 218
11.6 Initialization/application information........................................................................................................................... 219
11.6.1 Reset.............................................................................................................................................................219
11.6.2 Enabling and configuring sources................................................................................................................219
Chapter 12
Enhanced Direct Memory Access (eDMA)
12.1 Introduction...................................................................................................................................................................223
12.1.1 eDMA system block diagram...................................................................................................................... 223
12.1.2 Block parts................................................................................................................................................... 224
12.1.3 Features........................................................................................................................................................ 225
12.2 Modes of operation....................................................................................................................................................... 226
12.3 Memory map/register definition................................................................................................................................... 227
12.3.1 TCD memory............................................................................................................................................... 227
12.3.2 TCD initialization........................................................................................................................................ 227
12.3.3 TCD structure...............................................................................................................................................227
12.3.4 Reserved memory and bit fields...................................................................................................................228
12.3.5 Control Register (DMA_CR).......................................................................................................................239
12.3.6 Error Status Register (DMA_ES)................................................................................................................ 242
12.3.7 Enable Request Register (DMA_ERQ)....................................................................................................... 244
12.3.8 Enable Error Interrupt Register (DMA_EEI)...............................................................................................246
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12.3.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 249
12.3.10 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 250
12.3.11 Clear Enable Request Register (DMA_CERQ)...........................................................................................250
12.3.12 Set Enable Request Register (DMA_SERQ)...............................................................................................251
12.3.13 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................252
12.3.14 Set START Bit Register (DMA_SSRT)...................................................................................................... 253
12.3.15 Clear Error Register (DMA_CERR)............................................................................................................254
12.3.16 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 255
12.3.17 Interrupt Request Register (DMA_INT)......................................................................................................256
12.3.18 Error Register (DMA_ERR)........................................................................................................................ 258
12.3.19 Hardware Request Status Register (DMA_HRS)........................................................................................ 261
12.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................264
12.3.21
Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 266
12.3.22
TCD Source Address (DMA_TCDn_SADDR)...........................................................................................267
12.3.23
TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................267
12.3.24
TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................268
12.3.25
TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 269
12.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................270
12.3.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 271
12.3.28
TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................272
12.3.29
TCD Destination Address (DMA_TCDn_DADDR)...................................................................................273
12.3.30
TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................273
12.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................274
12.3.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 275
12.3.33
TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 276
12.3.34
TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 277
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12.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................279
12.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 280
12.4 Functional description...................................................................................................................................................281
12.4.1 eDMA basic data flow................................................................................................................................. 281
12.4.2 Fault reporting and handling........................................................................................................................284
12.4.3 Channel preemption..................................................................................................................................... 287
12.4.4 Performance................................................................................................................................................. 287
12.5 Initialization/application information........................................................................................................................... 291
12.5.1 eDMA initialization..................................................................................................................................... 291
12.5.2 Programming errors..................................................................................................................................... 293
12.5.3 Arbitration mode considerations..................................................................................................................294
12.5.4 Performing DMA transfers.......................................................................................................................... 294
12.5.5 Monitoring transfer descriptor status........................................................................................................... 298
12.5.6 Channel Linking...........................................................................................................................................300
12.5.7 Dynamic programming................................................................................................................................ 301
12.5.8 Suspend/resume a DMA channel with active hardware service requests....................................................305
12.6 Usage Guide..................................................................................................................................................................306
Chapter 13
Memory and memory map
13.1 Introduction...................................................................................................................................................................307
13.2 Flash memory............................................................................................................................................................... 309
13.2.1 Flash memory types..................................................................................................................................... 309
13.2.2 Flash Memory Sizes.....................................................................................................................................309
13.3 SRAM memory.............................................................................................................................................................310
13.3.1 SRAM sizes..................................................................................................................................................310
13.3.2 SRAM retention in low power modes..........................................................................................................310
13.3.3 SRAM accesses............................................................................................................................................310
13.3.4 SRAM arbitration and priority control.........................................................................................................311
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13.4 System memory map.....................................................................................................................................................312
13.4.1 Aliased bit-band regions.............................................................................................................................. 313
13.5 Peripheral memory map................................................................................................................................................314
13.5.1 Peripheral Bridge (AIPS-Lite) Memory Map.............................................................................................. 315
13.6 Private Peripheral Bus (PPB) memory map..................................................................................................................318
Chapter 14
Local Memory Controller (LMEM)
14.1 Chip-specific information for this module....................................................................................................................321
14.1.1 Local memory controller region assignment............................................................................................... 321
14.2 Introduction...................................................................................................................................................................322
14.2.1 Block Diagram............................................................................................................................................. 322
14.2.2 Cache features..............................................................................................................................................323
14.3 Memory Map/Register Definition.................................................................................................................................325
14.3.1 Cache control register (LMEM_PCCCR)....................................................................................................325
14.3.2 Cache line control register (LMEM_PCCLCR).......................................................................................... 326
14.3.3 Cache search address register (LMEM_PCCSAR)..................................................................................... 329
14.3.4 Cache read/write value register (LMEM_PCCCVR).................................................................................. 330
14.3.5 Cache regions mode register (LMEM_PCCRMR)......................................................................................330
14.4 Functional Description..................................................................................................................................................333
14.4.1 LMEM Function.......................................................................................................................................... 333
14.4.2 SRAM Function........................................................................................................................................... 334
14.4.3 Cache Function............................................................................................................................................ 336
14.4.4 Cache Control.............................................................................................................................................. 337
Chapter 15
Miscellaneous System Control Module (MSCM)
15.1 Overview.......................................................................................................................................................................343
15.2 Chip Configuration and Boot........................................................................................................................................343
15.3 MSCM Memory Map/Register Definition....................................................................................................................344
15.3.1 CPU Configuration Memory Map and Registers.........................................................................................344
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15.3.2 Processor X Type Register (MSCM_CPxTYPE)........................................................................................ 345
15.3.3 Processor X Number Register (MSCM_CPxNUM)....................................................................................346
15.3.4 Processor X Master Register (MSCM_CPxMASTER)...............................................................................346
15.3.5 Processor X Count Register (MSCM_CPxCOUNT)...................................................................................347
15.3.6
Processor X Configuration Register (MSCM_CPxCFGn).......................................................................... 348
15.3.7 Processor 0 Type Register (MSCM_CP0TYPE).........................................................................................349
15.3.8 Processor 0 Number Register (MSCM_CP0NUM).....................................................................................350
15.3.9 Processor 0 Master Register (MSCM_CP0MASTER)................................................................................350
15.3.10 Processor 0 Count Register (MSCM_CP0COUNT)....................................................................................351
15.3.11
Processor 0 Configuration Register (MSCM_CP0CFGn)...........................................................................352
15.3.12
On-Chip Memory Descriptor Register (MSCM_OCMDRn)...................................................................... 353
Chapter 16
Flash Acceleration Unit (FAU)
16.1 Flash Acceleration Unit (FAU).....................................................................................................................................357
16.1.1 Introduction..................................................................................................................................................357
16.1.2 Modes of operation...................................................................................................................................... 357
16.1.3 External signal description...........................................................................................................................357
16.1.4 Functional description..................................................................................................................................357
16.2 Usage Guide..................................................................................................................................................................359
Chapter 17
Flash Memory Module (FTFE)
17.1 Chip-specific Information for this Module...................................................................................................................361
17.2 Introduction...................................................................................................................................................................361
17.2.1 Features........................................................................................................................................................ 362
17.2.2 Block diagram..............................................................................................................................................364
17.2.3 Glossary....................................................................................................................................................... 364
17.3 External signal description............................................................................................................................................367
17.4 Memory map and registers............................................................................................................................................367
17.4.1 Flash configuration field description........................................................................................................... 367
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17.4.2 Program flash 0 IFR map.............................................................................................................................368
17.4.3 Data flash 0 IFR map................................................................................................................................... 368
17.4.4 Register descriptions....................................................................................................................................371
17.5 Functional Description..................................................................................................................................................389
17.5.1 Flash Protection............................................................................................................................................389
17.5.2 Flash Access Protection............................................................................................................................... 391
17.5.3 FlexNVM Description..................................................................................................................................392
17.5.4 Interrupts...................................................................................................................................................... 396
17.5.5 Flash Operation in Low-Power Modes........................................................................................................ 397
17.5.6 Flash memory reads and ignored writes...................................................................................................... 397
17.5.7 Read while write (RWW)............................................................................................................................ 398
17.5.8 Flash Program and Erase..............................................................................................................................398
17.5.9 FTFE Command Operations........................................................................................................................ 398
17.5.10 Margin Read Commands............................................................................................................................. 405
17.5.11 Flash command descriptions........................................................................................................................406
17.5.12 Security........................................................................................................................................................ 431
17.6 Reset Sequence............................................................................................................................................................. 433
17.7 Usage Guide..................................................................................................................................................................434
Chapter 18
Clock Distribution
18.1 Introduction...................................................................................................................................................................435
18.2 High-level clocking diagram.........................................................................................................................................436
18.3 Clock definitions...........................................................................................................................................................436
18.4 Typical Clock Configuration........................................................................................................................................ 437
18.4.1 Default start-up clock...................................................................................................................................438
18.4.2 VLPR mode clocking...................................................................................................................................439
18.5 Clock Gating.................................................................................................................................................................439
18.6 Module clocks...............................................................................................................................................................439
18.6.1 LPO clock distribution.................................................................................................................................441
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18.6.2 EWM clocks.................................................................................................................................................441
18.6.3 WDOG Clocking Information..................................................................................................................... 441
18.6.4 ADC Clocking Information......................................................................................................................... 442
18.6.5 PDB Clock Options......................................................................................................................................443
18.6.6 FTM Clocking Information..........................................................................................................................443
18.6.7 LPTMR prescaler/glitch filter clocking options.......................................................................................... 444
18.6.8 RTC Clocking Information.......................................................................................................................... 444
18.6.9 FlexCAN Clocking Information.................................................................................................................. 445
18.6.10 Module Clocking Information for LPUART, LPSPI, LPI2C, FlexIO and LPIT.........................................445
Chapter 19
System Clock Generator (SCG)
19.1 Chip-specific information for this module....................................................................................................................447
19.1.1 Instantiation Information..............................................................................................................................447
19.2 Introduction...................................................................................................................................................................448
19.2.1 Features........................................................................................................................................................ 449
19.3 Memory Map/Register Definition.................................................................................................................................450
19.3.1 Version ID Register (SCG_VERID)............................................................................................................451
19.3.2 Parameter Register (SCG_PARAM)........................................................................................................... 451
19.3.3 Clock Status Register (SCG_CSR)..............................................................................................................452
19.3.4 Run Clock Control Register (SCG_RCCR).................................................................................................454
19.3.5 VLPR Clock Control Register (SCG_VCCR).............................................................................................457
19.3.6 HSRUN Clock Control Register (SCG_HCCR)..........................................................................................459
19.3.7 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG)...............................................................461
19.3.8 System OSC Control Status Register (SCG_SOSCCSR)............................................................................462
19.3.9 System OSC Divide Register (SCG_SOSCDIV)........................................................................................ 464
19.3.10 System Oscillator Configuration Register (SCG_SOSCCFG).................................................................... 465
19.3.11 Slow IRC Control Status Register (SCG_SIRCCSR)..................................................................................467
19.3.12 Slow IRC Divide Register (SCG_SIRCDIV).............................................................................................. 468
19.3.13 Slow IRC Configuration Register (SCG_SIRCCFG)..................................................................................469
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19.3.14 Fast IRC Control Status Register (SCG_FIRCCSR)................................................................................... 470
19.3.15 Fast IRC Divide Register (SCG_FIRCDIV)................................................................................................472
19.3.16 Fast IRC Configuration Register (SCG_FIRCCFG)................................................................................... 473
19.3.17 Fast IRC Trim Configuration Register (SCG_FIRCTCFG)........................................................................474
19.3.18 Fast IRC Status Register (SCG_FIRCSTAT)..............................................................................................475
19.3.19 System PLL Control Status Register (SCG_SPLLCSR)............................................................................. 476
19.3.20 System PLL Divide Register (SCG_SPLLDIV)..........................................................................................478
19.3.21 System PLL Configuration Register (SCG_SPLLCFG)............................................................................. 479
19.4 Functional description...................................................................................................................................................481
19.4.1 SCG Clock Mode Transitions......................................................................................................................481
Chapter 20
RTC Oscillator (OSC32)
20.1 Introduction...................................................................................................................................................................485
20.1.1 Features and Modes..................................................................................................................................... 485
20.1.2 Block Diagram............................................................................................................................................. 485
20.2 RTC Signal Descriptions.............................................................................................................................................. 486
20.2.1 EXTAL32 — Oscillator Input..................................................................................................................... 486
20.2.2 XTAL32 — Oscillator Output..................................................................................................................... 486
20.3 External Crystal Connections....................................................................................................................................... 487
20.4 Memory Map/Register Descriptions.............................................................................................................................487
20.4.1 RTC Oscillator Control Register (OSC32_CR)...........................................................................................487
20.5 Functional Description..................................................................................................................................................488
20.6 Reset Overview.............................................................................................................................................................489
20.7 Interrupts.......................................................................................................................................................................489
Chapter 21
Peripheral Clock Controller (PCC)
21.1 Chip-specific information for this module....................................................................................................................491
21.1.1 Information of PCC on this device.............................................................................................................. 491
21.2 Introduction...................................................................................................................................................................491
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21.2.1 Features........................................................................................................................................................ 491
21.3 Functional description...................................................................................................................................................492
21.4 Memory map and register definition.............................................................................................................................493
21.4.1 PCC Register Descriptions...........................................................................................................................493
Chapter 22
Reset and Boot
22.1 Introduction...................................................................................................................................................................551
22.2 Reset..............................................................................................................................................................................552
22.2.1 Power-on reset (POR).................................................................................................................................. 552
22.2.2 System resets................................................................................................................................................552
22.2.3 MCU Resets................................................................................................................................................. 556
22.2.4 Reset Pin ..................................................................................................................................................... 556
22.2.5 Debug resets.................................................................................................................................................557
22.3 Boot...............................................................................................................................................................................558
22.3.1 Boot options................................................................................................................................................. 558
22.3.2 Boot sequence.............................................................................................................................................. 560
Chapter 23
Kinetis ROM Bootloader
23.1 Chip-specific information for this module....................................................................................................................563
23.1.1 Boot ROM Configuration............................................................................................................................ 563
23.2 Introduction...................................................................................................................................................................564
23.3 Functional Description..................................................................................................................................................566
23.3.1 Memory Maps..............................................................................................................................................566
23.3.2 The Kinetis Bootloader Configuration Area (BCA)....................................................................................566
23.3.3 Start-up Process............................................................................................................................................568
23.3.4 Clock Configuration.....................................................................................................................................570
23.3.5 Bootloader Entry Point / API Tree...............................................................................................................571
23.3.6 Bootloader Protocol..................................................................................................................................... 572
23.3.7 Bootloader Packet Types............................................................................................................................. 577
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23.3.8 Bootloader Command API...........................................................................................................................583
23.3.9 Bootloader Exit state....................................................................................................................................598
23.4 Kinetis Flash Driver API.............................................................................................................................................. 598
23.4.1 Flash Driver Entry Point.............................................................................................................................. 598
23.4.2 Flash driver API Tree...................................................................................................................................599
23.4.3 Quick demo using Kinetis Flash Driver API............................................................................................... 600
23.4.4 Flash driver data structures.......................................................................................................................... 601
23.4.5 Flash driver API...........................................................................................................................................602
23.5 Peripherals Supported................................................................................................................................................... 616
23.5.1 I2C Peripheral.............................................................................................................................................. 616
23.5.2 SPI Peripheral.............................................................................................................................................. 618
23.5.3 UART Peripheral......................................................................................................................................... 621
23.5.4 FlexCAN Peripheral.....................................................................................................................................623
23.6 Get/SetProperty Command Properties..........................................................................................................................625
23.6.1 Property Definitions.....................................................................................................................................627
23.7 Verifying the application in flash using CRC-32......................................................................................................... 628
23.8 Kinetis Bootloader Status Error Codes.........................................................................................................................629
Chapter 24
Reset Control Module (RCM)
24.1 Chip-specific information for this module....................................................................................................................631
24.1.1 Instantiation Information..............................................................................................................................631
24.2 Introduction...................................................................................................................................................................631
24.3 Reset memory map and register descriptions............................................................................................................... 632
24.3.1 Version ID Register (RCM_VERID)...........................................................................................................632
24.3.2 Parameter Register (RCM_PARAM).......................................................................................................... 634
24.3.3 System Reset Status Register (RCM_SRS)................................................................................................. 636
24.3.4 Reset Pin Control register (RCM_RPC)...................................................................................................... 639
24.3.5 Mode Register (RCM_MR)......................................................................................................................... 640
24.3.6 Force Mode Register (RCM_FM)................................................................................................................641
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Section number Title Page
24.3.7 Sticky System Reset Status Register (RCM_SSRS)....................................................................................642
24.3.8 System Reset Interrupt Enable Register (RCM_SRIE)............................................................................... 644
Chapter 25
Power Management
25.1 Introduction...................................................................................................................................................................647
25.2 Power Modes Description.............................................................................................................................................648
25.2.1 Run mode..................................................................................................................................................... 649
25.2.2 Wait mode....................................................................................................................................................651
25.2.3 Stop mode.................................................................................................................................................... 651
25.2.4 Power domains.............................................................................................................................................653
25.2.5 Entering and exiting power modes...............................................................................................................654
25.3 Power mode transitions.................................................................................................................................................655
25.4 Power modes shutdown sequencing............................................................................................................................. 656
25.5 Module operation in low power modes........................................................................................................................ 656
25.5.1 Peripheral doze.............................................................................................................................................659
25.6 Low-power wake-up sources........................................................................................................................................ 660
25.7 Power supply supervisor...............................................................................................................................................660
Chapter 26
System Mode Controller (SMC)
26.1 Chip-specific information for this module....................................................................................................................663
26.1.1 Instantiation Information..............................................................................................................................663
26.2 Introduction...................................................................................................................................................................663
26.3 Modes of operation....................................................................................................................................................... 664
26.4 Memory map and register descriptions.........................................................................................................................665
26.4.1 SMC Version ID Register (SMC_VERID)..................................................................................................666
26.4.2 SMC Parameter Register (SMC_PARAM)................................................................................................. 667
26.4.3 Power Mode Protection register (SMC_PMPROT).....................................................................................668
26.4.4 Power Mode Control register (SMC_PMCTRL).........................................................................................669
26.4.5 Stop Control Register (SMC_STOPCTRL).................................................................................................671
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Section number Title Page
26.4.6 Power Mode Status register (SMC_PMSTAT)........................................................................................... 673
26.5 Functional description...................................................................................................................................................673
26.5.1 Power mode transitions................................................................................................................................674
26.5.2 Power mode entry/exit sequencing.............................................................................................................. 675
26.5.3 Run modes....................................................................................................................................................677
26.5.4 Wait modes.................................................................................................................................................. 679
26.5.5 Stop modes...................................................................................................................................................680
26.5.6 Debug in low power modes......................................................................................................................... 682
Chapter 27
Power Management Controller (PMC)
27.1 Chip-specific Information for this Module...................................................................................................................683
27.2 Introduction...................................................................................................................................................................683
27.3 Features.........................................................................................................................................................................683
27.4 Modes of Operation...................................................................................................................................................... 683
27.4.1 Full Performance Mode (FPM)....................................................................................................................684
27.4.2 Low Power Mode (LPM).............................................................................................................................684
27.5 Low Voltage Detect (LVD) System............................................................................................................................. 684
27.5.1 Low Voltage Reset (LVR) Operation.......................................................................................................... 685
27.5.2 LVD Interrupt Operation............................................................................................................................. 685
27.5.3 Low-voltage warning (LVW) interrupt operation....................................................................................... 685
27.6 Memory Map and Register Definition..........................................................................................................................686
27.6.1 Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)........................................................686
27.6.2 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)........................................................687
27.6.3 Regulator Status and Control Register (PMC_REGSC)..............................................................................688
27.6.4 Low Power Oscillator Trim Register (PMC_LPOTRIM)........................................................................... 689
Chapter 28
Security
28.1 Introduction...................................................................................................................................................................691
28.2 Flash security feature summary.................................................................................................................................... 691
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28.2.1 Flash security byte....................................................................................................................................... 691
28.2.2 Flash access protection (FAC)..................................................................................................................... 692
28.3 Security hardware accelerators..................................................................................................................................... 692
28.3.1 CRC..............................................................................................................................................................692
28.4 General security features...............................................................................................................................................693
28.4.1 Unique ID.....................................................................................................................................................693
28.4.2 Program Once Field..................................................................................................................................... 693
28.5 On-chip resource access control mechanism................................................................................................................ 693
Chapter 29
External Watchdog Monitor (EWM)
29.1 Introduction...................................................................................................................................................................695
29.1.1 Features........................................................................................................................................................ 695
29.1.2 Modes of Operation..................................................................................................................................... 696
29.1.3 Block Diagram............................................................................................................................................. 697
29.2 EWM Signal Descriptions............................................................................................................................................ 698
29.3 Memory Map/Register Definition.................................................................................................................................698
29.3.1 Control Register (EWM_CTRL)................................................................................................................. 698
29.3.2 Service Register (EWM_SERV)..................................................................................................................699
29.3.3 Compare Low Register (EWM_CMPL)......................................................................................................699
29.3.4 Compare High Register (EWM_CMPH).....................................................................................................700
29.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................701
29.4 Functional Description..................................................................................................................................................701
29.4.1 The EWM_out Signal.................................................................................................................................. 701
29.4.2 The EWM_in Signal.................................................................................................................................... 702
29.4.3 EWM Counter..............................................................................................................................................703
29.4.4 EWM Compare Registers............................................................................................................................ 703
29.4.5 EWM Refresh Mechanism...........................................................................................................................703
29.4.6 EWM Interrupt.............................................................................................................................................704
29.4.7 Counter clock prescaler................................................................................................................................704
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