Section number Title Page
8.1 Chip-specific information for this module....................................................................................................................115
8.1.1 Instantiation Information..............................................................................................................................115
8.2 Introduction...................................................................................................................................................................116
8.3 Overview.......................................................................................................................................................................116
8.3.1 Block diagram..............................................................................................................................................116
8.3.2 Features........................................................................................................................................................ 117
8.4 Memory map/register definition................................................................................................................................... 118
8.4.1 Control/Error Status Register (MPU_CESR).............................................................................................. 120
8.4.2
Error Address Register, slave port n (MPU_EARn)....................................................................................121
8.4.3
Error Detail Register, slave port n (MPU_EDRn)....................................................................................... 122
8.4.4
Region Descriptor n, Word 0 (MPU_RGDn_WORD0).............................................................................. 123
8.4.5
Region Descriptor n, Word 1 (MPU_RGDn_WORD1).............................................................................. 124
8.4.6
Region Descriptor n, Word 2 (MPU_RGDn_WORD2).............................................................................. 124
8.4.7
Region Descriptor n, Word 3 (MPU_RGDn_WORD3).............................................................................. 127
8.4.8
Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................128
8.5 Functional description...................................................................................................................................................130
8.5.1 Access evaluation macro..............................................................................................................................130
8.5.2 Putting it all together and error terminations............................................................................................... 132
8.5.3 Power management......................................................................................................................................133
8.6 Initialization information.............................................................................................................................................. 133
8.7 Application information................................................................................................................................................133
8.8 Usage Guide..................................................................................................................................................................135
8.8.1 MPU Access Violation Indications..............................................................................................................135
8.8.2 Reset Values for RGD0 Registers................................................................................................................136
8.8.3 Write Access Restrictions for RGD0 Registers........................................................................................... 136
Chapter 9
Peripheral Bridge (AIPS-Lite)
9.1 Chip-specific information for this module....................................................................................................................139
9.1.1 Peripheral slot assignment........................................................................................................................... 139
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
6 NXP Semiconductors