Freescale Semiconductor MK22FN256VMP12 Reference guide

Brand: Freescale Semiconductor

Model: MK22FN256VMP12

Type: Reference guide

This manual is also suitable for

K22F Sub-Family Reference Manual

Supports: MK22FN256VDC12, MK22FN256VLL12,

MK22FN256VMP12, MK22FN256VLH12

Document Number: K22P121M120SF8RM

Rev. 3, 7/2014

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Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................47

1.1.1 Purpose.........................................................................................................................................................47

1.1.2 Audience......................................................................................................................................................47

1.2 Conventions..................................................................................................................................................................47

1.2.1 Numbering systems......................................................................................................................................47

1.2.2 Typographic notation...................................................................................................................................48

1.2.3 Special terms................................................................................................................................................48

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................49

2.2 Module Functional Categories......................................................................................................................................49

2.2.1 ARM® Cortex®-M4 Core Modules............................................................................................................50

2.2.2 System Modules...........................................................................................................................................51

2.2.3 Memories and Memory Interfaces...............................................................................................................52

2.2.4 Clocks...........................................................................................................................................................52

2.2.5 Security and Integrity modules....................................................................................................................52

2.2.6 Analog modules...........................................................................................................................................53

2.2.7 Timer modules.............................................................................................................................................53

2.2.8 Communication interfaces...........................................................................................................................54

2.2.9 Human-machine interfaces..........................................................................................................................55

2.3 Orderable part numbers.................................................................................................................................................55

Chapter 3

Chip Configuration

3.1 Introduction...................................................................................................................................................................57

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3.2 Core modules................................................................................................................................................................57

3.2.1 ARM Cortex-M4 Core Configuration..........................................................................................................57

3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................59

3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration.........................................................65

3.2.4 FPU Configuration.......................................................................................................................................66

3.2.5 JTAG Controller Configuration...................................................................................................................66

3.3 System modules............................................................................................................................................................67

3.3.1 SIM Configuration.......................................................................................................................................67

3.3.2 System Mode Controller (SMC) Configuration...........................................................................................68

3.3.3 PMC Configuration......................................................................................................................................68

3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................69

3.3.5 MCM Configuration....................................................................................................................................71

3.3.6 Crossbar-Light Switch Configuration..........................................................................................................71

3.3.7 Peripheral Bridge Configuration..................................................................................................................73

3.3.8 DMA request multiplexer configuration......................................................................................................74

3.3.9 DMA Controller Configuration...................................................................................................................77

3.3.10 External Watchdog Monitor (EWM) Configuration....................................................................................78

3.3.11 Watchdog Configuration..............................................................................................................................80

3.4 Clock modules..............................................................................................................................................................81

3.4.1 MCG Configuration.....................................................................................................................................81

3.4.2 OSC Configuration......................................................................................................................................82

3.4.3 RTC OSC configuration...............................................................................................................................83

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3.5 Memories and memory interfaces.................................................................................................................................84

3.5.1 Flash Memory Configuration.......................................................................................................................84

3.5.2 Flash Memory Controller Configuration.....................................................................................................87

3.5.3 SRAM Configuration...................................................................................................................................87

3.5.4 System Register File Configuration.............................................................................................................89

3.5.5 VBAT Register File Configuration..............................................................................................................90

3.5.6 EzPort Configuration...................................................................................................................................90

3.6 Security.........................................................................................................................................................................91

3.6.1 CRC Configuration......................................................................................................................................92

3.6.2 RNG Configuration......................................................................................................................................92

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3.7 Analog...........................................................................................................................................................................93

3.7.1 16-bit SAR ADC Configuration..................................................................................................................93

3.7.2 CMP Configuration......................................................................................................................................101

3.7.3 12-bit DAC Configuration...........................................................................................................................103

3.7.4 VREF Configuration....................................................................................................................................104

3.8 Timers...........................................................................................................................................................................105

3.8.1 PDB Configuration......................................................................................................................................105

3.8.2 FlexTimer Configuration.............................................................................................................................108

3.8.3 PIT Configuration........................................................................................................................................114

3.8.4 Low-power timer configuration...................................................................................................................115

3.8.5 RTC configuration.......................................................................................................................................117

3.9 Communication interfaces............................................................................................................................................118

3.9.1 Universal Serial Bus (USB) FS Subsystem.................................................................................................118

3.9.2 SPI configuration.........................................................................................................................................123

3.9.3 I2C Configuration........................................................................................................................................127

3.9.4 UART Configuration...................................................................................................................................128

3.9.5 LPUART configuration................................................................................................................................130

3.9.6 I2S configuration..........................................................................................................................................131

3.10 Human-machine interfaces...........................................................................................................................................134

3.10.1 GPIO configuration......................................................................................................................................134

Chapter 4

Memory Map

4.1 Introduction...................................................................................................................................................................137

4.2 System memory map.....................................................................................................................................................137

4.2.1 Aliased bit-band regions..............................................................................................................................138

4.2.2 Flash Access Control Introduction...............................................................................................................140

4.3 Flash Memory Map.......................................................................................................................................................140

4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................141

4.4 SRAM memory map.....................................................................................................................................................141

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4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................141

4.5.1 Read-after-write sequence and required serialization of memory operations..............................................142

4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................142

4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................146

Chapter 5

Clock Distribution

5.1 Introduction...................................................................................................................................................................147

5.2 Programming model......................................................................................................................................................147

5.3 High-Level device clocking diagram............................................................................................................................147

5.4 Clock definitions...........................................................................................................................................................148

5.4.1 Device clock summary.................................................................................................................................149

5.5 Internal clocking requirements.....................................................................................................................................152

5.5.1 Clock divider values after reset....................................................................................................................153

5.5.2 VLPR mode clocking...................................................................................................................................153

5.6 Clock Gating.................................................................................................................................................................154

5.7 Module clocks...............................................................................................................................................................154

5.7.1 PMC 1-kHz LPO clock................................................................................................................................156

5.7.2 IRC 48MHz clock........................................................................................................................................156

5.7.3 WDOG clocking..........................................................................................................................................157

5.7.4 Debug trace clock.........................................................................................................................................157

5.7.5 PORT digital filter clocking.........................................................................................................................158

5.7.6 LPTMR clocking..........................................................................................................................................158

5.7.7 RTC_CLKOUT and CLKOUT32K clocking..............................................................................................159

5.7.8 USB FS OTG Controller clocking...............................................................................................................160

5.7.9 UART clocking............................................................................................................................................161

5.7.10 LPUART0 clocking.....................................................................................................................................161

5.7.11 I2S/SAI clocking..........................................................................................................................................162

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Chapter 6

Reset and Boot

6.1 Introduction...................................................................................................................................................................165

6.2 Reset..............................................................................................................................................................................166

6.2.1 Power-on reset (POR)..................................................................................................................................166

6.2.2 System reset sources....................................................................................................................................166

6.2.3 MCU Resets.................................................................................................................................................170

6.2.4 Reset Pin .....................................................................................................................................................171

6.2.5 Debug resets.................................................................................................................................................172

6.3 Boot...............................................................................................................................................................................173

6.3.1 Boot sources.................................................................................................................................................173

6.3.2 Boot options.................................................................................................................................................173

6.3.3 FOPT boot options.......................................................................................................................................174

6.3.4 Boot sequence..............................................................................................................................................175

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................177

7.2 Clocking modes............................................................................................................................................................177

7.2.1 Partial Stop...................................................................................................................................................177

7.2.2 DMA Wakeup..............................................................................................................................................178

7.2.3 Compute Operation......................................................................................................................................179

7.2.4 Peripheral Doze............................................................................................................................................180

7.2.5 Clock Gating................................................................................................................................................181

7.3 Power Modes Description.............................................................................................................................................181

7.4 Entering and exiting power modes...............................................................................................................................183

7.5 Power mode transitions.................................................................................................................................................184

7.6 Power modes shutdown sequencing.............................................................................................................................185

7.7 Flash Program Restrictions...........................................................................................................................................186

7.8 Module Operation in Low Power Modes......................................................................................................................186

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Chapter 8

Security

8.1 Introduction...................................................................................................................................................................191

8.2 Flash Security...............................................................................................................................................................191

8.3 Security Interactions with other Modules.....................................................................................................................192

8.3.1 Security Interactions with EzPort................................................................................................................192

8.3.2 Security Interactions with Debug.................................................................................................................192

Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................193

9.1.1 References....................................................................................................................................................195

9.2 The Debug Port.............................................................................................................................................................195

9.2.1 JTAG-to-SWD change sequence.................................................................................................................196

9.2.2 JTAG-to-cJTAG change sequence...............................................................................................................196

9.3 Debug Port Pin Descriptions.........................................................................................................................................197

9.4 System TAP connection................................................................................................................................................197

9.4.1 IR Codes.......................................................................................................................................................197

9.5 JTAG status and control registers.................................................................................................................................198

9.5.1 MDM-AP Control Register..........................................................................................................................199

9.5.2 MDM-AP Status Register............................................................................................................................201

9.6 Debug Resets................................................................................................................................................................202

9.7 AHB-AP........................................................................................................................................................................203

9.8 ITM...............................................................................................................................................................................203

9.9 Core Trace Connectivity...............................................................................................................................................204

9.10 TPIU..............................................................................................................................................................................204

9.11 DWT.............................................................................................................................................................................204

9.12 Debug in Low Power Modes........................................................................................................................................205

9.12.1 Debug Module State in Low Power Modes.................................................................................................205

9.13 Debug & Security.........................................................................................................................................................206

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Chapter 10

Signal Multiplexing and Signal Descriptions

10.1 Introduction...................................................................................................................................................................207

10.2 Signal Multiplexing Integration....................................................................................................................................207

10.2.1 Port control and interrupt module features..................................................................................................208

10.2.2 Clock gating.................................................................................................................................................209

10.2.3 Signal multiplexing constraints....................................................................................................................209

10.3 Pinout............................................................................................................................................................................209

10.3.1 K22F Signal Multiplexing and Pin Assignments.........................................................................................209

10.3.2 K22F Pinouts................................................................................................................................................214

10.4 Module Signal Description Tables................................................................................................................................218

10.4.1 Core Modules...............................................................................................................................................218

10.4.2 System Modules...........................................................................................................................................219

10.4.3 Clock Modules.............................................................................................................................................219

10.4.4 Memories and Memory Interfaces...............................................................................................................220

10.4.5 Analog..........................................................................................................................................................220

10.4.6 Timer Modules.............................................................................................................................................221

10.4.7 Communication Interfaces...........................................................................................................................223

10.4.8 Human-Machine Interfaces (HMI)..............................................................................................................225

Chapter 11

Port Control and Interrupts (PORT)

11.1 Introduction...................................................................................................................................................................227

11.2 Overview.......................................................................................................................................................................227

11.2.1 Features........................................................................................................................................................227

11.2.2 Modes of operation......................................................................................................................................228

11.3 External signal description............................................................................................................................................229

11.4 Detailed signal description............................................................................................................................................229

11.5 Memory map and register definition.............................................................................................................................229

11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................236

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11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................238

11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................239

11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................240

11.5.5 Digital Filter Enable Register (PORTx_DFER)...........................................................................................240

11.5.6 Digital Filter Clock Register (PORTx_DFCR)............................................................................................241

11.5.7 Digital Filter Width Register (PORTx_DFWR)..........................................................................................241

11.6 Functional description...................................................................................................................................................242

11.6.1 Pin control....................................................................................................................................................242

11.6.2 Global pin control........................................................................................................................................243

11.6.3 External interrupts........................................................................................................................................243

11.6.4 Digital filter..................................................................................................................................................244

Chapter 12

System Integration Module (SIM)

12.1 Introduction...................................................................................................................................................................247

12.1.1 Features........................................................................................................................................................247

12.2 Memory map and register definition.............................................................................................................................248

12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................249

12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................251

12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................252

12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................254

12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................257

12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................258

12.2.7 System Options Register 8 (SIM_SOPT8)..................................................................................................260

12.2.8 System Device Identification Register (SIM_SDID)...................................................................................262

12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................264

12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................266

12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................267

12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................270

12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................271

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12.2.14 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................273

12.2.15 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................274

12.2.16 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................276

12.2.17 Unique Identification Register High (SIM_UIDH).....................................................................................277

12.2.18 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................277

12.2.19 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................278

12.2.20 Unique Identification Register Low (SIM_UIDL)......................................................................................278

12.3 Functional description...................................................................................................................................................278

Chapter 13

Kinetis Flashloader

13.1 Chip-Specific Information............................................................................................................................................279

13.2 Introduction...................................................................................................................................................................279

13.3 Functional Description..................................................................................................................................................281

13.3.1 Memory Maps..............................................................................................................................................281

13.3.2 Kinetis Flashloader......................................................................................................................................281

13.3.3 Start-up Process............................................................................................................................................282

13.3.4 Clock Configuration.....................................................................................................................................283

13.3.5 Flashloader Protocol....................................................................................................................................283

13.3.6 Flashloader Packet Types.............................................................................................................................288

13.3.7 Flashloader Command API..........................................................................................................................295

13.3.8 Flashloader Exit state...................................................................................................................................313

13.4 Peripherals Supported...................................................................................................................................................315

13.4.1 I2C Peripheral..............................................................................................................................................315

13.4.2 SPI Peripheral..............................................................................................................................................316

13.4.3 UART Peripheral.........................................................................................................................................318

13.4.4 USB peripheral.............................................................................................................................................321

13.5 Get/SetProperty Command Properties..........................................................................................................................323

13.5.1 Property Definitions.....................................................................................................................................324

13.6 Kinetis Flashloader Status Error Codes........................................................................................................................326

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Chapter 14

Reset Control Module (RCM)

14.1 Introduction...................................................................................................................................................................329

14.2 Reset memory map and register descriptions...............................................................................................................329

14.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................330

14.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................331

14.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................333

14.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................334

14.2.5 Mode Register (RCM_MR).........................................................................................................................335

14.2.6 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................336

14.2.7 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................337

Chapter 15

System Mode Controller (SMC)

15.1 Introduction...................................................................................................................................................................339

15.2 Modes of operation.......................................................................................................................................................339

15.3 Memory map and register descriptions.........................................................................................................................341

15.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................342

15.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................343

15.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................345

15.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................346

15.4 Functional description...................................................................................................................................................347

15.4.1 Power mode transitions................................................................................................................................347

15.4.2 Power mode entry/exit sequencing..............................................................................................................350

15.4.3 Run modes....................................................................................................................................................352

15.4.4 Wait modes..................................................................................................................................................354

15.4.5 Stop modes...................................................................................................................................................355

15.4.6 Debug in low power modes.........................................................................................................................358

Chapter 16

Power Management Controller (PMC)

16.1 Introduction...................................................................................................................................................................361

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16.2 Features.........................................................................................................................................................................361

16.3 Low-voltage detect (LVD) system................................................................................................................................361

16.3.1 LVD reset operation.....................................................................................................................................362

16.3.2 LVD interrupt operation...............................................................................................................................362

16.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................362

16.4 I/O retention..................................................................................................................................................................363

16.5 Memory map and register descriptions.........................................................................................................................363

16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................364

16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................365

16.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................366

Chapter 17

Low-Leakage Wakeup Unit (LLWU)

17.1 Introduction...................................................................................................................................................................369

17.1.1 Features........................................................................................................................................................369

17.1.2 Modes of operation......................................................................................................................................370

17.1.3 Block diagram..............................................................................................................................................371

17.2 LLWU signal descriptions............................................................................................................................................372

17.3 Memory map/register definition...................................................................................................................................372

17.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................373

17.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................374

17.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................375

17.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................376

17.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................377

17.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................379

17.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................381

17.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................382

17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................384

17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................385

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17.4 Functional description...................................................................................................................................................386

17.4.1 LLS mode.....................................................................................................................................................387

17.4.2 VLLS modes................................................................................................................................................387

17.4.3 Initialization.................................................................................................................................................387

Chapter 18

Miscellaneous Control Module (MCM)

18.1 Introduction...................................................................................................................................................................389

18.1.1 Features........................................................................................................................................................389

18.2 Memory map/register descriptions...............................................................................................................................389

18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................390

18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................390

18.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR).....................................................................391

18.2.4 Interrupt Status and Control Register (MCM_ISCR)..................................................................................392

18.2.5 Compute Operation Control Register (MCM_CPO)...................................................................................395

18.3 Functional description...................................................................................................................................................396

18.3.1 Interrupts......................................................................................................................................................396

Chapter 19

Crossbar Switch Lite (AXBS-Lite)

19.1 Introduction...................................................................................................................................................................397

19.1.1 Features........................................................................................................................................................397

19.2 Memory Map / Register Definition...............................................................................................................................398

19.3 Functional Description..................................................................................................................................................398

19.3.1 General operation.........................................................................................................................................398

19.3.2 Arbitration....................................................................................................................................................399

19.4 Initialization/application information...........................................................................................................................400

Chapter 20

Peripheral Bridge (AIPS-Lite)

20.1 Introduction...................................................................................................................................................................403

20.1.1 Features........................................................................................................................................................403

20.1.2 General operation.........................................................................................................................................403

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20.2 Functional description...................................................................................................................................................404

20.2.1 Access support.............................................................................................................................................404

Chapter 21

Direct Memory Access Multiplexer (DMAMUX)

21.1 Introduction...................................................................................................................................................................405

21.1.1 Overview......................................................................................................................................................405

21.1.2 Features........................................................................................................................................................406

21.1.3 Modes of operation......................................................................................................................................406

21.2 External signal description............................................................................................................................................407

21.3 Memory map/register definition...................................................................................................................................407

21.3.1 Channel Configuration register (DMAMUX_CHCFGn)............................................................................408

21.4 Functional description...................................................................................................................................................409

21.4.1 DMA channels with periodic triggering capability......................................................................................409

21.4.2 DMA channels with no triggering capability...............................................................................................411

21.4.3 Always-enabled DMA sources....................................................................................................................411

21.5 Initialization/application information...........................................................................................................................413

21.5.1 Reset.............................................................................................................................................................413

21.5.2 Enabling and configuring sources................................................................................................................413

Chapter 22

Enhanced Direct Memory Access (eDMA)

22.1 Introduction...................................................................................................................................................................417

22.1.1 eDMA system block diagram......................................................................................................................417

22.1.2 Block parts...................................................................................................................................................418

22.1.3 Features........................................................................................................................................................419

22.2 Modes of operation.......................................................................................................................................................421

22.3 Memory map/register definition...................................................................................................................................421

22.3.1 TCD memory...............................................................................................................................................421

22.3.2 TCD initialization........................................................................................................................................422

22.3.3 TCD structure...............................................................................................................................................422

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22.3.4 Reserved memory and bit fields...................................................................................................................424

22.3.1 Control Register (DMA_CR).......................................................................................................................434

22.3.2 Error Status Register (DMA_ES)................................................................................................................437

22.3.3 Enable Request Register (DMA_ERQ).......................................................................................................439

22.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................441

22.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................................................................................443

22.3.6 Set Enable Error Interrupt Register (DMA_SEEI)......................................................................................444

22.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................445

22.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................446

22.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................447

22.3.10 Set START Bit Register (DMA_SSRT)......................................................................................................448

22.3.11 Clear Error Register (DMA_CERR)............................................................................................................449

22.3.12 Clear Interrupt Request Register (DMA_CINT).........................................................................................450

22.3.13 Interrupt Request Register (DMA_INT)......................................................................................................451

22.3.14 Error Register (DMA_ERR)........................................................................................................................453

22.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................456

22.3.16 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................459

22.3.17 Channel n Priority Register (DMA_DCHPRIn)..........................................................................................461

22.3.18 TCD Source Address (DMA_TCDn_SADDR)...........................................................................................462

22.3.19 TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................462

22.3.20 TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................463

22.3.21 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO).................................464

22.3.22 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)

(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................465

22.3.23 TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)

(DMA_TCDn_NBYTES_MLOFFYES).....................................................................................................466

22.3.24 TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................467

22.3.25 TCD Destination Address (DMA_TCDn_DADDR)...................................................................................468

22.3.26 TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................468

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22.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_CITER_ELINKYES)...........................................................................................................469

22.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_CITER_ELINKNO)............................................................................................................470

22.3.29 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)..........471

22.3.30 TCD Control and Status (DMA_TCDn_CSR)............................................................................................472

22.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_BITER_ELINKYES)...........................................................................................................474

22.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_BITER_ELINKNO)............................................................................................................475

22.4 Functional description...................................................................................................................................................476

22.4.1 eDMA basic data flow.................................................................................................................................476

22.4.2 Fault reporting and handling........................................................................................................................479

22.4.3 Channel preemption.....................................................................................................................................481

22.4.4 Performance.................................................................................................................................................481

22.5 Initialization/application information...........................................................................................................................486

22.5.1 eDMA initialization.....................................................................................................................................486

22.5.2 Programming errors.....................................................................................................................................488

22.5.3 Arbitration mode considerations..................................................................................................................488

22.5.4 Performing DMA transfers..........................................................................................................................489

22.5.5 Monitoring transfer descriptor status...........................................................................................................493

22.5.6 Channel Linking...........................................................................................................................................495

22.5.7 Dynamic programming................................................................................................................................496

Chapter 23

External Watchdog Monitor (EWM)

23.1 Introduction...................................................................................................................................................................501

23.1.1 Features........................................................................................................................................................501

23.1.2 Modes of Operation.....................................................................................................................................502

23.1.3 Block Diagram.............................................................................................................................................503

23.2 EWM Signal Descriptions............................................................................................................................................504

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23.3 Memory Map/Register Definition.................................................................................................................................504

23.3.1 Control Register (EWM_CTRL).................................................................................................................504

23.3.2 Service Register (EWM_SERV)..................................................................................................................505

23.3.3 Compare Low Register (EWM_CMPL)......................................................................................................505

23.3.4 Compare High Register (EWM_CMPH).....................................................................................................506

23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)................................................................................507

23.4 Functional Description..................................................................................................................................................507

23.4.1 The EWM_out Signal..................................................................................................................................507

23.4.2 The EWM_in Signal....................................................................................................................................508

23.4.3 EWM Counter..............................................................................................................................................509

23.4.4 EWM Compare Registers............................................................................................................................509

23.4.5 EWM Refresh Mechanism...........................................................................................................................509

23.4.6 EWM Interrupt.............................................................................................................................................510

23.4.7 Counter clock prescaler................................................................................................................................510

Chapter 24

Watchdog Timer (WDOG)

24.1 Introduction...................................................................................................................................................................511

24.2 Features.........................................................................................................................................................................511

24.3 Functional overview......................................................................................................................................................513

24.3.1 Unlocking and updating the watchdog.........................................................................................................514

24.3.2 Watchdog configuration time (WCT)..........................................................................................................515

24.3.3 Refreshing the watchdog..............................................................................................................................516

24.3.4 Windowed mode of operation......................................................................................................................516

24.3.5 Watchdog disabled mode of operation.........................................................................................................516

24.3.6 Debug modes of operation...........................................................................................................................517

24.4 Testing the watchdog....................................................................................................................................................517

24.4.1 Quick test.....................................................................................................................................................518

24.4.2 Byte test........................................................................................................................................................518

24.5 Backup reset generator..................................................................................................................................................519

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24.6 Generated resets and interrupts.....................................................................................................................................520

24.7 Memory map and register definition.............................................................................................................................520

24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)...........................................................521

24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL)............................................................523

24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH).................................................................523

24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)..................................................................524

24.7.5 Watchdog Window Register High (WDOG_WINH)..................................................................................524

24.7.6 Watchdog Window Register Low (WDOG_WINL)...................................................................................525

24.7.7 Watchdog Refresh register (WDOG_REFRESH).......................................................................................525

24.7.8 Watchdog Unlock register (WDOG_UNLOCK).........................................................................................525

24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH).................................................................526

24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..................................................................526

24.7.11 Watchdog Reset Count register (WDOG_RSTCNT)..................................................................................527

24.7.12 Watchdog Prescaler register (WDOG_PRESC)..........................................................................................527

24.8 Watchdog operation with 8-bit access..........................................................................................................................527

24.8.1 General guideline.........................................................................................................................................527

24.8.2 Refresh and unlock operations with 8-bit access.........................................................................................528

24.9 Restrictions on watchdog operation..............................................................................................................................529

Chapter 25

Multipurpose Clock Generator (MCG)

25.1 Introduction...................................................................................................................................................................531

25.1.1 Features........................................................................................................................................................531

25.1.2 Modes of Operation.....................................................................................................................................535

25.2 External Signal Description..........................................................................................................................................535

25.3 Memory Map/Register Definition.................................................................................................................................535

25.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................536

25.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................537

25.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................538

25.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................539

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