Kinetis KE1xZ64 Sub-Family
Reference Manual
Supports: MKE1xZ64VLF4, MKE1xZ64VLD4, MKE1xZ32VLF4,
MKE1xZ32VLD4
Document Number: KE1xZP48M48SF0RM
Rev. 2, 01/2019
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Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 39
1.2 Organization..................................................................................................................................................................39
1.3 Module descriptions......................................................................................................................................................39
1.3.1 Example: chip-specific information that supersedes content in the same chapter.........................................40
1.3.2 Example: chip-specific information that refers to a different chapter........................................................... 41
1.4 Register descriptions.....................................................................................................................................................42
1.5 Conventions.................................................................................................................................................................. 43
1.5.1 Numbering systems........................................................................................................................................43
1.5.2 Typographic notation..................................................................................................................................... 43
1.5.3 Special terms..................................................................................................................................................44
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................45
2.2 Block Diagram..............................................................................................................................................................45
2.3 Module Functional Categories......................................................................................................................................46
Chapter 3
Core Overview
3.1 ARM Cortex-M0+ ....................................................................................................................................................... 49
3.2 Core Buses and Interfaces.............................................................................................................................................50
3.3 Core Component Configuration....................................................................................................................................51
3.4 SysTick Clock Configuration....................................................................................................................................... 51
Chapter 4
Interrupts
4.1 Introduction...................................................................................................................................................................53
4.2 NVIC configuration...................................................................................................................................................... 53
4.2.1 Interrupt priority levels.................................................................................................................................. 53
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4.2.2 Non-maskable interrupt..................................................................................................................................54
4.3 Interrupt channel assignments.......................................................................................................................................54
4.3.1 Determining the bitfield and register location for configuring a particular interrupt.................................... 56
Chapter 5
System Integration Module (SIM)
5.1 Introduction...................................................................................................................................................................59
5.1.1 Features.......................................................................................................................................................... 59
5.2 Memory map and register definition.............................................................................................................................59
5.2.1 Chip Control register (SIM_CHIPCTL)........................................................................................................ 60
5.2.2 FTM Option Register 0 (SIM_FTMOPT0)................................................................................................... 62
5.2.3 ADC Options Register (SIM_ADCOPT)...................................................................................................... 63
5.2.4 FTM Option Register 1 (SIM_FTMOPT1)................................................................................................... 64
5.2.5 System Device Identification Register (SIM_SDID).....................................................................................65
5.2.6 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 66
5.2.7 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 68
5.2.8 Unique Identification Register High (SIM_UIDH)....................................................................................... 69
5.2.9 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................69
5.2.10 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 70
5.2.11 Unique Identification Register Low (SIM_UIDL)........................................................................................ 70
5.2.12 Miscellaneous Control register (SIM_MISCTRL)........................................................................................ 71
Chapter 6
Memory-Mapped Divide and Square Root (MMDVSQ)
6.1 Chip-specific Information for this Module...................................................................................................................73
6.2 Introduction...................................................................................................................................................................73
6.2.1 Features.......................................................................................................................................................... 73
6.2.2 Block diagram................................................................................................................................................74
6.2.3 Modes of operation........................................................................................................................................ 76
6.3 External signal description............................................................................................................................................77
6.4 Memory map and register definition.............................................................................................................................77
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6.4.1 Dividend Register (MMDVSQ_DEND)........................................................................................................78
6.4.2 Divisor Register (MMDVSQ_DSOR)...........................................................................................................78
6.4.3 Control/Status Register (MMDVSQ_CSR)...................................................................................................80
6.4.4 Result Register (MMDVSQ_RES)................................................................................................................ 83
6.4.5 Radicand Register (MMDVSQ_RCND)....................................................................................................... 83
6.5 Functional description...................................................................................................................................................84
6.5.1 Algorithms..................................................................................................................................................... 84
6.5.2 Execution times..............................................................................................................................................87
6.5.3 Software interface.......................................................................................................................................... 89
Chapter 7
Miscellaneous Control Module (MCM)
7.1 Chip-specific Information for this Module...................................................................................................................91
7.2 Introduction...................................................................................................................................................................92
7.2.1 Features.......................................................................................................................................................... 92
7.3 Memory map/register descriptions............................................................................................................................... 93
7.3.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................93
7.3.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 94
7.3.3 Platform Control Register (MCM_PLACR)..................................................................................................94
7.3.4 Compute Operation Control Register (MCM_CPO)..................................................................................... 97
Chapter 8
Crossbar Switch Lite (AXBS-Lite)
8.1 Chip-specific Information for this Module...................................................................................................................99
8.2 Introduction...................................................................................................................................................................100
8.2.1 Features.......................................................................................................................................................... 100
8.3 Memory Map / Register Definition...............................................................................................................................101
8.4 Functional Description..................................................................................................................................................101
8.4.1 General operation...........................................................................................................................................101
8.4.2 Arbitration......................................................................................................................................................102
8.5 Initialization/application information........................................................................................................................... 103
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Chapter 9
Peripheral Bridge (AIPS-Lite)
9.1 Chip-specific information for this module....................................................................................................................105
9.1.1 Instantiation Information................................................................................................................................105
9.2 Introduction...................................................................................................................................................................106
9.2.1 Features.......................................................................................................................................................... 106
9.2.2 General operation...........................................................................................................................................107
9.3 Memory map/register definition................................................................................................................................... 107
9.4 Functional description...................................................................................................................................................107
9.4.1 Access support............................................................................................................................................... 107
Chapter 10
Trigger MUX Control (TRGMUX)
10.1 Chip-specific information for this module....................................................................................................................109
10.1.1 Module Interconnectivity...............................................................................................................................109
10.2 Introduction...................................................................................................................................................................113
10.3 Features.........................................................................................................................................................................113
10.4 Memory map and register definition.............................................................................................................................113
10.4.1 TRGMUX0 register descriptions...................................................................................................................114
10.4.2 TRGMUX1 register descriptions...................................................................................................................134
10.5 Usage Guide..................................................................................................................................................................137
10.5.1 ADC Trigger Source...................................................................................................................................... 137
10.5.2 CMP Window/Sample Input .........................................................................................................................138
10.5.3 FTM Fault Detection Input / Hardware Triggers and Synchronization.........................................................138
Chapter 11
Memory and memory map
11.1 Introduction...................................................................................................................................................................139
11.2 Flash memory............................................................................................................................................................... 141
11.2.1 Flash memory types....................................................................................................................................... 141
11.2.2 Flash Memory Sizes.......................................................................................................................................141
11.3 SRAM memory.............................................................................................................................................................141
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11.3.1 SRAM sizes....................................................................................................................................................141
11.3.2 SRAM retention in low power modes............................................................................................................142
11.4 System memory map.....................................................................................................................................................142
11.4.1 Aliased bit-band regions................................................................................................................................ 143
11.5 Peripheral memory map................................................................................................................................................145
11.5.1 Peripheral Bridge (AIPS-Lite) Memory Map................................................................................................ 145
11.6 Private Peripheral Bus (PPB) memory map..................................................................................................................149
Chapter 12
Flash Acceleration Unit (FAU)
12.1 Flash Acceleration Unit (FAU).....................................................................................................................................151
12.1.1 Introduction....................................................................................................................................................151
12.1.2 Modes of operation........................................................................................................................................ 151
12.1.3 External signal description.............................................................................................................................151
12.1.4 Memory map and register descriptions..........................................................................................................151
12.1.5 Functional description....................................................................................................................................152
12.2 Usage Guide..................................................................................................................................................................152
Chapter 13
Flash Memory Module (FTFA)
13.1 Introduction...................................................................................................................................................................155
13.1.1 Features.......................................................................................................................................................... 155
13.1.2 Block Diagram............................................................................................................................................... 156
13.1.3 Glossary......................................................................................................................................................... 157
13.2 External Signal Description.......................................................................................................................................... 158
13.3 Memory Map and Registers..........................................................................................................................................158
13.3.1 Flash Configuration Field Description...........................................................................................................158
13.3.2 Program Flash IFR Map.................................................................................................................................159
13.3.3 Register Descriptions..................................................................................................................................... 159
13.4 Functional Description..................................................................................................................................................168
13.4.1 Flash Protection..............................................................................................................................................168
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13.4.2 Interrupts........................................................................................................................................................ 169
13.4.3 Flash Operation in Low-Power Modes.......................................................................................................... 169
13.4.4 Flash Reads and Ignored Writes.................................................................................................................... 170
13.4.5 Read While Write (RWW).............................................................................................................................170
13.4.6 Flash Program and Erase................................................................................................................................170
13.4.7 Flash Command Operations...........................................................................................................................171
13.4.8 Margin Read Commands............................................................................................................................... 174
13.4.9 Flash Command Description..........................................................................................................................175
13.4.10 Security.......................................................................................................................................................... 189
13.4.11 Reset Sequence.............................................................................................................................................. 191
Chapter 14
Clock Distribution
14.1 Introduction...................................................................................................................................................................193
14.2 High-Level clocking diagram....................................................................................................................................... 194
14.3 Clock definitions...........................................................................................................................................................194
14.4 Typical Clock Configuration........................................................................................................................................ 195
14.4.1 Default start-up clock.....................................................................................................................................195
14.4.2 VLPR mode clocking.....................................................................................................................................196
14.5 Clock Gating.................................................................................................................................................................196
14.6 Module clocks...............................................................................................................................................................197
14.6.1 LPO clock distribution...................................................................................................................................198
14.6.2 EWM clocks...................................................................................................................................................198
14.6.3 WDOG Clocking Information....................................................................................................................... 198
14.6.4 ADC Clocking Information........................................................................................................................... 199
14.6.5 PDB Clock Options........................................................................................................................................200
14.6.6 FTM Clocking Information............................................................................................................................200
14.6.7 LPTMR prescaler/glitch filter clocking options............................................................................................ 200
14.6.8 RTC Clocking Information............................................................................................................................ 201
14.6.9 MSCAN clocking...........................................................................................................................................202
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14.6.10 TSI Clocking Information..............................................................................................................................202
14.6.11 Module Clocking Information for LPUART, LPSPI, LPI2C and LPIT........................................................203
Chapter 15
System Clock Generator (SCG)
15.1 Chip-specific information for this module....................................................................................................................205
15.1.1 Instantiation Information................................................................................................................................205
15.2 Introduction...................................................................................................................................................................206
15.2.1 Features.......................................................................................................................................................... 207
15.3 Memory Map/Register Definition.................................................................................................................................208
15.3.1 Version ID Register (SCG_VERID)..............................................................................................................209
15.3.2 Parameter Register (SCG_PARAM)............................................................................................................. 209
15.3.3 Clock Status Register (SCG_CSR)................................................................................................................210
15.3.4 Run Clock Control Register (SCG_RCCR)...................................................................................................212
15.3.5 VLPR Clock Control Register (SCG_VCCR)...............................................................................................214
15.3.6 SCG CLKOUT Configuration Register (SCG_CLKOUTCNFG).................................................................216
15.3.7 System OSC Control Status Register (SCG_SOSCCSR)..............................................................................217
15.3.8 System OSC Divide Register (SCG_SOSCDIV).......................................................................................... 219
15.3.9 System Oscillator Configuration Register (SCG_SOSCCFG)...................................................................... 220
15.3.10 Slow IRC Control Status Register (SCG_SIRCCSR)....................................................................................222
15.3.11 Slow IRC Divide Register (SCG_SIRCDIV)................................................................................................ 223
15.3.12 Slow IRC Configuration Register (SCG_SIRCCFG)....................................................................................224
15.3.13 Fast IRC Control Status Register (SCG_FIRCCSR)..................................................................................... 225
15.3.14 Fast IRC Divide Register (SCG_FIRCDIV)..................................................................................................227
15.3.15 Fast IRC Configuration Register (SCG_FIRCCFG)..................................................................................... 228
15.3.16 Fast IRC Trim Configuration Register (SCG_FIRCTCFG)..........................................................................229
15.3.17 Fast IRC Status Register (SCG_FIRCSTAT)................................................................................................230
15.3.18 Low Power FLL Control Status Register (SCG_LPFLLCSR)......................................................................231
15.3.19 Low Power FLL Divide Register (SCG_LPFLLDIV).................................................................................. 233
15.3.20 Low Power FLL Configuration Register (SCG_LPFLLCFG)...................................................................... 234
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15.3.21 Low Power FLL Trim Configuration Register (SCG_LPFLLTCFG)...........................................................235
15.3.22 Low Power FLL Status Register (SCG_LPFLLSTAT).................................................................................236
15.4 Functional description...................................................................................................................................................237
15.4.1 SCG Clock Mode Transitions........................................................................................................................237
Chapter 16
Peripheral Clock Controller (PCC)
16.1 Chip-specific information for this module....................................................................................................................241
16.1.1 Information of PCC on this device................................................................................................................ 241
16.2 Introduction...................................................................................................................................................................241
16.3 Features.........................................................................................................................................................................242
16.4 Functional description...................................................................................................................................................243
16.5 Memory map and register definition.............................................................................................................................243
16.6 PCC register descriptions..............................................................................................................................................243
16.6.1 PCC Memory map......................................................................................................................................... 243
16.6.2 PCC FLASH Register (PCC_FLASH).......................................................................................................... 244
16.6.3 PCC MSCAN0 Register (PCC_MSCAN0)................................................................................................... 246
16.6.4 PCC LPSPI0 Register (PCC_LPSPI0)...........................................................................................................247
16.6.5 PCC CRC Register (PCC_CRC)....................................................................................................................249
16.6.6 PCC PDB0 Register (PCC_PDB0)................................................................................................................250
16.6.7 PCC LPIT0 Register (PCC_LPIT0)...............................................................................................................252
16.6.8 PCC FLEXTMR0 Register (PCC_FLEXTMR0).......................................................................................... 253
16.6.9 PCC FLEXTMR1 Register (PCC_FLEXTMR1).......................................................................................... 255
16.6.10 PCC ADC0 Register (PCC_ADC0)...............................................................................................................256
16.6.11 PCC RTC Register (PCC_RTC)....................................................................................................................258
16.6.12 PCC LPTMR0 Register (PCC_LPTMR0).....................................................................................................259
16.6.13 PCC TSI Register (PCC_TSI)........................................................................................................................261
16.6.14 PCC PORTA Register (PCC_PORTA)......................................................................................................... 262
16.6.15 PCC PORTB Register (PCC_PORTB)..........................................................................................................264
16.6.16 PCC PORTC Register (PCC_PORTC)..........................................................................................................265
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16.6.17 PCC PORTD Register (PCC_PORTD)......................................................................................................... 267
16.6.18 PCC PORTE Register (PCC_PORTE).......................................................................................................... 268
16.6.19 PCC PWT Register (PCC_PWT)...................................................................................................................270
16.6.20 PCC EWM Register (PCC_EWM)................................................................................................................271
16.6.21 PCC LPI2C0 Register (PCC_LPI2C0).......................................................................................................... 273
16.6.22 PCC LPUART0 Register (PCC_LPUART0)................................................................................................ 274
16.6.23 PCC LPUART1 Register (PCC_LPUART1)................................................................................................ 276
16.6.24 PCC LPUART2 Register (PCC_LPUART2)................................................................................................ 277
16.6.25 PCC CMP0 Register (PCC_CMP0)...............................................................................................................279
Chapter 17
Reset and Boot
17.1 Introduction...................................................................................................................................................................281
17.2 Reset..............................................................................................................................................................................282
17.2.1 Power-on reset (POR).................................................................................................................................... 282
17.2.2 System resets..................................................................................................................................................282
17.2.3 MCU Resets................................................................................................................................................... 285
17.2.4 Reset Pin ....................................................................................................................................................... 286
17.3 Boot...............................................................................................................................................................................286
17.3.1 Boot options................................................................................................................................................... 287
17.3.2 Boot sequence................................................................................................................................................ 288
Chapter 18
Reset Control Module (RCM)
18.1 Chip-specific information for this module....................................................................................................................291
18.1.1 Instantiation Information................................................................................................................................291
18.2 Introduction...................................................................................................................................................................291
18.3 Reset memory map and register descriptions............................................................................................................... 292
18.3.1 Version ID Register (RCM_VERID).............................................................................................................292
18.3.2 System Reset Status Register (RCM_SRS)................................................................................................... 293
18.3.3 Reset Pin Control register (RCM_RPC)........................................................................................................ 296
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18.3.4 Mode Register (RCM_MR)........................................................................................................................... 297
18.3.5 Force Mode Register (RCM_FM)..................................................................................................................298
18.3.6 Sticky System Reset Status Register (RCM_SSRS)......................................................................................299
18.3.7 System Reset Interrupt Enable Register (RCM_SRIE)................................................................................. 301
Chapter 19
Power Management
19.1 Introduction...................................................................................................................................................................305
19.2 Power Modes Description.............................................................................................................................................306
19.2.1 Run mode....................................................................................................................................................... 307
19.2.2 Wait mode......................................................................................................................................................308
19.2.3 Stop mode...................................................................................................................................................... 309
19.2.4 Power domains...............................................................................................................................................310
19.2.5 Entering and exiting power modes.................................................................................................................310
19.3 Power mode transitions.................................................................................................................................................310
19.4 Power modes shutdown sequencing............................................................................................................................. 311
19.5 Module Operation in Low Power Modes......................................................................................................................312
19.5.1 Peripheral doze...............................................................................................................................................314
19.6 Low-power wake-up sources........................................................................................................................................ 315
19.7 Power supply supervisor...............................................................................................................................................315
Chapter 20
System Mode Controller (SMC)
20.1 Introduction...................................................................................................................................................................317
20.2 Modes of operation....................................................................................................................................................... 317
20.3 Memory map and register descriptions.........................................................................................................................319
20.3.1 SMC Version ID Register (SMC_VERID)....................................................................................................319
20.3.2 SMC Parameter Register (SMC_PARAM)................................................................................................... 320
20.3.3 Power Mode Protection register (SMC_PMPROT).......................................................................................321
20.3.4 Power Mode Control register (SMC_PMCTRL)...........................................................................................323
20.3.5 Stop Control Register (SMC_STOPCTRL)...................................................................................................324
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20.3.6 Power Mode Status register (SMC_PMSTAT)............................................................................................. 326
20.4 Functional description...................................................................................................................................................326
20.4.1 Power mode transitions..................................................................................................................................326
20.4.2 Power mode entry/exit sequencing................................................................................................................ 328
20.4.3 Run modes......................................................................................................................................................330
20.4.4 Wait modes.................................................................................................................................................... 332
20.4.5 Stop modes.....................................................................................................................................................333
20.4.6 Debug in low power modes........................................................................................................................... 334
Chapter 21
Power Management Controller (PMC)
21.1 Chip-specific Information for this Module...................................................................................................................335
21.2 Introduction...................................................................................................................................................................335
21.3 Features.........................................................................................................................................................................335
21.4 Modes of Operation...................................................................................................................................................... 335
21.4.1 Full Performance Mode (FPM)......................................................................................................................336
21.4.2 Low Power Mode (LPM)...............................................................................................................................336
21.5 Low Voltage Detect (LVD) System............................................................................................................................. 336
21.5.1 Low Voltage Reset (LVR) Operation............................................................................................................ 337
21.5.2 LVD Interrupt Operation............................................................................................................................... 337
21.5.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 337
21.6 Memory Map and Register Definition..........................................................................................................................338
21.6.1 Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)..........................................................338
21.6.2 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)..........................................................339
21.6.3 Regulator Status and Control Register (PMC_REGSC)................................................................................340
21.6.4 Low Power Oscillator Trim Register (PMC_LPOTRIM)............................................................................. 341
Chapter 22
Security
22.1 Introduction...................................................................................................................................................................343
22.2 Flash Security............................................................................................................................................................... 343
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22.3 Security Interactions with other Modules.....................................................................................................................343
22.3.1 Security Interactions with Debug...................................................................................................................344
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................345
23.1.1 Features.......................................................................................................................................................... 345
23.1.2 Modes of Operation....................................................................................................................................... 346
23.1.3 Block Diagram............................................................................................................................................... 347
23.2 EWM Signal Descriptions............................................................................................................................................ 348
23.3 Memory Map/Register Definition.................................................................................................................................348
23.3.1 Control Register (EWM_CTRL)................................................................................................................... 348
23.3.2 Service Register (EWM_SERV)....................................................................................................................349
23.3.3 Compare Low Register (EWM_CMPL)........................................................................................................349
23.3.4 Compare High Register (EWM_CMPH).......................................................................................................350
23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)..................................................................................351
23.4 Functional Description..................................................................................................................................................351
23.4.1 The EWM_out Signal.................................................................................................................................... 351
23.4.2 The EWM_in Signal...................................................................................................................................... 352
23.4.3 EWM Counter................................................................................................................................................353
23.4.4 EWM Compare Registers.............................................................................................................................. 353
23.4.5 EWM Refresh Mechanism.............................................................................................................................353
23.4.6 EWM Interrupt...............................................................................................................................................354
23.4.7 Counter clock prescaler..................................................................................................................................354
23.5 Usage Guide..................................................................................................................................................................354
23.5.1 EWM low-power modes................................................................................................................................ 354
23.5.2 EWM_out pin state in low power modes.......................................................................................................355
23.5.3 Example code.................................................................................................................................................355
Chapter 24
Watchdog timer (WDOG)
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24.1 Chip-specific information for this module....................................................................................................................357
24.1.1 WDOG Clocking Information....................................................................................................................... 357
24.1.2 WDOG low-power modes............................................................................................................................. 357
24.2 Introduction...................................................................................................................................................................358
24.2.1 Features.......................................................................................................................................................... 358
24.2.2 Block diagram................................................................................................................................................359
24.3 Memory map and register definition.............................................................................................................................359
24.3.1 Watchdog Control and Status Register (WDOG_CS)................................................................................... 360
24.3.2 Watchdog Counter Register (WDOG_CNT).................................................................................................363
24.3.3 Watchdog Timeout Value Register (WDOG_TOVAL)................................................................................ 363
24.3.4 Watchdog Window Register (WDOG_WIN)................................................................................................364
24.4 Functional description...................................................................................................................................................365
24.4.1 Clock source...................................................................................................................................................365
24.4.2 Watchdog refresh mechanism........................................................................................................................366
24.4.3 Configuring the Watchdog.............................................................................................................................368
24.4.4 Using interrupts to delay resets......................................................................................................................369
24.4.5 Backup reset...................................................................................................................................................369
24.4.6 Functionality in debug and low-power modes...............................................................................................370
24.4.7 Fast testing of the watchdog...........................................................................................................................370
24.5 Application Information................................................................................................................................................371
24.5.1 Disable Watchdog..........................................................................................................................................372
24.5.2 Configure Watchdog......................................................................................................................................372
24.5.3 Refreshing the Watchdog...............................................................................................................................373
Chapter 25
Cyclic Redundancy Check (CRC)
25.1 Introduction...................................................................................................................................................................375
25.1.1 Features.......................................................................................................................................................... 375
25.1.2 Block diagram................................................................................................................................................375
25.1.3 Modes of operation........................................................................................................................................ 376
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25.2 Memory map and register descriptions.........................................................................................................................376
25.2.1 CRC Data register (CRC_DATA)................................................................................................................. 377
25.2.2 CRC Polynomial register (CRC_GPOLY).................................................................................................... 378
25.2.3 CRC Control register (CRC_CTRL)..............................................................................................................378
25.3 Functional description...................................................................................................................................................379
25.3.1 CRC initialization/reinitialization..................................................................................................................379
25.3.2 CRC calculations............................................................................................................................................380
25.3.3 Transpose feature........................................................................................................................................... 381
25.3.4 CRC result complement.................................................................................................................................383
25.4 Usage Guide..................................................................................................................................................................383
25.4.1 32-bit POSIX CRC.........................................................................................................................................384
25.4.2 16-bit KERMIT CRC.....................................................................................................................................385
Chapter 26
Debug
26.1 Introduction...................................................................................................................................................................387
26.2 Debug port pin descriptions..........................................................................................................................................387
26.3 SWD status and control registers..................................................................................................................................387
26.3.1 MDM-AP status register................................................................................................................................ 389
26.3.2 MDM-AP Control register.............................................................................................................................390
26.4 Debug resets..................................................................................................................................................................391
26.5 Micro Trace Buffer (MTB)...........................................................................................................................................391
26.6 Debug in low-power modes..........................................................................................................................................392
26.7 Debug and security....................................................................................................................................................... 392
Chapter 27
Micro Trace Buffer (MTB)
27.1 Introduction...................................................................................................................................................................393
27.1.1 Overview........................................................................................................................................................393
27.1.2 Features.......................................................................................................................................................... 396
27.1.3 Modes of operation........................................................................................................................................ 397
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27.2 External signal description............................................................................................................................................397
27.3 Memory map and register definition.............................................................................................................................398
27.3.1 MTB_RAM Memory Map.............................................................................................................................398
27.3.2 MTB_DWT Memory Map.............................................................................................................................410
27.3.3 System ROM Memory Map...........................................................................................................................420
27.4 Usage Guide..................................................................................................................................................................424
27.4.1 ARM reference...............................................................................................................................................424
Chapter 28
Signal Multiplexing and Pin Assignment
28.1 Package types................................................................................................................................................................427
28.2 Introduction...................................................................................................................................................................427
28.3 Pinouts.......................................................................................................................................................................... 427
28.3.1 KE1xZ64 Signal Multiplexing and Pin Assignments....................................................................................427
28.3.2 Pin properties................................................................................................................................................. 429
28.3.3 Pinout diagram............................................................................................................................................... 431
28.4 Module Signal Description Tables................................................................................................................................433
28.4.1 Core Modules.................................................................................................................................................433
28.4.2 System Modules.............................................................................................................................................434
28.4.3 Clock Modules............................................................................................................................................... 434
28.4.4 Analog............................................................................................................................................................434
28.4.5 Timer Modules...............................................................................................................................................435
28.4.6 Communication Interfaces............................................................................................................................. 436
28.4.7 Human-Machine Interfaces (HMI)................................................................................................................ 437
Chapter 29
Port Control and Interrupts (PORT)
29.1 Chip-specific information for this module....................................................................................................................439
29.1.1 I/O pin structure............................................................................................................................................. 439
29.1.2 Port control and interrupt module features.................................................................................................... 440
29.1.3 Application-related Information.................................................................................................................... 440
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NXP Semiconductors 17
Section number Title Page
29.2 Introduction...................................................................................................................................................................441
29.3 Overview.......................................................................................................................................................................441
29.3.1 Features.......................................................................................................................................................... 441
29.3.2 Modes of operation........................................................................................................................................ 442
29.4 External signal description............................................................................................................................................443
29.5 Detailed signal description............................................................................................................................................443
29.6 Memory map and register definition.............................................................................................................................443
29.6.1
Pin Control Register n (PORTx_PCRn).........................................................................................................450
29.6.2
Global Pin Control Low Register (PORTx_GPCLR)....................................................................................452
29.6.3
Global Pin Control High Register (PORTx_GPCHR)...................................................................................453
29.6.4
Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 454
29.6.5
Digital Filter Enable Register (PORTx_DFER).............................................................................................454
29.6.6
Digital Filter Clock Register (PORTx_DFCR)..............................................................................................455
29.6.7
Digital Filter Width Register (PORTx_DFWR)............................................................................................ 455
29.7 Functional description...................................................................................................................................................456
29.7.1 Pin control......................................................................................................................................................456
29.7.2 Global pin control.......................................................................................................................................... 457
29.7.3 External interrupts..........................................................................................................................................457
29.7.4 Digital filter....................................................................................................................................................458
Chapter 30
General-Purpose Input/Output (GPIO)
30.1 Chip-specific information for this module....................................................................................................................459
30.1.1 Instantiation Information................................................................................................................................459
30.1.2 GPIO accessibility in the memory map......................................................................................................... 459
30.2 Introduction...................................................................................................................................................................459
30.2.1 Features.......................................................................................................................................................... 460
30.2.2 Modes of operation........................................................................................................................................ 460
30.2.3 GPIO signal descriptions............................................................................................................................... 460
30.3 Memory map and register definition.............................................................................................................................461
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Section number Title Page
30.3.1
Port Data Output Register (GPIOx_PDOR)...................................................................................................463
30.3.2
Port Set Output Register (GPIOx_PSOR)......................................................................................................464
30.3.3
Port Clear Output Register (GPIOx_PCOR)..................................................................................................464
30.3.4
Port Toggle Output Register (GPIOx_PTOR)............................................................................................... 465
30.3.5
Port Data Input Register (GPIOx_PDIR).......................................................................................................465
30.3.6
Port Data Direction Register (GPIOx_PDDR)...............................................................................................466
30.4 FGPIO memory map and register definition................................................................................................................ 466
30.4.1
Port Data Output Register (FGPIOx_PDOR)................................................................................................ 468
30.4.2
Port Set Output Register (FGPIOx_PSOR)................................................................................................... 468
30.4.3
Port Clear Output Register (FGPIOx_PCOR)............................................................................................... 469
30.4.4
Port Toggle Output Register (FGPIOx_PTOR).............................................................................................469
30.4.5
Port Data Input Register (FGPIOx_PDIR).....................................................................................................470
30.4.6
Port Data Direction Register (FGPIOx_PDDR)............................................................................................ 470
30.5 Functional description...................................................................................................................................................471
30.5.1 General-purpose input....................................................................................................................................471
30.5.2 General-purpose output..................................................................................................................................471
30.5.3 IOPORT......................................................................................................................................................... 471
Chapter 31
Analog-to-Digital Converter (ADC)
31.1 Chip-specific information for this module....................................................................................................................473
31.1.1 Instantiation information................................................................................................................................473
31.1.2 ADC Clocking Information........................................................................................................................... 474
31.1.3 Application-related Information.................................................................................................................... 475
31.2 Introduction...................................................................................................................................................................479
31.2.1 Features.......................................................................................................................................................... 479
31.2.2 Block diagram................................................................................................................................................480
31.3 ADC signal descriptions............................................................................................................................................... 480
31.3.1 Analog Power (VDDA)................................................................................................................................. 481
31.3.2 Analog Ground (VSSA).................................................................................................................................481
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Section number Title Page
31.3.3 Voltage Reference Select...............................................................................................................................481
31.3.4 Analog Channel Inputs (ADx)....................................................................................................................... 482
31.4 ADC register descriptions.............................................................................................................................................482
31.4.1 ADC Memory map.........................................................................................................................................482
31.4.2 ADC Status and Control Register 1 (SC1A - SC1D).....................................................................................483
31.4.3 ADC Configuration Register 1 (CFG1).........................................................................................................486
31.4.4 ADC Configuration Register 2 (CFG2).........................................................................................................488
31.4.5 ADC Data Result Registers (RA - RD)......................................................................................................... 489
31.4.6 Compare Value Registers (CV1 - CV2)........................................................................................................ 490
31.4.7 Status and Control Register 2 (SC2)..............................................................................................................491
31.4.8 Status and Control Register 3 (SC3)..............................................................................................................493
31.4.9 BASE Offset Register (BASE_OFS).............................................................................................................495
31.4.10 ADC Offset Correction Register (OFS).........................................................................................................496
31.4.11 USER Offset Correction Register (USR_OFS)............................................................................................. 497
31.4.12 ADC X Offset Correction Register (XOFS)..................................................................................................498
31.4.13 ADC Y Offset Correction Register (YOFS)..................................................................................................499
31.4.14 ADC Gain Register (G)..................................................................................................................................500
31.4.15 ADC User Gain Register (UG)...................................................................................................................... 501
31.4.16 ADC General Calibration Value Register S (CLPS)..................................................................................... 502
31.4.17 ADC Plus-Side General Calibration Value Register 3 (CLP3)..................................................................... 503
31.4.18 ADC Plus-Side General Calibration Value Register 2 (CLP2)..................................................................... 504
31.4.19 ADC Plus-Side General Calibration Value Register 1 (CLP1)..................................................................... 505
31.4.20 ADC Plus-Side General Calibration Value Register 0 (CLP0)..................................................................... 506
31.4.21 ADC Plus-Side General Calibration Value Register X (CLPX)....................................................................507
31.4.22 ADC Plus-Side General Calibration Value Register 9 (CLP9)..................................................................... 508
31.4.23 ADC General Calibration Offset Value Register S (CLPS_OFS).................................................................509
31.4.24 ADC Plus-Side General Calibration Offset Value Register 3 (CLP3_OFS).................................................510
31.4.25 ADC Plus-Side General Calibration Offset Value Register 2 (CLP2_OFS).................................................511
31.4.26 ADC Plus-Side General Calibration Offset Value Register 1 (CLP1_OFS).................................................512
Kinetis KE1xZ64 Sub-Family Reference Manual, Rev. 2, 01/2019
20 NXP Semiconductors
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