NXP MWCT1x1x Reference guide

MWCT1013VLH Reference Manual

Supports MWCT1013VLH

Document Number: MWCT1013VLHRM

Rev. 1, 03/2019

MWCT1013VLH Reference Manual, Rev. 1, 03/2019

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Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................45

1.1.1 Purpose...........................................................................................................................................................45

1.1.2 Audience........................................................................................................................................................ 45

1.2 Conventions.................................................................................................................................................................. 45

1.2.1 Numbering systems........................................................................................................................................45

1.2.2 Typographic notation..................................................................................................................................... 46

1.2.3 Special terms..................................................................................................................................................46

Chapter 2

Introduction

2.1 Introduction...................................................................................................................................................................47

2.1.1 Core Overview............................................................................................................................................... 47

2.1.2 Memory Overview......................................................................................................................................... 48

2.1.3 Peripheral Overview...................................................................................................................................... 48

2.2 Application Examples...................................................................................................................................................48

2.3 Features.........................................................................................................................................................................48

2.3.1 MWCT1013VLH product features................................................................................................................ 49

2.3.2 Block Diagram............................................................................................................................................... 50

2.3.3 56800EX 32-bit core......................................................................................................................................51

2.3.4 Operation Parameters.....................................................................................................................................52

2.3.5 Packages.........................................................................................................................................................53

2.3.6 On-Chip Memory and Memory Protection....................................................................................................53

2.3.7 Peripherals......................................................................................................................................................53

2.3.7.1 System Modules.........................................................................................................................53

2.3.7.2 General Purpose I/O (GPIO)......................................................................................................55

2.3.7.3 Timers and PWM modules........................................................................................................ 55

2.3.7.4 Clock Modules........................................................................................................................... 57

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2.3.7.5 Analog Modules.........................................................................................................................58

2.3.7.6 Communication Interfaces......................................................................................................... 59

2.3.7.7 Power Management....................................................................................................................61

Chapter 3

Chip Configuration

3.1 Introduction...................................................................................................................................................................63

3.2 Core Configuration....................................................................................................................................................... 63

3.3 System modules............................................................................................................................................................ 64

3.3.1 System Integration Module (SIM) Configuration..........................................................................................64

3.3.2 MCM Configuration...................................................................................................................................... 64

3.3.3 Inter-Peripheral Crossbar Switch (XBAR) and AND/OR/INVERT (AOI) Configuration........................... 65

3.3.3.1 Number of inputs and outputs....................................................................................................66

3.3.3.2 XBARA and XBARB Inputs..................................................................................................... 66

3.3.3.3 XBAR Interconnections.............................................................................................................67

3.3.3.4 XBARA Outputs........................................................................................................................68

3.3.3.5 AOI module register write protection........................................................................................ 70

3.3.4 Interrupt Controller (INTC) Configuration....................................................................................................70

3.3.4.1 Reset/Interrupt Vector Table......................................................................................................71

3.3.5 DMA Controller Configuration..................................................................................................................... 79

3.3.5.1 DMA channel assignments........................................................................................................ 79

3.3.6 Power Management Controller (PMC) Configuration...................................................................................80

3.4 Clock Modules..............................................................................................................................................................81

3.4.1 On-Chip Clock Synthesis (OCCS) Configuration......................................................................................... 81

3.5 Memories and Memory Interfaces................................................................................................................................82

3.5.1 Flash Memory Controller (FMC) Configuration........................................................................................... 82

3.5.2 Flash Memory Configuration.........................................................................................................................83

3.5.2.1 Flash memory types and terminology........................................................................................84

3.5.2.2 FTFL_FOPT Register................................................................................................................ 84

3.6 Security and Integrity....................................................................................................................................................84

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3.6.1 Computer Operating Properly (COP) Module Configuration........................................................................84

3.6.1.1 COP low power clocks...............................................................................................................85

3.6.2 External Watchdog Monitor (EWM) Configuration......................................................................................85

3.6.2.1 EWM low power clocks.............................................................................................................86

3.6.2.2 EWM_OUT pin state in Low Power Modes..............................................................................86

3.6.2.3 EWM_IN signal......................................................................................................................... 87

3.6.3 Cyclic Redundancy Check (CRC) Configuration..........................................................................................87

3.7 Analog...........................................................................................................................................................................87

3.7.1 SAR Analog-to-Digital Converter (ADC) Configuration..............................................................................87

3.7.1.1 SAR ADC Instantiation............................................................................................................. 88

3.7.1.2 SAR ADC Channel Assignments.............................................................................................. 88

3.7.1.3 SAR ADC clock in stop modes..................................................................................................89

3.7.1.4 SAR ADC alternate clock..........................................................................................................89

3.7.1.5 SAR ADC Reference Options....................................................................................................89

3.7.1.6 SAR ADC Hardware Conversion Trigger Source..................................................................... 90

3.7.2 Cyclic Analog-to-Digital Converter (ADC) Configuration...........................................................................90

3.7.2.1 Cyclic ADC Instantiation...........................................................................................................90

3.7.2.2 Cyclic ADC SYNC Signal Connections....................................................................................91

3.7.2.3 Cyclic ADC and PWM Connections......................................................................................... 91

3.7.3 Comparator (CMP) Configuration.................................................................................................................91

3.7.3.1 Comparator Channel Assignments.............................................................................................92

3.7.3.2 Comparator Voltage References................................................................................................ 93

3.7.4 12-bit Digital-to-Analog Converter (DAC) Configuration............................................................................93

3.8 Timers and PWM..........................................................................................................................................................94

3.8.1 PWM Configuration.......................................................................................................................................94

3.8.1.1 PWM auxiliary signals and analog inputs..................................................................................95

3.8.2 PDB Configuration........................................................................................................................................ 95

3.8.2.1 PDB Trigger Connections..........................................................................................................96

3.8.3 PIT Configuration.......................................................................................................................................... 97

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3.8.3.1 PIT low power clocks................................................................................................................ 97

3.8.3.2 PIT master/slave selection......................................................................................................... 98

3.8.4 TMR Configuration........................................................................................................................................98

3.9 Communication interfaces............................................................................................................................................ 99

3.9.1 CAN Configuration........................................................................................................................................99

3.9.1.1 FlexCAN3 glitch filter............................................................................................................... 99

3.9.1.2 FlexCAN3 Supervisor Mode..................................................................................................... 100

3.9.2 Serial Peripheral Interface (SPI) Configuration.............................................................................................100

3.9.3 Inter-Integrated Circuit (I2C) Configuration................................................................................................. 101

3.9.3.1 I2C module address matching to wake the device from stop mode...........................................102

3.9.4 SCI Configuration..........................................................................................................................................102

3.10 Human-machine interfaces (HMI)................................................................................................................................103

3.10.1 GPIO Configuration.......................................................................................................................................103

3.10.1.1 GPIO Port D[4:0] configuration................................................................................................ 104

3.10.1.2 GPIO unbonded pads................................................................................................................. 105

Chapter 4

Memory Map

4.1 Introduction...................................................................................................................................................................107

4.2 Program/Data Memory Maps....................................................................................................................................... 107

4.3 Core and System Peripheral Memory Map...................................................................................................................108

4.4 Slave Peripheral Memory Map..................................................................................................................................... 109

Chapter 5

Clock Distribution

5.1 Overview.......................................................................................................................................................................113

5.2 Clock definitions...........................................................................................................................................................113

5.3 System clock source configuration............................................................................................................................... 114

5.4 Module clocks...............................................................................................................................................................115

Chapter 6

Reset and Boot

6.1 Reset Configuration...................................................................................................................................................... 117

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6.2 System Boot..................................................................................................................................................................118

6.2.1 FOPT boot options.........................................................................................................................................118

6.2.2 Boot Procedure for Normal Operation...........................................................................................................118

6.2.3 Boot sequence................................................................................................................................................ 119

Chapter 7

Power Management

7.1 Overview.......................................................................................................................................................................121

7.2 Architecture...................................................................................................................................................................121

7.3 External Supplies and Regulation.................................................................................................................................122

7.4 User Power Management Methods...............................................................................................................................122

7.5 Power Modes................................................................................................................................................................ 123

7.6 Power mode transitions.................................................................................................................................................125

Chapter 8

Signal Multiplexing and Signal Descriptions

8.1 Introduction...................................................................................................................................................................129

8.2 Signal Multiplexing Integration....................................................................................................................................129

8.3 Signal Multiplexing and Pin Assignments....................................................................................................................130

8.4 Pinout diagrams............................................................................................................................................................ 132

Chapter 9

Memory Resource Protection (MRP)

9.1 Overview.......................................................................................................................................................................135

9.2 Features.........................................................................................................................................................................136

9.3 Operation.......................................................................................................................................................................136

9.4 Programming Model Overview.................................................................................................................................... 140

9.5 Memory Resource Protection Restrictions................................................................................................................... 140

9.6 Base Address Setup.......................................................................................................................................................140

9.7 Programming Example................................................................................................................................................. 142

Chapter 10

Miscellaneous Control Module (MCM)

10.1 Introduction...................................................................................................................................................................145

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10.1.1 Features.......................................................................................................................................................... 145

10.2 Memory Map/Register Descriptions.............................................................................................................................146

10.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)....................................................................147

10.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)................................................................ 147

10.2.3 Core control register (MCM_CPCR).............................................................................................................148

10.2.4 Core fault address register (MCM_CFADR).................................................................................................149

10.2.5 Core fault attributes register (MCM_CFATR).............................................................................................. 150

10.2.6 Core fault location register (MCM_CFLOC)................................................................................................ 151

10.2.7 Core fault interrupt enable register (MCM_CFIER)......................................................................................152

10.2.8 MCM interrupt status register (MCM_CFISR)............................................................................................. 152

10.2.9 Core fault data register (MCM_CFDTR).......................................................................................................153

10.2.10 Resource Protection Control Register (MCM_RPCR).................................................................................. 153

10.2.11 User Flash Base Address Register (MCM_UFLASHBAR)..........................................................................155

10.2.12 User Program RAM Base Address Register (MCM_UPRAMBAR)............................................................ 155

10.2.13 Resource Protection Other Stack Pointer (MCM_SRPOSP).........................................................................156

10.2.14 Memory Protection Illegal PC (MCM_SRPIPC)...........................................................................................156

10.2.15 Resource Protection Misaligned PC (MCM_SRPMPC)............................................................................... 158

10.3 Functional Description..................................................................................................................................................159

10.3.1 Core Data Fault Recovery Registers..............................................................................................................159

Chapter 11

System Integration Module (SIM)

11.1 Introduction...................................................................................................................................................................161

11.1.1 Overview........................................................................................................................................................161

11.1.2 Features.......................................................................................................................................................... 161

11.1.3 Modes of Operation....................................................................................................................................... 162

11.1.4 Block Diagram............................................................................................................................................... 163

11.2 Memory Map and Register Descriptions...................................................................................................................... 165

11.2.1 Control Register (SIM_CTRL)...................................................................................................................... 166

11.2.2 Reset Status Register (SIM_RSTAT)............................................................................................................ 168

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11.2.3 Software Control Register (SIM_SCR0)....................................................................................................... 169

11.2.4 Software Control Register (SIM_SCR1)....................................................................................................... 170

11.2.5 Software Control Register (SIM_SCR2)....................................................................................................... 170

11.2.6 Software Control Register (SIM_SCR3)....................................................................................................... 170

11.2.7 Most Significant Half of JTAG ID (SIM_MSHID).......................................................................................171

11.2.8 Least Significant Half of JTAG ID (SIM_LSHID)....................................................................................... 172

11.2.9 Power Control Register (SIM_PWR)............................................................................................................ 173

11.2.10 Clock Output Select Register (SIM_CLKOUT)............................................................................................174

11.2.11 Peripheral Clock Rate Register (SIM_PCR)..................................................................................................176

11.2.12 Peripheral Clock Enable Register 0 (SIM_PCE0)......................................................................................... 177

11.2.13 Peripheral Clock Enable Register 1 (SIM_PCE1)......................................................................................... 179

11.2.14 Peripheral Clock Enable Register 2 (SIM_PCE2)......................................................................................... 181

11.2.15 Peripheral Clock Enable Register 3 (SIM_PCE3)......................................................................................... 182

11.2.16 STOP Disable Register 0 (SIM_SD0)........................................................................................................... 183

11.2.17 Peripheral Clock STOP Disable Register 1 (SIM_SD1)............................................................................... 186

11.2.18 Peripheral Clock STOP Disable Register 2 (SIM_SD2)............................................................................... 188

11.2.19 Peripheral Clock STOP Disable Register 3 (SIM_SD3)............................................................................... 190

11.2.20 I/O Short Address Location Register (SIM_IOSAHI)...................................................................................192

11.2.21 I/O Short Address Location Register (SIM_IOSALO)..................................................................................193

11.2.22 Protection Register (SIM_PROT)..................................................................................................................194

11.2.23 GPIOA LSBs Peripheral Select Register (SIM_GPSAL)..............................................................................196

11.2.24 GPIOC LSBs Peripheral Select Register (SIM_GPSCL)..............................................................................197

11.2.25 GPIOC MSBs Peripheral Select Register (SIM_GPSCH)............................................................................ 198

11.2.26 GPIOE LSBs Peripheral Select Register (SIM_GPSEL).............................................................................. 200

11.2.27 GPIOF LSBs Peripheral Select Register (SIM_GPSFL)...............................................................................201

11.2.28 GPIOF MSBs Peripheral Select Register (SIM_GPSFH)............................................................................. 202

11.2.29 Internal Peripheral Select Register 0 (SIM_IPS0)......................................................................................... 202

11.2.30 Miscellaneous Register 0 (SIM_MISC0).......................................................................................................205

11.2.31 Peripheral Software Reset Register 0 (SIM_PSWR0)...................................................................................206

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11.2.32 Peripheral Software Reset Register 1 (SIM_PSWR1)...................................................................................207

11.2.33 Peripheral Software Reset Register 2 (SIM_PSWR2)...................................................................................208

11.2.34 Peripheral Software Reset Register 3 (SIM_PSWR3)...................................................................................210

11.2.35 Power Mode Register (SIM_PWRMODE)....................................................................................................211

11.2.36 Non-Volatile Memory Option Register 2 (High) (SIM_NVMOPT2H)........................................................ 212

11.2.37 Non-Volatile Memory Option Register 2 (Low) (SIM_NVMOPT2L)......................................................... 213

11.2.38 Non-Volatile Memory Option Register 3 (High) (SIM_NVMOPT3H)........................................................ 213

11.3 Functional Description..................................................................................................................................................214

11.3.1 Clock Generation Overview...........................................................................................................................214

11.3.2 Power-Down Modes Overview......................................................................................................................215

11.3.3 STOP and WAIT Mode Disable Function.....................................................................................................216

11.4 Resets............................................................................................................................................................................217

11.5 Clocks........................................................................................................................................................................... 217

11.6 Interrupts.......................................................................................................................................................................217

Chapter 12

Interrupt Controller (INTC)

12.1 Introduction...................................................................................................................................................................219

12.1.1 References......................................................................................................................................................219

12.1.2 Features.......................................................................................................................................................... 219

12.1.3 Modes of Operation....................................................................................................................................... 219

12.1.4 Block Diagram............................................................................................................................................... 220

12.2 Memory Map and Registers..........................................................................................................................................221

12.2.1 Interrupt Priority Register 0 (INTC_IPR0)....................................................................................................222

12.2.2 Interrupt Priority Register 1 (INTC_IPR1)....................................................................................................223

12.2.3 Interrupt Priority Register 2 (INTC_IPR2)....................................................................................................225

12.2.4 Interrupt Priority Register 3 (INTC_IPR3)....................................................................................................226

12.2.5 Interrupt Priority Register 4 (INTC_IPR4)....................................................................................................228

12.2.6 Interrupt Priority Register 5 (INTC_IPR5)....................................................................................................229

12.2.7 Interrupt Priority Register 6 (INTC_IPR6)....................................................................................................231

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12.2.8 Interrupt Priority Register 8 (INTC_IPR8)....................................................................................................232

12.2.9 Interrupt Priority Register 9 (INTC_IPR9)....................................................................................................233

12.2.10 Interrupt Priority Register 10 (INTC_IPR10)................................................................................................234

12.2.11 Interrupt Priority Register 11 (INTC_IPR11)................................................................................................236

12.2.12 Interrupt Priority Register 12 (INTC_IPR12)................................................................................................237

12.2.13 Vector Base Address Register (INTC_VBA)................................................................................................ 238

12.2.14 Fast Interrupt 0 Match Register (INTC_FIM0)............................................................................................. 239

12.2.15 Fast Interrupt 0 Vector Address Low Register (INTC_FIVAL0)..................................................................239

12.2.16 Fast Interrupt 0 Vector Address High Register (INTC_FIVAH0)................................................................ 240

12.2.17 Fast Interrupt 1 Match Register (INTC_FIM1)............................................................................................. 240

12.2.18 Fast Interrupt 1 Vector Address Low Register (INTC_FIVAL1)..................................................................241

12.2.19 Fast Interrupt 1 Vector Address High Register (INTC_FIVAH1)................................................................ 241

12.2.20 IRQ Pending Register 0 (INTC_IRQP0)....................................................................................................... 241

12.2.21 IRQ Pending Register 1 (INTC_IRQP1)....................................................................................................... 242

12.2.22 IRQ Pending Register 2 (INTC_IRQP2)....................................................................................................... 242

12.2.23 IRQ Pending Register 3 (INTC_IRQP3)....................................................................................................... 243

12.2.24 IRQ Pending Register 4 (INTC_IRQP4)....................................................................................................... 243

12.2.25 IRQ Pending Register 5 (INTC_IRQP5)....................................................................................................... 244

12.2.26 IRQ Pending Register 6 (INTC_IRQP6)....................................................................................................... 244

12.2.27 Control Register (INTC_CTRL)....................................................................................................................245

12.3 Functional Description..................................................................................................................................................246

12.3.1 Normal Interrupt Handling.............................................................................................................................246

12.3.2 Interrupt Nesting............................................................................................................................................ 246

12.3.3 Fast Interrupt Handling.................................................................................................................................. 247

12.4 Interrupts.......................................................................................................................................................................247

Chapter 13

DMA Controller

13.1 Introduction...................................................................................................................................................................249

13.1.1 Overview........................................................................................................................................................249

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13.1.2 Features.......................................................................................................................................................... 251

13.2 DMA Transfer Overview..............................................................................................................................................251

13.3 Memory Map/Register Definition.................................................................................................................................253

13.3.1 DMA Request Control Register (DMA_REQC)........................................................................................... 254

13.3.2

Source Address Register (DMA_SARn)....................................................................................................... 258

13.3.3

Destination Address Register (DMA_DARn)............................................................................................... 258

13.3.4

DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............................................................258

13.3.5

DMA Control Register (DMA_DCRn)..........................................................................................................261

13.4 Functional Description..................................................................................................................................................264

13.4.1 Transfer requests (Cycle-Steal and Continuous modes)................................................................................265

13.4.2 Channel initialization and startup.................................................................................................................. 265

13.4.2.1 Channel prioritization................................................................................................................ 265

13.4.2.2 Programming the DMA Controller Module...............................................................................266

13.4.3 Dual-Address Data Transfer Mode................................................................................................................267

13.4.4 Advanced Data Transfer Controls: Auto-Alignment.....................................................................................268

13.4.5 Termination....................................................................................................................................................269

Chapter 14

Power Management Controller (PMC)

14.1 Introduction...................................................................................................................................................................271

14.1.1 Overview........................................................................................................................................................271

14.1.2 Features.......................................................................................................................................................... 271

14.1.3 Modes of Operation....................................................................................................................................... 272

14.1.4 Block Diagram............................................................................................................................................... 273

14.2 Memory Map and Register Descriptions...................................................................................................................... 274

14.2.1 Control Register (PMC_CTRL).....................................................................................................................275

14.2.2 Status Register (PMC_STS)...........................................................................................................................276

14.3 Functional Description..................................................................................................................................................278

14.4 Resets............................................................................................................................................................................279

14.5 Clocks........................................................................................................................................................................... 279

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14.6 Interrupts.......................................................................................................................................................................280

Chapter 15

Crossbar AND/OR/INVERT (AOI) Module

15.1 Introduction...................................................................................................................................................................281

15.1.1 Overview........................................................................................................................................................281

15.1.2 Features.......................................................................................................................................................... 283

15.1.3 Modes of Operation....................................................................................................................................... 283

15.2 External Signal Description.......................................................................................................................................... 283

15.3 Memory Map and Register Descriptions...................................................................................................................... 283

15.3.1

Boolean Function Term 0 and 1 Configuration Register for EVENTn (AOI_BFCRT01n)..........................285

15.3.2

Boolean Function Term 2 and 3 Configuration Register for EVENTn (AOI_BFCRT23n)..........................286

15.4 Functional Description..................................................................................................................................................288

15.4.1 Configuration Examples for the Boolean Function Evaluation.....................................................................289

15.4.2 AOI Timing Between Inputs and Outputs..................................................................................................... 290

Chapter 16

Inter-Peripheral Crossbar Switch A (XBARA)

16.1 Introduction...................................................................................................................................................................293

16.1.1 Overview........................................................................................................................................................293

16.1.2 Features.......................................................................................................................................................... 293

16.1.3 Modes of Operation....................................................................................................................................... 294

16.1.4 Block Diagram............................................................................................................................................... 294

16.2 Signal Descriptions.......................................................................................................................................................295

16.2.1 XBAR_OUT[0:NUM_OUT-1] - MUX Outputs........................................................................................... 295

16.2.2 XBAR_IN[0:NUM_IN-1] - MUX Inputs......................................................................................................295

16.2.3 DMA_REQ[n] - DMA Request Output(s).....................................................................................................295

16.2.4 DMA_ACK[n] - DMA Acknowledge Input(s)..............................................................................................295

16.2.5 INT_REQ[n] - Interrupt Request Output(s)...................................................................................................296

16.3 Memory Map and Register Descriptions...................................................................................................................... 296

16.3.1 Crossbar A Select Register 0 (XBARA_SEL0).............................................................................................297

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16.3.2 Crossbar A Select Register 1 (XBARA_SEL1).............................................................................................298

16.3.3 Crossbar A Select Register 2 (XBARA_SEL2).............................................................................................298

16.3.4 Crossbar A Select Register 3 (XBARA_SEL3).............................................................................................299

16.3.5 Crossbar A Select Register 4 (XBARA_SEL4).............................................................................................299

16.3.6 Crossbar A Select Register 5 (XBARA_SEL5).............................................................................................300

16.3.7 Crossbar A Select Register 6 (XBARA_SEL6).............................................................................................300

16.3.8 Crossbar A Select Register 7 (XBARA_SEL7).............................................................................................301

16.3.9 Crossbar A Select Register 8 (XBARA_SEL8).............................................................................................301

16.3.10 Crossbar A Select Register 9 (XBARA_SEL9).............................................................................................302

16.3.11 Crossbar A Select Register 10 (XBARA_SEL10).........................................................................................302

16.3.12 Crossbar A Select Register 11 (XBARA_SEL11).........................................................................................303

16.3.13 Crossbar A Select Register 12 (XBARA_SEL12).........................................................................................303

16.3.14 Crossbar A Select Register 13 (XBARA_SEL13).........................................................................................304

16.3.15 Crossbar A Select Register 14 (XBARA_SEL14).........................................................................................304

16.3.16 Crossbar A Select Register 15 (XBARA_SEL15).........................................................................................305

16.3.17 Crossbar A Select Register 16 (XBARA_SEL16).........................................................................................305

16.3.18 Crossbar A Select Register 17 (XBARA_SEL17).........................................................................................306

16.3.19 Crossbar A Select Register 18 (XBARA_SEL18).........................................................................................306

16.3.20 Crossbar A Select Register 19 (XBARA_SEL19).........................................................................................307

16.3.21 Crossbar A Select Register 20 (XBARA_SEL20).........................................................................................307

16.3.22 Crossbar A Select Register 21 (XBARA_SEL21).........................................................................................308

16.3.23 Crossbar A Select Register 22 (XBARA_SEL22).........................................................................................308

16.3.24 Crossbar A Select Register 23 (XBARA_SEL23).........................................................................................309

16.3.25 Crossbar A Select Register 24 (XBARA_SEL24).........................................................................................309

16.3.26 Crossbar A Select Register 25 (XBARA_SEL25).........................................................................................310

16.3.27 Crossbar A Select Register 26 (XBARA_SEL26).........................................................................................310

16.3.28 Crossbar A Select Register 27 (XBARA_SEL27).........................................................................................311

16.3.29 Crossbar A Select Register 28 (XBARA_SEL28).........................................................................................311

16.3.30 Crossbar A Select Register 29 (XBARA_SEL29).........................................................................................312

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16.3.31 Crossbar A Control Register 0 (XBARA_CTRL0)....................................................................................... 312

16.3.32 Crossbar A Control Register 1 (XBARA_CTRL1)....................................................................................... 314

16.4 Functional Description..................................................................................................................................................316

16.4.1 General...........................................................................................................................................................316

16.4.2 Functional Mode............................................................................................................................................ 317

16.5 Resets............................................................................................................................................................................317

16.6 Clocks........................................................................................................................................................................... 317

16.7 Interrupts and DMA Requests...................................................................................................................................... 317

Chapter 17

Inter-Peripheral Crossbar Switch B (XBARB): AOI Input

17.1 Introduction...................................................................................................................................................................319

17.2 Memory Map and Register Descriptions...................................................................................................................... 319

17.2.1 Crossbar B Select Register 0 (XBARB_SEL0)............................................................................................. 320

17.2.2 Crossbar B Select Register 1 (XBARB_SEL1)............................................................................................. 320

17.2.3 Crossbar B Select Register 2 (XBARB_SEL2)............................................................................................. 321

17.2.4 Crossbar B Select Register 3 (XBARB_SEL3)............................................................................................. 321

17.2.5 Crossbar B Select Register 4 (XBARB_SEL4)............................................................................................. 322

17.2.6 Crossbar B Select Register 5 (XBARB_SEL5)............................................................................................. 322

17.2.7 Crossbar B Select Register 6 (XBARB_SEL6)............................................................................................. 323

17.2.8 Crossbar B Select Register 7 (XBARB_SEL7)............................................................................................. 323

Chapter 18

On-Chip Clock Synthesis (OCCS)

18.1 Introduction...................................................................................................................................................................325

18.1.1 Overview........................................................................................................................................................325

18.1.2 Features.......................................................................................................................................................... 325

18.2 Modes of Operation...................................................................................................................................................... 326

18.2.1 Internal Clock Sources...................................................................................................................................327

18.2.2 Loop Controlled Pierce Crystal Oscillator.....................................................................................................327

18.2.3 External Clock Source - Crystal Oscillator Bypass Option........................................................................... 328

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18.2.4 External Clock Source - CLKIN....................................................................................................................328

18.3 Block Diagram..............................................................................................................................................................330

18.4 Pin Description..............................................................................................................................................................331

18.4.1 External Clock Reference.............................................................................................................................. 331

18.4.2 Oscillator IO (XTAL, EXTAL)..................................................................................................................... 331

18.4.3 CLKO.............................................................................................................................................................331

18.5 Memory Map and Register Descriptions...................................................................................................................... 332

18.5.1 PLL Control Register (OCCS_CTRL)...........................................................................................................332

18.5.2 PLL Divide-By Register (OCCS_DIVBY)....................................................................................................334

18.5.3 OCCS Status Register (OCCS_STAT)..........................................................................................................335

18.5.4 Oscillator Control Register 1 (OCCS_OSCTL1)...........................................................................................337

18.5.5 Oscillator Control Register 2 (OCCS_OSCTL2)...........................................................................................338

18.5.6 External Clock Check Reference (OCCS_CLKCHKR)................................................................................340

18.5.7 External Clock Check Target (OCCS_CLKCHKT)......................................................................................341

18.5.8 Protection Register (OCCS_PROT)...............................................................................................................341

18.6 Functional Description..................................................................................................................................................342

18.7 Relaxation Oscillators...................................................................................................................................................346

18.7.1 Trimming Frequency on the Internal 8 MHz Relaxation Oscillator..............................................................346

18.7.2 Trimming Frequency on the Internal 32 kHz Relaxation Oscillator............................................................. 346

18.8 External Reference........................................................................................................................................................347

18.9 Crystal Oscillator.......................................................................................................................................................... 347

18.9.1 Switching Clock Sources............................................................................................................................... 347

18.10 Phase Locked Loop.......................................................................................................................................................349

18.10.1 PLL Recommended Range of Operation.......................................................................................................349

18.10.2 PLL Lock Time Specification........................................................................................................................349

18.10.2.1 Lock Time Definition.................................................................................................................349

18.10.2.2 Parametric Influences on Reaction Time...................................................................................349

18.11 PLL Frequency Lock Detector Block...........................................................................................................................350

18.12 Loss of Reference Clock Detector................................................................................................................................ 350

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18.13 Resets............................................................................................................................................................................351

18.13.1 Resets............................................................................................................................................................. 351

18.14 Clocks........................................................................................................................................................................... 351

18.15 Interrupts.......................................................................................................................................................................352

Chapter 19

Flash Memory Controller (FMC)

19.1 Introduction...................................................................................................................................................................353

19.1.1 Overview........................................................................................................................................................353

19.1.2 Features.......................................................................................................................................................... 354

19.2 Modes of operation....................................................................................................................................................... 354

19.3 External signal description............................................................................................................................................354

19.4 Memory map and register descriptions.........................................................................................................................355

19.4.1 Flash Access Protection Register (FMC_PFAPR).........................................................................................359

19.4.2 Flash Bank 0 Control Register (FMC_PFB0CR).......................................................................................... 361

19.4.3 Flash Bank 1 Control Register (FMC_PFB1CR).......................................................................................... 363

19.4.4

Cache Tag Storage (FMC_TAGVDW0Sn)................................................................................................... 364

19.4.5

Cache Tag Storage (FMC_TAGVDW1Sn)................................................................................................... 365

19.4.6

Cache Tag Storage (FMC_TAGVDW2Sn)................................................................................................... 366

19.4.7

Cache Tag Storage (FMC_TAGVDW3Sn)................................................................................................... 367

19.4.8

Cache Data Storage (upper word) (FMC_DATAW0SnU)............................................................................367

19.4.9

Cache Data Storage (lower word) (FMC_DATAW0SnL)............................................................................ 368

19.4.10

Cache Data Storage (upper word) (FMC_DATAW1SnU)............................................................................368

19.4.11

Cache Data Storage (lower word) (FMC_DATAW1SnL)............................................................................ 369

19.4.12

Cache Data Storage (upper word) (FMC_DATAW2SnU)............................................................................369

19.4.13

Cache Data Storage (lower word) (FMC_DATAW2SnL)............................................................................ 370

19.4.14

Cache Data Storage (upper word) (FMC_DATAW3SnU)............................................................................370

19.4.15

Cache Data Storage (lower word) (FMC_DATAW3SnL)............................................................................ 371

19.5 Functional description...................................................................................................................................................371

19.5.1 Default configuration..................................................................................................................................... 371

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19.5.2 Configuration options.................................................................................................................................... 372

19.5.3 Wait states......................................................................................................................................................372

19.5.4 Speculative reads............................................................................................................................................373

19.6 Initialization and application information.....................................................................................................................374

Chapter 20

Flash Memory Module (FTFL)

20.1 Introduction...................................................................................................................................................................375

20.1.1 Features.......................................................................................................................................................... 376

20.1.1.1 Program Flash Memory Features...............................................................................................376

20.1.1.2 FlexNVM Memory Features......................................................................................................376

20.1.1.3 FlexRAM Features.....................................................................................................................376

20.1.1.4 Other Flash Memory Module Features...................................................................................... 377

20.1.2 Block Diagram............................................................................................................................................... 377

20.1.3 Glossary......................................................................................................................................................... 378

20.2 External Signal Description.......................................................................................................................................... 380

20.3 Memory Map and Registers..........................................................................................................................................380

20.3.1 Flash Configuration Field Description...........................................................................................................381

20.3.2 Program Flash IFR Map.................................................................................................................................381

20.3.2.1 Program Once Field................................................................................................................... 382

20.3.3 Data Flash IFR Map.......................................................................................................................................382

20.3.3.1 EEPROM Data Set Size.............................................................................................................382

20.3.3.2 FlexNVM Partition Code...........................................................................................................383

20.3.4 Register Descriptions..................................................................................................................................... 384

20.3.4.1 Flash Status Register (FTFL_FSTAT).......................................................................................386

20.3.4.2 Flash Configuration Register (FTFL_FCNFG)......................................................................... 387

20.3.4.3 Flash Security Register (FTFL_FSEC)......................................................................................389

20.3.4.4 Flash Option Register (FTFL_FOPT)........................................................................................390

20.3.4.5

Flash Common Command Object Registers (FTFL_FCCOBn)................................................391

20.3.4.6

Program Flash Protection Registers (FTFL_FPROTn)............................................................. 392

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20.3.4.7 EEPROM Protection Register (FTFL_FEPROT)......................................................................394

20.3.4.8 Data Flash Protection Register (FTFL_FDPROT).................................................................... 395

20.4 Functional Description..................................................................................................................................................396

20.4.1 Flash Protection..............................................................................................................................................396

20.4.2 FlexNVM Description....................................................................................................................................398

20.4.2.1 FlexNVM Block Partitioning for FlexRAM..............................................................................398

20.4.2.2 EEPROM User Perspective....................................................................................................... 399

20.4.2.3 EEPROM Implementation Overview........................................................................................ 400

20.4.2.4 Write endurance to FlexRAM for EEPROM.............................................................................401

20.4.3 Interrupts........................................................................................................................................................ 402

20.4.4 Flash Operation in Low-Power Modes.......................................................................................................... 403

20.4.4.1 Wait Mode..................................................................................................................................403

20.4.4.2 Stop Mode..................................................................................................................................403

20.4.5 Functional Modes of Operation..................................................................................................................... 403

20.4.6 Flash Reads and Ignored Writes.................................................................................................................... 403

20.4.7 Read While Write (RWW).............................................................................................................................404

20.4.8 Flash Program and Erase................................................................................................................................404

20.4.9 Flash Command Operations...........................................................................................................................404

20.4.9.1 Command Write Sequence.........................................................................................................405

20.4.9.2 Flash Commands........................................................................................................................407

20.4.9.3 Flash Commands by Mode........................................................................................................ 410

20.4.9.4 Allowed Simultaneous Flash Operations...................................................................................410

20.4.10 Margin Read Commands............................................................................................................................... 411

20.4.11 Flash Command Description..........................................................................................................................412

20.4.11.1 Read 1s Block Command...........................................................................................................413

20.4.11.2 Read 1s Section Command........................................................................................................ 414

20.4.11.3 Program Check Command.........................................................................................................415

20.4.11.4 Read Resource Command..........................................................................................................416

20.4.11.5 Program Longword Command...................................................................................................417

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20.4.11.6 Erase Flash Block Command.....................................................................................................419

20.4.11.7 Erase Flash Sector Command.................................................................................................... 420

20.4.11.8 Program Section Command....................................................................................................... 423

20.4.11.9 Read 1s All Blocks Command...................................................................................................425

20.4.11.10 Read Once Command................................................................................................................ 426

20.4.11.11 Program Once Command...........................................................................................................427

20.4.11.12 Erase All Blocks Command.......................................................................................................428

20.4.11.13 Verify Backdoor Access Key Command...................................................................................429

20.4.11.14 Program Partition Command..................................................................................................... 430

20.4.11.15 Set FlexRAM Function Command............................................................................................ 432

20.4.12 Security.......................................................................................................................................................... 434

20.4.12.1 Flash Memory Access by Mode and Security........................................................................... 434

20.4.12.2 Changing the Security State.......................................................................................................435

20.4.13 Reset Sequence.............................................................................................................................................. 436

Chapter 21

Computer Operating Properly (COP) Watchdog

21.1 Introduction...................................................................................................................................................................437

21.1.1 Features.......................................................................................................................................................... 437

21.1.2 Block Diagram............................................................................................................................................... 437

21.2 Memory Map and Registers..........................................................................................................................................438

21.2.1 COP Control Register (COP_CTRL).............................................................................................................439

21.2.2 COP Timeout Register (COP_TOUT)...........................................................................................................441

21.2.3 COP Counter Register (COP_CNTR)............................................................................................................441

21.2.4 COP Interrupt Value Register (COP_INTVAL)............................................................................................442

21.3 Functional Description..................................................................................................................................................442

21.3.1 COP after Reset..............................................................................................................................................443

21.3.2 Wait Mode Operation.....................................................................................................................................443

21.3.3 Stop Mode Operation.....................................................................................................................................443

21.3.4 Debug Mode Operation..................................................................................................................................443

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