KL82 Sub-Family Reference Manual
Supports: MKL82Z128VMC7(R), MKL82Z128VLK7(R),
MKL82Z128VLL7(R), MKL82Z128VLH7(R), MKL82Z128VMP7(R)
Document Number: KL82P121M72SF0RM
Rev. 3, 08/2016
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
About This Manual
1.1 Audience....................................................................................................................................................................... 53
1.2 Organization..................................................................................................................................................................53
1.3 Module descriptions......................................................................................................................................................53
1.3.1 Example: chip-specific information that supersedes content in the same chapter.......................................54
1.3.2 Example: chip-specific information that refers to a different chapter......................................................... 55
1.4 Register descriptions.....................................................................................................................................................56
1.5 Conventions.................................................................................................................................................................. 57
1.5.1 Numbering systems......................................................................................................................................57
1.5.2 Typographic notation................................................................................................................................... 57
1.5.3 Special terms................................................................................................................................................58
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................59
2.2 Block diagram...............................................................................................................................................................59
2.3 Module functional categories........................................................................................................................................60
2.3.1 ARM® Cortex®-M0+ Core Modules..........................................................................................................62
2.3.2 System modules........................................................................................................................................... 62
2.3.3 Memories and memory interfaces................................................................................................................63
2.3.4 Clocks...........................................................................................................................................................64
2.3.5 Analog modules........................................................................................................................................... 64
2.3.6 Timer modules............................................................................................................................................. 65
2.3.7 Security and Integrity modules.................................................................................................................... 65
2.3.8 Communication interfaces........................................................................................................................... 66
2.3.9 Human-machine interfaces.......................................................................................................................... 66
2.4 Ordering information.................................................................................................................................................... 67
Chapter 3
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
NXP Semiconductors 3
Section number Title Page
Core Overview
3.1 ARM Cortex-M0+ Core................................................................................................................................................69
3.1.1 Buses, interconnects, and interfaces............................................................................................................ 69
3.1.2 System tick timer......................................................................................................................................... 69
3.1.3 Debug facilities............................................................................................................................................ 69
3.1.4 Core privilege levels.................................................................................................................................... 70
3.2 Nested vectored interrupt controller (NVIC) configuration......................................................................................... 70
3.2.1 Interrupt priority levels................................................................................................................................ 70
3.2.2 Non-maskable interrupt................................................................................................................................70
3.2.3 Interrupt connections....................................................................................................................................70
3.2.4 Interrupt channel assignments......................................................................................................................72
3.2.5 INTMUX0 input mux assignment............................................................................................................... 73
3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................................ 74
3.3.1 AWIC overview........................................................................................................................................... 74
3.3.2 Wake-up sources..........................................................................................................................................75
Chapter 4
Memories and Memory Interfaces
4.1 Flash memory............................................................................................................................................................... 77
4.1.1 Flash memory types..................................................................................................................................... 77
4.1.2 Flash memory sizes......................................................................................................................................77
4.1.3 Flash security............................................................................................................................................... 77
4.1.4 Flash modes..................................................................................................................................................77
4.1.5 Erase all flash contents.................................................................................................................................78
4.1.6 FTFA_FOPT register................................................................................................................................... 78
4.1.7 Flash access control introduction.................................................................................................................78
4.2 SRAM........................................................................................................................................................................... 79
4.2.1 SRAM sizes..................................................................................................................................................79
4.2.2 SRAM retention in low power modes..........................................................................................................79
4.3 QuadSPI memory interface...........................................................................................................................................80
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
4 NXP Semiconductors
Section number Title Page
4.4 System register file....................................................................................................................................................... 80
4.5 VBAT register file........................................................................................................................................................ 80
4.6 Memory map.................................................................................................................................................................80
4.6.1 Introduction..................................................................................................................................................80
4.6.2 System memory map....................................................................................................................................81
4.6.3 Flash memory map.......................................................................................................................................83
4.6.4 SRAM memory map.................................................................................................................................... 84
4.6.5 Peripheral bridge (AIPS-Lite) memory map................................................................................................84
4.6.6 Private peripherals........................................................................................................................................89
4.6.7 Private peripheral bus (PPB) memory map..................................................................................................89
Chapter 5
Clock Distribution using MCG
5.1 Introduction...................................................................................................................................................................91
5.2 Programming model......................................................................................................................................................91
5.3 High-Level device clocking diagram............................................................................................................................91
5.4 Clock definitions...........................................................................................................................................................92
5.4.1 Device clock summary.................................................................................................................................93
5.5 Internal clocking requirements..................................................................................................................................... 96
5.5.1 Clock divider values after reset....................................................................................................................96
5.5.2 VLPR mode clocking...................................................................................................................................97
5.6 Clock gating..................................................................................................................................................................97
5.7 Module clocks...............................................................................................................................................................98
5.7.1 PMC 1-kHz LPO clock................................................................................................................................99
5.7.2 IRC 48MHz clock........................................................................................................................................ 99
5.7.3 WDOG clocking.......................................................................................................................................... 100
5.7.4 PORT digital filter clocking.........................................................................................................................101
5.7.5 LPTMR clocking..........................................................................................................................................101
5.7.6 TPM clocking...............................................................................................................................................102
5.7.7 USB FS OTG Controller clocking...............................................................................................................102
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
NXP Semiconductors 5
Section number Title Page
5.7.8 LPUART clocking....................................................................................................................................... 103
5.7.9 QSPI clocking.............................................................................................................................................. 103
5.7.10 LP Trusted Cryptography (LTC) clocking...................................................................................................104
5.7.11 TRNG clocking............................................................................................................................................104
5.7.12 FlexIO clocking............................................................................................................................................104
5.7.13 EMVSIM clocking.......................................................................................................................................105
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................107
6.2 Reset..............................................................................................................................................................................107
6.2.1 Power-on reset (POR).................................................................................................................................. 108
6.2.2 System reset sources.................................................................................................................................... 108
6.2.3 MCU Resets................................................................................................................................................. 111
6.2.4 Reset Pin ..................................................................................................................................................... 113
6.2.5 Debug resets.................................................................................................................................................113
6.3 Boot...............................................................................................................................................................................114
6.3.1 Boot sources.................................................................................................................................................114
6.3.2 Boot options................................................................................................................................................. 114
6.3.3 FOPT boot options.......................................................................................................................................114
6.3.4 Boot sequence.............................................................................................................................................. 115
Chapter 7
Kinetis ROM Bootloader
7.1 Chip-Specific Information............................................................................................................................................ 119
7.2 Introduction...................................................................................................................................................................120
7.3 Functional Description..................................................................................................................................................122
7.3.1 Memory Maps..............................................................................................................................................122
7.3.2 The Kinetis Bootloader Configuration Area (BCA)....................................................................................122
7.3.3 Start-up Process............................................................................................................................................125
7.3.4 Clock Configuration.....................................................................................................................................127
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
6 NXP Semiconductors
Section number Title Page
7.3.5 Bootloader Entry Point.................................................................................................................................128
7.3.6 Bootloader Protocol..................................................................................................................................... 129
7.3.7 Bootloader Packet Types............................................................................................................................. 134
7.3.8 Bootloader Command API...........................................................................................................................141
7.3.9 Bootloader Exit state....................................................................................................................................165
7.4 Peripherals Supported................................................................................................................................................... 165
7.4.1 I2C Peripheral.............................................................................................................................................. 165
7.4.2 SPI Peripheral.............................................................................................................................................. 167
7.4.3 QuadSPI Peripheral .....................................................................................................................................170
7.4.4 USB peripheral.............................................................................................................................................179
7.5 Get/SetProperty Command Properties..........................................................................................................................183
7.5.1 Property Definitions.....................................................................................................................................184
7.6 SB File Decryption Support..........................................................................................................................................186
7.6.1 Decryption using LTC................................................................................................................................. 186
7.7 CRC-32 Check on Application Data.............................................................................................................................187
7.8 Kinetis Bootloader Status Error Codes.........................................................................................................................187
Chapter 8
Power Management
8.1 Introduction...................................................................................................................................................................191
8.2 Clocking modes............................................................................................................................................................ 191
8.2.1 Partial Stop...................................................................................................................................................191
8.2.2 DMA Wakeup..............................................................................................................................................192
8.2.3 Compute Operation......................................................................................................................................193
8.2.4 Peripheral Doze............................................................................................................................................194
8.2.5 Clock Gating................................................................................................................................................ 195
8.3 Power modes description.............................................................................................................................................. 195
8.4 Entering and exiting power modes............................................................................................................................... 198
8.5 Power mode transitions.................................................................................................................................................198
8.6 Power modes shutdown sequencing............................................................................................................................. 199
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
NXP Semiconductors 7
Section number Title Page
8.7 Flash Program Restrictions...........................................................................................................................................200
8.8 Module Operation in Low Power Modes......................................................................................................................200
Chapter 9
Security
9.1 Introduction...................................................................................................................................................................205
9.2 Flash security................................................................................................................................................................ 205
9.3 Security interactions with other modules......................................................................................................................206
9.3.1 Security interactions with debug..................................................................................................................206
Chapter 10
Debug
10.1 Introduction...................................................................................................................................................................207
10.2 Debug port pin descriptions..........................................................................................................................................207
10.3 SWD status and control registers..................................................................................................................................208
10.3.1 MDM-AP control register............................................................................................................................209
10.3.2 MDM-AP status register.............................................................................................................................. 210
10.4 Debug resets..................................................................................................................................................................212
10.5 Micro trace buffer (MTB).............................................................................................................................................212
10.6 Debug in low power modes.......................................................................................................................................... 213
10.7 Debug and security....................................................................................................................................................... 214
Chapter 11
Signal Multiplexing and Signal Descriptions
11.1 Signal multiplexing introduction.................................................................................................................................. 215
11.2 Signal multiplexing integration.................................................................................................................................... 215
11.2.1 Port control and interrupt module features.................................................................................................. 216
11.2.2 Clock gating................................................................................................................................................. 217
11.2.3 Signal multiplexing constraints....................................................................................................................217
11.3 Pinous............................................................................................................................................................................217
11.3.1 KL82 signal multiplexing and pin assignments...........................................................................................217
11.3.2 KL82 Pinouts............................................................................................................................................... 222
11.4 Module signal description tables.................................................................................................................................. 228
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
8 NXP Semiconductors
Section number Title Page
11.4.1 Core Modules...............................................................................................................................................228
11.4.2 System modules........................................................................................................................................... 228
11.4.3 Clock Modules............................................................................................................................................. 229
11.4.4 Memories and memory interfaces................................................................................................................230
11.4.5 Analog..........................................................................................................................................................231
11.4.6 Timer Modules.............................................................................................................................................232
11.4.7 Communication interfaces........................................................................................................................... 233
11.4.8 Human-machine interfaces (HMI)...............................................................................................................236
Chapter 12
Port Control and Interrupts (PORT)
12.1 Introduction...................................................................................................................................................................237
12.2 Overview.......................................................................................................................................................................237
12.2.1 Features........................................................................................................................................................ 237
12.2.2 Modes of operation...................................................................................................................................... 238
12.3 External signal description............................................................................................................................................238
12.4 Detailed signal description............................................................................................................................................239
12.5 Memory map and register definition.............................................................................................................................239
12.5.1
Pin Control Register n (PORTx_PCRn).......................................................................................................246
12.5.2
Global Pin Control Low Register (PORTx_GPCLR)..................................................................................249
12.5.3
Global Pin Control High Register (PORTx_GPCHR).................................................................................249
12.5.4
Global Interrupt Control Low Register (PORTx_GICLR).......................................................................... 250
12.5.5
Global Interrupt Control High Register (PORTx_GICHR)......................................................................... 250
12.5.6
Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 251
12.6 Functional description...................................................................................................................................................251
12.6.1 Pin control....................................................................................................................................................251
12.6.2 Global pin control........................................................................................................................................ 252
12.6.3 Global interrupt control................................................................................................................................253
12.6.4 External interrupts........................................................................................................................................253
Chapter 13
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
NXP Semiconductors 9
Section number Title Page
System Integration Module (SIM)
13.1 Introduction...................................................................................................................................................................255
13.1.1 Features........................................................................................................................................................ 255
13.2 Memory map and register definition.............................................................................................................................255
13.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 257
13.2.2 System Options Register 2 (SIM_SOPT2).................................................................................................. 258
13.2.3 System Options Register 5 (SIM_SOPT5).................................................................................................. 260
13.2.4 System Options Register 7 (SIM_SOPT7).................................................................................................. 261
13.2.5 System Options Register 9 (SIM_SOPT9).................................................................................................. 263
13.2.6 System Device Identification Register (SIM_SDID)...................................................................................264
13.2.7 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................266
13.2.8 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................268
13.2.9 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................271
13.2.10 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................273
13.2.11 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................274
13.2.12 System Clock Divider Register 2 (SIM_CLKDIV2)...................................................................................277
13.2.13 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 278
13.2.14 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 279
13.2.15 Unique Identification Register High (SIM_UIDH)..................................................................................... 280
13.2.16 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................280
13.2.17 Unique Identification Register Mid Low (SIM_UIDML)........................................................................... 281
13.2.18 Unique Identification Register Low (SIM_UIDL)...................................................................................... 281
13.2.19 System Clock Divider Register 3 (SIM_CLKDIV3)...................................................................................282
13.2.20 Misc Control Register (SIM_MISCCTRL)................................................................................................. 283
13.2.21 Secure Key Register 0 (SIM_SECKEY0)................................................................................................... 284
13.2.22 Secure Key Register 1 (SIM_SECKEY1)................................................................................................... 285
13.2.23 Secure Key Register 2 (SIM_SECKEY2)................................................................................................... 285
13.2.24 Secure Key Register 3 (SIM_SECKEY3)................................................................................................... 286
Chapter 14
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
10 NXP Semiconductors
Section number Title Page
EMV SIM
14.1 Chip-specific EMVSIM information............................................................................................................................ 287
14.1.1 Overview......................................................................................................................................................287
14.1.2 EMV_SIM instantiations............................................................................................................................. 287
14.2 Introduction...................................................................................................................................................................287
14.2.1 Features........................................................................................................................................................ 288
14.3 Block Diagram..............................................................................................................................................................288
14.4 Design Overview.......................................................................................................................................................... 289
14.5 Signal Description.........................................................................................................................................................291
14.6 Memory Map and Registers..........................................................................................................................................291
14.6.1
Version ID Register (EMVSIMx_VER_ID)................................................................................................293
14.6.2
Parameter Register (EMVSIMx_PARAM)................................................................................................. 293
14.6.3
Clock Configuration Register (EMVSIMx_CLKCFG)............................................................................... 294
14.6.4
Baud Rate Divisor Register (EMVSIMx_DIVISOR)..................................................................................295
14.6.5
Control Register (EMVSIMx_CTRL)......................................................................................................... 296
14.6.6
Interrupt Mask Register (EMVSIMx_INT_MASK)....................................................................................300
14.6.7
Receiver Threshold Register (EMVSIMx_RX_THD).................................................................................302
14.6.8
Transmitter Threshold Register (EMVSIMx_TX_THD)............................................................................ 303
14.6.9
Receive Status Register (EMVSIMx_RX_STATUS)..................................................................................304
14.6.10
Transmitter Status Register (EMVSIMx_TX_STATUS)............................................................................307
14.6.11
Port Control and Status Register (EMVSIMx_PCSR).................................................................................310
14.6.12
Receive Data Read Buffer (EMVSIMx_RX_BUF).....................................................................................312
14.6.13
Transmit Data Buffer (EMVSIMx_TX_BUF).............................................................................................313
14.6.14
Transmitter Guard ETU Value Register (EMVSIMx_TX_GETU).............................................................313
14.6.15
Character Wait Time Value Register (EMVSIMx_CWT_VAL).................................................................314
14.6.16
Block Wait Time Value Register (EMVSIMx_BWT_VAL)...................................................................... 314
14.6.17
Block Guard Time Value Register (EMVSIMx_BGT_VAL)..................................................................... 314
14.6.18
General Purpose Counter 0 Timeout Value Register (EMVSIMx_GPCNT0_VAL)..................................315
14.6.19
General Purpose Counter 1 Timeout Value (EMVSIMx_GPCNT1_VAL)................................................ 315
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
NXP Semiconductors 11
Section number Title Page
14.7 Functional Description..................................................................................................................................................316
14.7.1 Initialization................................................................................................................................................. 316
14.7.2 Smart Card Interface and Control................................................................................................................ 318
14.7.3 EMV SIM Receiver..................................................................................................................................... 321
14.7.4 EMV SIM Transmitter.................................................................................................................................325
14.7.5 LRC and CRC.............................................................................................................................................. 327
14.7.6 Message Handling........................................................................................................................................329
14.7.7 Protocol Timers............................................................................................................................................331
14.7.8 Answer To Reset (ATR) Detection..............................................................................................................334
Chapter 15
Reset Control Module (RCM)
15.1 Introduction...................................................................................................................................................................339
15.2 Reset memory map and register descriptions............................................................................................................... 339
15.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................ 340
15.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................ 341
15.2.3 Reset Pin Filter Control register (RCM_RPFC).......................................................................................... 343
15.2.4 Reset Pin Filter Width register (RCM_RPFW)........................................................................................... 344
15.2.5 Force Mode Register (RCM_FM)................................................................................................................345
15.2.6 Mode Register (RCM_MR)......................................................................................................................... 346
15.2.7 Sticky System Reset Status Register 0 (RCM_SSRS0)...............................................................................347
15.2.8 Sticky System Reset Status Register 1 (RCM_SSRS1)...............................................................................348
Chapter 16
System Mode Controller (SMC)
16.1 Introduction...................................................................................................................................................................351
16.2 Modes of operation....................................................................................................................................................... 351
16.3 Memory map and register descriptions.........................................................................................................................353
16.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................354
16.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................355
16.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................357
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
12 NXP Semiconductors
Section number Title Page
16.3.4 Power Mode Status register (SMC_PMSTAT)........................................................................................... 358
16.4 Functional description...................................................................................................................................................359
16.4.1 Power mode transitions................................................................................................................................359
16.4.2 Power mode entry/exit sequencing.............................................................................................................. 362
16.4.3 Run modes....................................................................................................................................................364
16.4.4 Wait modes.................................................................................................................................................. 366
16.4.5 Stop modes...................................................................................................................................................367
16.4.6 Debug in low power modes......................................................................................................................... 371
Chapter 17
Power Management Controller (PMC)
17.1 Introduction...................................................................................................................................................................373
17.2 Features.........................................................................................................................................................................373
17.3 Low-voltage detect (LVD) system................................................................................................................................373
17.3.1 LVD reset operation.....................................................................................................................................374
17.3.2 LVD interrupt operation...............................................................................................................................374
17.3.3 Low-voltage warning (LVW) interrupt operation....................................................................................... 374
17.4 High-voltage detect (HVD) system.............................................................................................................................. 375
17.4.1 HVD reset operation.................................................................................................................................... 375
17.4.2 HVD interrupt operation.............................................................................................................................. 375
17.5 I/O retention..................................................................................................................................................................376
17.6 Memory map and register descriptions.........................................................................................................................376
17.6.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................ 377
17.6.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................ 378
17.6.3 Regulator Status And Control register (PMC_REGSC)..............................................................................379
17.6.4 High Voltage Detect Status And Control 1 register (PMC_HVDSC1).......................................................381
Chapter 18
Interrupt Multiplexer (INTMUX)
18.1 About this module.........................................................................................................................................................383
18.1.1 Introduction..................................................................................................................................................383
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
NXP Semiconductors 13
Section number Title Page
18.1.2 Features........................................................................................................................................................ 383
18.1.3 Block diagram..............................................................................................................................................383
18.2 Memory Map and register definition............................................................................................................................ 384
18.2.1
Channel n Control Status Register (INTMUXx_CHn_CSR)...................................................................... 385
18.2.2
Channel n Vector Number Register (INTMUXx_CHn_VEC)....................................................................386
18.2.3
Channel n Interrupt Enable Register (INTMUXx_CHn_IER_31_0).......................................................... 387
18.2.4
Channel n Interrupt Pending Register (INTMUXx_CHn_IPR_31_0).........................................................387
18.3 Functional Description..................................................................................................................................................388
18.3.1 Configuring Output Channels...................................................................................................................... 388
18.3.2 INTMUX Vectors........................................................................................................................................ 388
Chapter 19
Low-Leakage Wakeup Unit (LLWU)
19.1 Chip-specific LLWU information.................................................................................................................................391
19.1.1 Wake-up sources..........................................................................................................................................391
19.2 Introduction...................................................................................................................................................................392
19.2.1 Features........................................................................................................................................................ 393
19.2.2 Modes of operation...................................................................................................................................... 393
19.2.3 Block diagram..............................................................................................................................................394
19.3 LLWU signal descriptions............................................................................................................................................ 394
19.4 Memory map/register definition................................................................................................................................... 395
19.4.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................396
19.4.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................397
19.4.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................398
19.4.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................399
19.4.5 LLWU Pin Enable 5 register (LLWU_PE5)................................................................................................400
19.4.6 LLWU Pin Enable 6 register (LLWU_PE6)................................................................................................401
19.4.7 LLWU Pin Enable 7 register (LLWU_PE7)................................................................................................402
19.4.8 LLWU Pin Enable 8 register (LLWU_PE8)................................................................................................404
19.4.9 LLWU Module Enable register (LLWU_ME)............................................................................................ 405
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
14 NXP Semiconductors
Section number Title Page
19.4.10 LLWU Pin Flag 1 register (LLWU_PF1)....................................................................................................406
19.4.11 LLWU Pin Flag 2 register (LLWU_PF2)....................................................................................................408
19.4.12 LLWU Pin Flag 3 register (LLWU_PF3)....................................................................................................410
19.4.13 LLWU Pin Flag 4 register (LLWU_PF4)....................................................................................................411
19.4.14 LLWU Module Flag 5 register (LLWU_MF5)............................................................................................413
19.4.15 LLWU Pin Filter 1 register (LLWU_FILT1).............................................................................................. 415
19.4.16 LLWU Pin Filter 2 register (LLWU_FILT2).............................................................................................. 416
19.4.17 LLWU Pin Filter 3 register (LLWU_FILT3).............................................................................................. 417
19.4.18 LLWU Pin Filter 4 register (LLWU_FILT4).............................................................................................. 418
19.5 Functional description...................................................................................................................................................419
19.5.1 LLS mode.....................................................................................................................................................419
19.5.2 VLLS modes................................................................................................................................................ 419
19.5.3 Initialization................................................................................................................................................. 420
Chapter 20
Miscellaneous Control Module (MCM)
20.1 Introduction...................................................................................................................................................................421
20.1.1 Features........................................................................................................................................................ 421
20.2 Memory map/register descriptions............................................................................................................................... 421
20.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................422
20.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 422
20.2.3 Platform Control Register (MCM_PLACR)................................................................................................423
20.2.4 Compute Operation Control Register (MCM_CPO)................................................................................... 426
Chapter 21
Crossbar-Lite Switch (AXBS-Lite)
21.1 Chip-specific AXBS-Lite information..........................................................................................................................429
21.1.1 Crossbar-Light Switch Master Assignments - with System MPU...............................................................429
21.1.2 Crossbar-Light Switch Slave Assignments - with System MPU.................................................................429
21.2 Introduction...................................................................................................................................................................430
21.2.1 Features........................................................................................................................................................ 430
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
NXP Semiconductors 15
Section number Title Page
21.3 Memory Map / Register Definition...............................................................................................................................430
21.4 Functional Description..................................................................................................................................................430
21.4.1 General operation.........................................................................................................................................430
Chapter 22
Peripheral Bridge (AIPS-Lite)
22.1 Chip-specific AIPS-Lite information............................................................................................................................433
22.1.1 Number of peripheral bridges...................................................................................................................... 433
22.1.2 Memory maps.............................................................................................................................................. 433
22.1.3 AIPS_Lite MPRA register reset value.........................................................................................................433
22.1.4 AIPS_Lite PACRE-P register reset values.................................................................................................. 433
22.2 Introduction...................................................................................................................................................................434
22.2.1 Features........................................................................................................................................................ 434
22.2.2 General operation.........................................................................................................................................434
22.3 Memory map/register definition................................................................................................................................... 434
22.3.1 Master Privilege Register A (AIPS_MPRA)............................................................................................... 435
22.3.2
Peripheral Access Control Register (AIPS_PACRn)...................................................................................438
22.3.3
Peripheral Access Control Register (AIPS_PACRn)...................................................................................444
22.4 Functional description...................................................................................................................................................448
22.4.1 Access support............................................................................................................................................. 448
Chapter 23
Memory Protection Unit (MPU)
23.1 Chip-specific MPU information................................................................................................................................... 451
23.1.1 MPU slave port assignments........................................................................................................................451
23.1.2 MPU logical bus master assignments.......................................................................................................... 451
23.1.3 MPU access violation indications................................................................................................................451
23.1.4 Reset values for RGD0 registers..................................................................................................................452
23.1.5 Write access restrictions for RGD0 registers...............................................................................................452
23.2 Introduction...................................................................................................................................................................453
23.3 Overview.......................................................................................................................................................................453
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
16 NXP Semiconductors
Section number Title Page
23.3.1 Block diagram..............................................................................................................................................453
23.3.2 Features........................................................................................................................................................ 454
23.4 Memory map/register definition................................................................................................................................... 455
23.4.1 Control/Error Status Register (MPU_CESR).............................................................................................. 457
23.4.2
Error Address Register, slave port n (MPU_EARn)....................................................................................459
23.4.3
Error Detail Register, slave port n (MPU_EDRn)....................................................................................... 459
23.4.4
Region Descriptor n, Word 0 (MPU_RGDn_WORD0).............................................................................. 460
23.4.5
Region Descriptor n, Word 1 (MPU_RGDn_WORD1).............................................................................. 461
23.4.6
Region Descriptor n, Word 2 (MPU_RGDn_WORD2).............................................................................. 461
23.4.7
Region Descriptor n, Word 3 (MPU_RGDn_WORD3).............................................................................. 464
23.4.8
Region Descriptor Alternate Access Control n (MPU_RGDAACn)...........................................................465
23.5 Functional description...................................................................................................................................................467
23.5.1 Access evaluation macro..............................................................................................................................467
23.5.2 Putting it all together and error terminations............................................................................................... 469
23.5.3 Power management......................................................................................................................................470
23.6 Initialization information.............................................................................................................................................. 470
23.7 Application information................................................................................................................................................470
Chapter 24
Bit Manipulation Engine (BME)
24.1 Introduction...................................................................................................................................................................473
24.1.1 Overview......................................................................................................................................................474
24.1.2 Features........................................................................................................................................................ 474
24.1.3 Modes of operation...................................................................................................................................... 475
24.2 Memory map and register definition.............................................................................................................................475
24.3 Functional description...................................................................................................................................................475
24.3.1 BME decorated stores.................................................................................................................................. 476
24.3.2 BME decorated loads...................................................................................................................................483
24.3.3 Additional details on decorated addresses and GPIO accesses....................................................................489
24.4 Application information................................................................................................................................................490
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
NXP Semiconductors 17
Section number Title Page
Chapter 25
Direct Memory Access Multiplexer (DMAMUX)
25.1 Chip-specific DMAMUX information......................................................................................................................... 493
25.1.1 DMAMUX request sources......................................................................................................................... 493
25.1.2 DMA transfers via PIT trigger.....................................................................................................................495
25.2 Introduction...................................................................................................................................................................495
25.2.1 Overview......................................................................................................................................................495
25.2.2 Features........................................................................................................................................................ 496
25.2.3 Modes of operation...................................................................................................................................... 496
25.3 External signal description............................................................................................................................................497
25.4 Memory map/register definition................................................................................................................................... 497
25.4.1
Channel Configuration register (DMAMUX_CHCFGn)............................................................................ 498
25.5 Functional description...................................................................................................................................................498
25.5.1 DMA channels with periodic triggering capability......................................................................................499
25.5.2 DMA channels with no triggering capability...............................................................................................501
25.5.3 Always-enabled DMA sources.................................................................................................................... 501
25.6 Initialization/application information........................................................................................................................... 503
25.6.1 Reset.............................................................................................................................................................503
25.6.2 Enabling and configuring sources................................................................................................................503
Chapter 26
Enhanced Direct Memory Access (eDMA)
26.1 Introduction...................................................................................................................................................................507
26.1.1 eDMA system block diagram...................................................................................................................... 507
26.1.2 Block parts................................................................................................................................................... 508
26.1.3 Features........................................................................................................................................................ 509
26.2 Modes of operation....................................................................................................................................................... 510
26.3 Memory map/register definition................................................................................................................................... 511
26.3.1 TCD memory............................................................................................................................................... 511
26.3.2 TCD initialization........................................................................................................................................ 511
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
18 NXP Semiconductors
Section number Title Page
26.3.3 TCD structure...............................................................................................................................................511
26.3.4 Reserved memory and bit fields...................................................................................................................512
26.3.1 Control Register (DMA_CR).......................................................................................................................519
26.3.2 Error Status Register (DMA_ES)................................................................................................................ 522
26.3.3 Enable Request Register (DMA_ERQ)....................................................................................................... 524
26.3.4 Enable Error Interrupt Register (DMA_EEI)...............................................................................................526
26.3.5 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................. 527
26.3.6 Set Enable Error Interrupt Register (DMA_SEEI)...................................................................................... 528
26.3.7 Clear Enable Request Register (DMA_CERQ)...........................................................................................529
26.3.8 Set Enable Request Register (DMA_SERQ)...............................................................................................530
26.3.9 Clear DONE Status Bit Register (DMA_CDNE)........................................................................................531
26.3.10 Set START Bit Register (DMA_SSRT)...................................................................................................... 532
26.3.11 Clear Error Register (DMA_CERR)............................................................................................................533
26.3.12 Clear Interrupt Request Register (DMA_CINT)......................................................................................... 534
26.3.13 Interrupt Request Register (DMA_INT)......................................................................................................535
26.3.14 Error Register (DMA_ERR)........................................................................................................................ 536
26.3.15 Hardware Request Status Register (DMA_HRS)........................................................................................ 538
26.3.16 Enable Asynchronous Request in Stop Register (DMA_EARS).................................................................540
26.3.17
Channel n Priority Register (DMA_DCHPRIn).......................................................................................... 541
26.3.18
TCD Source Address (DMA_TCDn_SADDR)...........................................................................................542
26.3.19
TCD Signed Source Address Offset (DMA_TCDn_SOFF)........................................................................542
26.3.20
TCD Transfer Attributes (DMA_TCDn_ATTR).........................................................................................543
26.3.21
TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................. 544
26.3.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).......................................................................................................544
26.3.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)..................................................................................................... 546
26.3.24
TCD Last Source Address Adjustment (DMA_TCDn_SLAST).................................................................547
26.3.25
TCD Destination Address (DMA_TCDn_DADDR)...................................................................................547
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
NXP Semiconductors 19
Section number Title Page
26.3.26
TCD Signed Destination Address Offset (DMA_TCDn_DOFF)................................................................548
26.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES)...........................................................................................................548
26.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO)............................................................................................................ 550
26.3.29
TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).......... 551
26.3.30
TCD Control and Status (DMA_TCDn_CSR)............................................................................................ 551
26.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES)...........................................................................................................554
26.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO)............................................................................................................ 555
26.4 Functional description...................................................................................................................................................556
26.4.1 eDMA basic data flow................................................................................................................................. 556
26.4.2 Fault reporting and handling........................................................................................................................559
26.4.3 Channel preemption..................................................................................................................................... 561
26.4.4 Performance................................................................................................................................................. 561
26.5 Initialization/application information........................................................................................................................... 566
26.5.1 eDMA initialization..................................................................................................................................... 566
26.5.2 Programming errors..................................................................................................................................... 568
26.5.3 Arbitration mode considerations..................................................................................................................568
26.5.4 Performing DMA transfers.......................................................................................................................... 569
26.5.5 Monitoring transfer descriptor status........................................................................................................... 573
26.5.6 Channel Linking...........................................................................................................................................575
26.5.7 Dynamic programming................................................................................................................................ 576
Chapter 27
External Watchdog Monitor (EWM)
27.1 Chip-specific EWM information.................................................................................................................................. 581
27.1.1 EWM clocks.................................................................................................................................................581
27.1.2 EWM low-power modes.............................................................................................................................. 581
27.1.3 EWM_OUT pin state in low power modes..................................................................................................581
KL82 Sub-Family Reference Manual, Rev. 3, 08/2016
20 NXP Semiconductors
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
-
1
-
2
-
3
-
4
-
5
-
6
-
7
-
8
-
9
-
10
-
11
-
12
-
13
-
14
-
15
-
16
-
17
-
18
-
19
-
20
-
21
-
22
-
23
-
24
-
25
-
26
-
27
-
28
-
29
-
30
-
31
-
32
-
33
-
34
-
35
-
36
-
37
-
38
-
39
-
40
-
41
-
42
-
43
-
44
-
45
-
46
-
47
-
48
-
49
-
50
-
51
-
52
-
53
-
54
-
55
-
56
-
57
-
58
-
59
-
60
-
61
-
62
-
63
-
64
-
65
-
66
-
67
-
68
-
69
-
70
-
71
-
72
-
73
-
74
-
75
-
76
-
77
-
78
-
79
-
80
-
81
-
82
-
83
-
84
-
85
-
86
-
87
-
88
-
89
-
90
-
91
-
92
-
93
-
94
-
95
-
96
-
97
-
98
-
99
-
100
-
101
-
102
-
103
-
104
-
105
-
106
-
107
-
108
-
109
-
110
-
111
-
112
-
113
-
114
-
115
-
116
-
117
-
118
-
119
-
120
-
121
-
122
-
123
-
124
-
125
-
126
-
127
-
128
-
129
-
130
-
131
-
132
-
133
-
134
-
135
-
136
-
137
-
138
-
139
-
140
-
141
-
142
-
143
-
144
-
145
-
146
-
147
-
148
-
149
-
150
-
151
-
152
-
153
-
154
-
155
-
156
-
157
-
158
-
159
-
160
-
161
-
162
-
163
-
164
-
165
-
166
-
167
-
168
-
169
-
170
-
171
-
172
-
173
-
174
-
175
-
176
-
177
-
178
-
179
-
180
-
181
-
182
-
183
-
184
-
185
-
186
-
187
-
188
-
189
-
190
-
191
-
192
-
193
-
194
-
195
-
196
-
197
-
198
-
199
-
200
-
201
-
202
-
203
-
204
-
205
-
206
-
207
-
208
-
209
-
210
-
211
-
212
-
213
-
214
-
215
-
216
-
217
-
218
-
219
-
220
-
221
-
222
-
223
-
224
-
225
-
226
-
227
-
228
-
229
-
230
-
231
-
232
-
233
-
234
-
235
-
236
-
237
-
238
-
239
-
240
-
241
-
242
-
243
-
244
-
245
-
246
-
247
-
248
-
249
-
250
-
251
-
252
-
253
-
254
-
255
-
256
-
257
-
258
-
259
-
260
-
261
-
262
-
263
-
264
-
265
-
266
-
267
-
268
-
269
-
270
-
271
-
272
-
273
-
274
-
275
-
276
-
277
-
278
-
279
-
280
-
281
-
282
-
283
-
284
-
285
-
286
-
287
-
288
-
289
-
290
-
291
-
292
-
293
-
294
-
295
-
296
-
297
-
298
-
299
-
300
-
301
-
302
-
303
-
304
-
305
-
306
-
307
-
308
-
309
-
310
-
311
-
312
-
313
-
314
-
315
-
316
-
317
-
318
-
319
-
320
-
321
-
322
-
323
-
324
-
325
-
326
-
327
-
328
-
329
-
330
-
331
-
332
-
333
-
334
-
335
-
336
-
337
-
338
-
339
-
340
-
341
-
342
-
343
-
344
-
345
-
346
-
347
-
348
-
349
-
350
-
351
-
352
-
353
-
354
-
355
-
356
-
357
-
358
-
359
-
360
-
361
-
362
-
363
-
364
-
365
-
366
-
367
-
368
-
369
-
370
-
371
-
372
-
373
-
374
-
375
-
376
-
377
-
378
-
379
-
380
-
381
-
382
-
383
-
384
-
385
-
386
-
387
-
388
-
389
-
390
-
391
-
392
-
393
-
394
-
395
-
396
-
397
-
398
-
399
-
400
-
401
-
402
-
403
-
404
-
405
-
406
-
407
-
408
-
409
-
410
-
411
-
412
-
413
-
414
-
415
-
416
-
417
-
418
-
419
-
420
-
421
-
422
-
423
-
424
-
425
-
426
-
427
-
428
-
429
-
430
-
431
-
432
-
433
-
434
-
435
-
436
-
437
-
438
-
439
-
440
-
441
-
442
-
443
-
444
-
445
-
446
-
447
-
448
-
449
-
450
-
451
-
452
-
453
-
454
-
455
-
456
-
457
-
458
-
459
-
460
-
461
-
462
-
463
-
464
-
465
-
466
-
467
-
468
-
469
-
470
-
471
-
472
-
473
-
474
-
475
-
476
-
477
-
478
-
479
-
480
-
481
-
482
-
483
-
484
-
485
-
486
-
487
-
488
-
489
-
490
-
491
-
492
-
493
-
494
-
495
-
496
-
497
-
498
-
499
-
500
-
501
-
502
-
503
-
504
-
505
-
506
-
507
-
508
-
509
-
510
-
511
-
512
-
513
-
514
-
515
-
516
-
517
-
518
-
519
-
520
-
521
-
522
-
523
-
524
-
525
-
526
-
527
-
528
-
529
-
530
-
531
-
532
-
533
-
534
-
535
-
536
-
537
-
538
-
539
-
540
-
541
-
542
-
543
-
544
-
545
-
546
-
547
-
548
-
549
-
550
-
551
-
552
-
553
-
554
-
555
-
556
-
557
-
558
-
559
-
560
-
561
-
562
-
563
-
564
-
565
-
566
-
567
-
568
-
569
-
570
-
571
-
572
-
573
-
574
-
575
-
576
-
577
-
578
-
579
-
580
-
581
-
582
-
583
-
584
-
585
-
586
-
587
-
588
-
589
-
590
-
591
-
592
-
593
-
594
-
595
-
596
-
597
-
598
-
599
-
600
-
601
-
602
-
603
-
604
-
605
-
606
-
607
-
608
-
609
-
610
-
611
-
612
-
613
-
614
-
615
-
616
-
617
-
618
-
619
-
620
-
621
-
622
-
623
-
624
-
625
-
626
-
627
-
628
-
629
-
630
-
631
-
632
-
633
-
634
-
635
-
636
-
637
-
638
-
639
-
640
-
641
-
642
-
643
-
644
-
645
-
646
-
647
-
648
-
649
-
650
-
651
-
652
-
653
-
654
-
655
-
656
-
657
-
658
-
659
-
660
-
661
-
662
-
663
-
664
-
665
-
666
-
667
-
668
-
669
-
670
-
671
-
672
-
673
-
674
-
675
-
676
-
677
-
678
-
679
-
680
-
681
-
682
-
683
-
684
-
685
-
686
-
687
-
688
-
689
-
690
-
691
-
692
-
693
-
694
-
695
-
696
-
697
-
698
-
699
-
700
-
701
-
702
-
703
-
704
-
705
-
706
-
707
-
708
-
709
-
710
-
711
-
712
-
713
-
714
-
715
-
716
-
717
-
718
-
719
-
720
-
721
-
722
-
723
-
724
-
725
-
726
-
727
-
728
-
729
-
730
-
731
-
732
-
733
-
734
-
735
-
736
-
737
-
738
-
739
-
740
-
741
-
742
-
743
-
744
-
745
-
746
-
747
-
748
-
749
-
750
-
751
-
752
-
753
-
754
-
755
-
756
-
757
-
758
-
759
-
760
-
761
-
762
-
763
-
764
-
765
-
766
-
767
-
768
-
769
-
770
-
771
-
772
-
773
-
774
-
775
-
776
-
777
-
778
-
779
-
780
-
781
-
782
-
783
-
784
-
785
-
786
-
787
-
788
-
789
-
790
-
791
-
792
-
793
-
794
-
795
-
796
-
797
-
798
-
799
-
800
-
801
-
802
-
803
-
804
-
805
-
806
-
807
-
808
-
809
-
810
-
811
-
812
-
813
-
814
-
815
-
816
-
817
-
818
-
819
-
820
-
821
-
822
-
823
-
824
-
825
-
826
-
827
-
828
-
829
-
830
-
831
-
832
-
833
-
834
-
835
-
836
-
837
-
838
-
839
-
840
-
841
-
842
-
843
-
844
-
845
-
846
-
847
-
848
-
849
-
850
-
851
-
852
-
853
-
854
-
855
-
856
-
857
-
858
-
859
-
860
-
861
-
862
-
863
-
864
-
865
-
866
-
867
-
868
-
869
-
870
-
871
-
872
-
873
-
874
-
875
-
876
-
877
-
878
-
879
-
880
-
881
-
882
-
883
-
884
-
885
-
886
-
887
-
888
-
889
-
890
-
891
-
892
-
893
-
894
-
895
-
896
-
897
-
898
-
899
-
900
-
901
-
902
-
903
-
904
-
905
-
906
-
907
-
908
-
909
-
910
-
911
-
912
-
913
-
914
-
915
-
916
-
917
-
918
-
919
-
920
-
921
-
922
-
923
-
924
-
925
-
926
-
927
-
928
-
929
-
930
-
931
-
932
-
933
-
934
-
935
-
936
-
937
-
938
-
939
-
940
-
941
-
942
-
943
-
944
-
945
-
946
-
947
-
948
-
949
-
950
-
951
-
952
-
953
-
954
-
955
-
956
-
957
-
958
-
959
-
960
-
961
-
962
-
963
-
964
-
965
-
966
-
967
-
968
-
969
-
970
-
971
-
972
-
973
-
974
-
975
-
976
-
977
-
978
-
979
-
980
-
981
-
982
-
983
-
984
-
985
-
986
-
987
-
988
-
989
-
990
-
991
-
992
-
993
-
994
-
995
-
996
-
997
-
998
-
999
-
1000
-
1001
-
1002
-
1003
-
1004
-
1005
-
1006
-
1007
-
1008
-
1009
-
1010
-
1011
-
1012
-
1013
-
1014
-
1015
-
1016
-
1017
-
1018
-
1019
-
1020
-
1021
-
1022
-
1023
-
1024
-
1025
-
1026
-
1027
-
1028
-
1029
-
1030
-
1031
-
1032
-
1033
-
1034
-
1035
-
1036
-
1037
-
1038
-
1039
-
1040
-
1041
-
1042
-
1043
-
1044
-
1045
-
1046
-
1047
-
1048
-
1049
-
1050
-
1051
-
1052
-
1053
-
1054
-
1055
-
1056
-
1057
-
1058
-
1059
-
1060
-
1061
-
1062
-
1063
-
1064
-
1065
-
1066
-
1067
-
1068
-
1069
-
1070
-
1071
-
1072
-
1073
-
1074
-
1075
-
1076
-
1077
-
1078
-
1079
-
1080
-
1081
-
1082
-
1083
-
1084
-
1085
-
1086
-
1087
-
1088
-
1089
-
1090
-
1091
-
1092
-
1093
-
1094
-
1095
-
1096
-
1097
-
1098
-
1099
-
1100
-
1101
-
1102
-
1103
-
1104
-
1105
-
1106
-
1107
-
1108
-
1109
-
1110
-
1111
-
1112
-
1113
-
1114
-
1115
-
1116
-
1117
-
1118
-
1119
-
1120
-
1121
-
1122
-
1123
-
1124
-
1125
-
1126
-
1127
-
1128
-
1129
-
1130
-
1131
-
1132
-
1133
-
1134
-
1135
-
1136
-
1137
-
1138
-
1139
-
1140
-
1141
-
1142
-
1143
-
1144
-
1145
-
1146
-
1147
-
1148
-
1149
-
1150
-
1151
-
1152
-
1153
-
1154
-
1155
-
1156
-
1157
-
1158
-
1159
-
1160
-
1161
-
1162
-
1163
-
1164
-
1165
-
1166
-
1167
-
1168
-
1169
-
1170
-
1171
-
1172
-
1173
-
1174
-
1175
-
1176
-
1177
-
1178
-
1179
-
1180
-
1181
-
1182
-
1183
-
1184
-
1185
-
1186
-
1187
-
1188
-
1189
-
1190
-
1191
-
1192
-
1193
-
1194
-
1195
-
1196
-
1197
-
1198
-
1199
-
1200
-
1201
-
1202
-
1203
-
1204
-
1205
-
1206
-
1207
-
1208
-
1209
-
1210
-
1211
-
1212
-
1213
-
1214
-
1215
-
1216
-
1217
-
1218
-
1219
-
1220
-
1221
-
1222
-
1223
-
1224
-
1225
-
1226
-
1227
-
1228
-
1229
-
1230
-
1231
-
1232
-
1233
-
1234
-
1235
-
1236
-
1237
-
1238
-
1239
-
1240
-
1241
-
1242
-
1243
-
1244
-
1245
-
1246
-
1247
-
1248
-
1249
-
1250
-
1251
-
1252
-
1253
-
1254
-
1255
-
1256
-
1257
-
1258
-
1259
-
1260
-
1261
-
1262
-
1263
-
1264
-
1265
-
1266
-
1267
-
1268
-
1269
-
1270
-
1271
-
1272
-
1273
-
1274
-
1275
-
1276
-
1277
-
1278
-
1279
-
1280
-
1281
-
1282
-
1283
-
1284
-
1285
-
1286
-
1287
-
1288
-
1289
-
1290
-
1291
-
1292
-
1293
-
1294
-
1295
-
1296
-
1297
-
1298
-
1299
-
1300
-
1301
-
1302
-
1303
-
1304
-
1305
-
1306
-
1307
-
1308
-
1309
-
1310
-
1311
-
1312
-
1313
-
1314
-
1315
-
1316
-
1317
-
1318
-
1319
-
1320
-
1321
-
1322
-
1323
-
1324
-
1325
-
1326
-
1327
-
1328
-
1329
-
1330
-
1331
-
1332
-
1333
-
1334
-
1335
-
1336
-
1337
-
1338
-
1339
-
1340
-
1341
-
1342
-
1343
-
1344
-
1345
-
1346
-
1347
-
1348
-
1349
-
1350
-
1351
-
1352
-
1353
-
1354
-
1355
-
1356
-
1357
-
1358
-
1359
-
1360
-
1361
-
1362
-
1363
-
1364
-
1365
-
1366
-
1367
-
1368
-
1369
-
1370
-
1371
-
1372
-
1373
-
1374
-
1375
-
1376
-
1377
-
1378
-
1379
-
1380
-
1381
-
1382
-
1383
-
1384
-
1385
-
1386
-
1387
-
1388
-
1389
-
1390
-
1391
-
1392
-
1393
-
1394
-
1395
-
1396
-
1397
-
1398
-
1399
-
1400
-
1401
-
1402
-
1403
-
1404
-
1405
-
1406
-
1407
-
1408
-
1409
-
1410
-
1411
-
1412
-
1413
-
1414
-
1415
-
1416
-
1417
-
1418
-
1419
-
1420
-
1421
-
1422
-
1423
-
1424
-
1425
-
1426
-
1427
-
1428
-
1429
-
1430
-
1431
-
1432
-
1433
-
1434
-
1435
-
1436
-
1437
-
1438
-
1439
-
1440
-
1441
-
1442
-
1443
-
1444
-
1445
-
1446
-
1447
-
1448
-
1449
-
1450
-
1451
-
1452
-
1453
-
1454
-
1455
-
1456
-
1457
-
1458
-
1459
-
1460
-
1461
-
1462
-
1463
-
1464
-
1465
-
1466
-
1467
-
1468
-
1469
-
1470
-
1471
-
1472
-
1473
-
1474
-
1475
-
1476
-
1477
-
1478
-
1479
-
1480
-
1481
-
1482
-
1483
-
1484
-
1485
-
1486
-
1487
-
1488
-
1489
-
1490
-
1491
-
1492
-
1493
-
1494
-
1495
-
1496
-
1497
-
1498
-
1499
-
1500
-
1501
-
1502
-
1503
-
1504
-
1505
-
1506
-
1507
-
1508
-
1509
-
1510
-
1511
-
1512
-
1513
-
1514
-
1515
-
1516
-
1517
-
1518
-
1519
-
1520
-
1521
-
1522
-
1523
-
1524
-
1525
-
1526
-
1527
-
1528
-
1529
-
1530
-
1531
-
1532
-
1533
-
1534
-
1535
-
1536
-
1537
-
1538
-
1539
-
1540
-
1541
-
1542
-
1543
-
1544
-
1545
-
1546
-
1547
-
1548
-
1549
-
1550
-
1551
-
1552
-
1553
-
1554
-
1555
-
1556
-
1557
-
1558
-
1559
-
1560
-
1561
-
1562
-
1563
-
1564
-
1565
-
1566
-
1567
-
1568
-
1569
-
1570
-
1571
-
1572
-
1573
-
1574
-
1575
-
1576
-
1577
-
1578
-
1579
-
1580
-
1581
-
1582
-
1583
-
1584
-
1585
-
1586
-
1587
-
1588
-
1589
-
1590
-
1591
-
1592
-
1593
-
1594
-
1595
-
1596
-
1597
-
1598
-
1599
-
1600
-
1601
-
1602
-
1603
-
1604
-
1605
-
1606
-
1607
-
1608
-
1609
-
1610
-
1611
-
1612
-
1613
-
1614
-
1615
-
1616
-
1617
-
1618
-
1619
-
1620
-
1621
-
1622
-
1623
Ask a question and I''ll find the answer in the document
Finding information in a document is now easier with AI
Related papers
Other documents
-
Silicon Labs EFM32WG Reference guide
-
Texas Instruments DLPC150 Programmer's (Rev. A) User guide
-
Pepperl+Fuchs VBG-PN-K20-DMD Owner's manual
-
Jameco Electronics Superpro Series User manual
-
STMicroelectronics STM32F756VG Reference guide
-
NXP Semiconductors MC9S12G Reference guide
-
Omega HHP350 Series Owner's manual
-
-
-
