K02F Sub-Family Reference Manual
Supports: MK02FN128VLH10, MK02FN128VLF10,
MK02FN128VFM10, MK02FN64VLH10, MK02FN64VLF10,
MK02FN64VFM10
Document Number: K02P64M100SFARM
Rev. 2, 08/2016
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................39
1.1.1 Purpose...........................................................................................................................................................39
1.1.2 Audience........................................................................................................................................................ 39
1.2 Conventions.................................................................................................................................................................. 39
1.2.1 Numbering systems........................................................................................................................................39
1.2.2 Typographic notation..................................................................................................................................... 40
1.2.3 Special terms..................................................................................................................................................40
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................41
2.2 Module Functional Categories......................................................................................................................................41
2.2.1 ARM® Cortex®-M4 Core Modules..............................................................................................................42
2.2.2 System Modules.............................................................................................................................................43
2.2.3 Memories and Memory Interfaces................................................................................................................. 43
2.2.4 Clocks.............................................................................................................................................................44
2.2.5 Security and Integrity modules...................................................................................................................... 44
2.2.6 Analog modules............................................................................................................................................. 44
2.2.7 Timer modules............................................................................................................................................... 45
2.2.8 Communication interfaces............................................................................................................................. 46
2.2.9 Human-machine interfaces............................................................................................................................ 46
2.3 Orderable part numbers.................................................................................................................................................47
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................49
3.2 Core modules................................................................................................................................................................ 49
3.2.1 ARM Cortex-M4 Core Configuration............................................................................................................49
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
NXP Semiconductors 3
Section number Title Page
3.2.2 Nested Vectored Interrupt Controller (NVIC) Configuration........................................................................51
3.2.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration...........................................................57
3.2.4 FPU Configuration.........................................................................................................................................58
3.2.5 JTAG Controller Configuration.....................................................................................................................58
3.3 System modules............................................................................................................................................................ 59
3.3.1 SIM Configuration......................................................................................................................................... 59
3.3.2 System Mode Controller (SMC) Configuration.............................................................................................60
3.3.3 PMC Configuration........................................................................................................................................60
3.3.4 Low-Leakage Wake-up Unit (LLWU) Configuration...................................................................................61
3.3.5 MCM Configuration...................................................................................................................................... 62
3.3.6 Crossbar-Light Switch Configuration............................................................................................................63
3.3.7 Peripheral Bridge Configuration....................................................................................................................65
3.3.8 DMA request multiplexer configuration........................................................................................................66
3.3.9 DMA Controller Configuration..................................................................................................................... 68
3.3.10 External Watchdog Monitor (EWM) Configuration......................................................................................69
3.3.11 Watchdog Configuration................................................................................................................................71
3.4 Clock modules.............................................................................................................................................................. 72
3.4.1 MCG Configuration....................................................................................................................................... 72
3.4.2 OSC Configuration........................................................................................................................................ 74
3.5 Memories and memory interfaces.................................................................................................................................74
3.5.1 Flash Memory Configuration.........................................................................................................................74
3.5.2 Flash Memory Controller Configuration....................................................................................................... 77
3.5.3 SRAM Configuration.....................................................................................................................................78
3.6 Security......................................................................................................................................................................... 80
3.6.1 CRC Configuration........................................................................................................................................ 80
3.7 Analog...........................................................................................................................................................................81
3.7.1 16-bit SAR ADC Configuration.................................................................................................................... 81
3.7.2 CMP Configuration........................................................................................................................................86
3.7.3 12-bit DAC Configuration............................................................................................................................. 88
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
4 NXP Semiconductors
Section number Title Page
3.7.4 VREF Configuration......................................................................................................................................89
3.8 Timers........................................................................................................................................................................... 90
3.8.1 PDB Configuration........................................................................................................................................ 90
3.8.2 FlexTimer Configuration............................................................................................................................... 93
3.8.3 PIT Configuration.......................................................................................................................................... 99
3.8.4 Low-power timer configuration.....................................................................................................................100
3.9 Communication interfaces............................................................................................................................................ 102
3.9.1 SPI configuration........................................................................................................................................... 102
3.9.2 I2C Configuration.......................................................................................................................................... 105
3.9.3 UART Configuration..................................................................................................................................... 106
3.10 Human-machine interfaces........................................................................................................................................... 108
3.10.1 GPIO configuration........................................................................................................................................108
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................111
4.2 System memory map.....................................................................................................................................................111
4.2.1 Aliased bit-band regions................................................................................................................................ 112
4.2.2 Flash Access Control Introduction.................................................................................................................114
4.3 Flash Memory Map.......................................................................................................................................................114
4.3.1 Alternate Non-Volatile IRC User Trim Description......................................................................................115
4.4 SRAM memory map.....................................................................................................................................................115
4.5 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................116
4.5.1 Read-after-write sequence and required serialization of memory operations................................................116
4.5.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map.......................................................................................... 116
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................120
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................123
5.2 Programming model......................................................................................................................................................123
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
NXP Semiconductors 5
Section number Title Page
5.3 High-Level device clocking diagram............................................................................................................................123
5.4 Clock definitions...........................................................................................................................................................124
5.4.1 Device clock summary...................................................................................................................................125
5.5 Internal clocking requirements..................................................................................................................................... 127
5.5.1 Clock divider values after reset......................................................................................................................128
5.5.2 VLPR mode clocking.....................................................................................................................................128
5.6 Clock Gating.................................................................................................................................................................129
5.7 Module clocks...............................................................................................................................................................129
5.7.1 PMC 1-kHz LPO clock..................................................................................................................................130
5.7.2 IRC 48MHz clock.......................................................................................................................................... 130
5.7.3 WDOG clocking............................................................................................................................................ 131
5.7.4 Debug trace clock...........................................................................................................................................131
5.7.5 PORT digital filter clocking...........................................................................................................................132
5.7.6 LPTMR clocking............................................................................................................................................132
5.7.7 CLKOUT32K clocking..................................................................................................................................133
5.7.8 UART clocking..............................................................................................................................................133
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................135
6.2 Reset..............................................................................................................................................................................135
6.2.1 Power-on reset (POR).................................................................................................................................... 136
6.2.2 System reset sources...................................................................................................................................... 136
6.2.3 MCU Resets................................................................................................................................................... 139
6.2.4 Reset Pin ....................................................................................................................................................... 141
6.2.5 Debug resets...................................................................................................................................................141
6.3 Boot...............................................................................................................................................................................142
6.3.1 Boot sources...................................................................................................................................................142
6.3.2 Boot options................................................................................................................................................... 142
6.3.3 FOPT boot options.........................................................................................................................................143
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
6 NXP Semiconductors
Section number Title Page
6.3.4 Boot sequence................................................................................................................................................ 144
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................147
7.2 Clocking modes............................................................................................................................................................ 147
7.2.1 Partial Stop.....................................................................................................................................................147
7.2.2 DMA Wakeup................................................................................................................................................148
7.2.3 Compute Operation........................................................................................................................................149
7.2.4 Peripheral Doze..............................................................................................................................................150
7.2.5 Clock Gating.................................................................................................................................................. 151
7.3 Power Modes Description.............................................................................................................................................151
7.4 Entering and exiting power modes............................................................................................................................... 153
7.5 Power mode transitions.................................................................................................................................................154
7.6 Power modes shutdown sequencing............................................................................................................................. 155
7.7 Flash Program Restrictions...........................................................................................................................................156
7.8 Module Operation in Low Power Modes......................................................................................................................156
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................161
8.2 Flash Security............................................................................................................................................................... 161
8.3 Security Interactions with other Modules.....................................................................................................................162
8.3.1 Security Interactions with Debug...................................................................................................................162
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................163
9.1.1 References......................................................................................................................................................165
9.2 The Debug Port.............................................................................................................................................................166
9.2.1 JTAG-to-SWD change sequence................................................................................................................... 166
9.2.2 JTAG-to-cJTAG change sequence.................................................................................................................167
9.3 Debug Port Pin Descriptions.........................................................................................................................................167
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
NXP Semiconductors 7
Section number Title Page
9.4 System TAP connection................................................................................................................................................167
9.4.1 IR Codes.........................................................................................................................................................168
9.5 JTAG status and control registers.................................................................................................................................168
9.5.1 MDM-AP Control Register............................................................................................................................169
9.5.2 MDM-AP Status Register.............................................................................................................................. 171
9.6 Debug Resets................................................................................................................................................................ 172
9.7 AHB-AP........................................................................................................................................................................173
9.8 ITM............................................................................................................................................................................... 173
9.9 Core Trace Connectivity...............................................................................................................................................174
9.10 TPIU..............................................................................................................................................................................174
9.11 DWT............................................................................................................................................................................. 174
9.12 Debug in Low Power Modes........................................................................................................................................ 175
9.12.1 Debug Module State in Low Power Modes...................................................................................................175
9.13 Debug & Security......................................................................................................................................................... 176
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................177
10.2 Signal Multiplexing Integration....................................................................................................................................177
10.2.1 Port control and interrupt module features.................................................................................................... 178
10.2.2 Clock gating................................................................................................................................................... 179
10.2.3 Signal multiplexing constraints......................................................................................................................179
10.3 Pinout............................................................................................................................................................................179
10.3.1 K02F Signal Multiplexing and Pin Assignments...........................................................................................179
10.3.2 K02F Pinouts..................................................................................................................................................182
10.4 Module Signal Description Tables................................................................................................................................185
10.4.1 Core Modules.................................................................................................................................................185
10.4.2 System Modules.............................................................................................................................................186
10.4.3 Clock Modules............................................................................................................................................... 186
10.4.4 Analog............................................................................................................................................................187
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
8 NXP Semiconductors
Section number Title Page
10.4.5 Timer Modules...............................................................................................................................................188
10.4.6 Communication Interfaces............................................................................................................................. 189
10.4.7 Human-Machine Interfaces (HMI)................................................................................................................ 190
Chapter 11
Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................191
11.2 Overview.......................................................................................................................................................................191
11.2.1 Features.......................................................................................................................................................... 191
11.2.2 Modes of operation........................................................................................................................................ 192
11.3 External signal description............................................................................................................................................193
11.4 Detailed signal description............................................................................................................................................193
11.5 Memory map and register definition.............................................................................................................................193
11.5.1
Pin Control Register n (PORTx_PCRn).........................................................................................................200
11.5.2
Global Pin Control Low Register (PORTx_GPCLR)....................................................................................203
11.5.3
Global Pin Control High Register (PORTx_GPCHR)...................................................................................203
11.5.4
Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 204
11.5.5
Digital Filter Enable Register (PORTx_DFER).............................................................................................204
11.5.6
Digital Filter Clock Register (PORTx_DFCR)..............................................................................................205
11.5.7
Digital Filter Width Register (PORTx_DFWR)............................................................................................ 205
11.6 Functional description...................................................................................................................................................206
11.6.1 Pin control......................................................................................................................................................206
11.6.2 Global pin control.......................................................................................................................................... 207
11.6.3 External interrupts..........................................................................................................................................207
11.6.4 Digital filter....................................................................................................................................................208
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................211
12.1.1 Features.......................................................................................................................................................... 211
12.2 Memory map and register definition.............................................................................................................................212
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
NXP Semiconductors 9
Section number Title Page
12.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 213
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)......................................................................................214
12.2.3 System Options Register 2 (SIM_SOPT2).................................................................................................... 215
12.2.4 System Options Register 4 (SIM_SOPT4).................................................................................................... 217
12.2.5 System Options Register 5 (SIM_SOPT5).................................................................................................... 219
12.2.6 System Options Register 7 (SIM_SOPT7).................................................................................................... 221
12.2.7 System Options Register 8 (SIM_SOPT8).................................................................................................... 222
12.2.8 System Device Identification Register (SIM_SDID).....................................................................................224
12.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................226
12.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................228
12.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................229
12.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)..............................................................................232
12.2.13 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................232
12.2.14 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 235
12.2.15 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 236
12.2.16 Unique Identification Register High (SIM_UIDH)....................................................................................... 237
12.2.17 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................237
12.2.18 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 238
12.2.19 Unique Identification Register Low (SIM_UIDL)........................................................................................ 238
12.3 Functional description...................................................................................................................................................238
Chapter 13
Kinetis Flashloader
13.1 Chip-Specific Information............................................................................................................................................ 239
13.2 Introduction...................................................................................................................................................................239
13.3 Functional Description..................................................................................................................................................241
13.3.1 Memory Maps................................................................................................................................................241
13.3.2 Start-up Process..............................................................................................................................................241
13.3.3 Clock Configuration.......................................................................................................................................242
13.3.4 Flashloader Protocol...................................................................................................................................... 242
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
10 NXP Semiconductors
Section number Title Page
13.3.5 Flashloader Packet Types...............................................................................................................................247
13.3.6 Flashloader Command API............................................................................................................................254
13.4 Peripherals Supported................................................................................................................................................... 273
13.4.1 I2C Peripheral................................................................................................................................................ 273
13.4.2 SPI Peripheral................................................................................................................................................ 275
13.4.3 UART Peripheral........................................................................................................................................... 277
13.5 Get/SetProperty Command Properties..........................................................................................................................280
13.5.1 Property Definitions.......................................................................................................................................281
13.6 Kinetis Flashloader Status Error Codes........................................................................................................................ 283
Chapter 14
Reset Control Module (RCM)
14.1 Introduction...................................................................................................................................................................285
14.2 Reset memory map and register descriptions............................................................................................................... 285
14.2.1 System Reset Status Register 0 (RCM_SRS0).............................................................................................. 286
14.2.2 System Reset Status Register 1 (RCM_SRS1).............................................................................................. 287
14.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................ 289
14.2.4 Reset Pin Filter Width register (RCM_RPFW)............................................................................................. 290
14.2.5 Sticky System Reset Status Register 0 (RCM_SSRS0).................................................................................291
14.2.6 Sticky System Reset Status Register 1 (RCM_SSRS1).................................................................................292
Chapter 15
System Mode Controller (SMC)
15.1 Introduction...................................................................................................................................................................295
15.2 Modes of operation....................................................................................................................................................... 295
15.3 Memory map and register descriptions.........................................................................................................................297
15.3.1 Power Mode Protection register (SMC_PMPROT).......................................................................................298
15.3.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................299
15.3.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................301
15.3.4 Power Mode Status register (SMC_PMSTAT)............................................................................................. 302
15.4 Functional description...................................................................................................................................................303
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
NXP Semiconductors 11
Section number Title Page
15.4.1 Power mode transitions..................................................................................................................................303
15.4.2 Power mode entry/exit sequencing................................................................................................................ 306
15.4.3 Run modes......................................................................................................................................................308
15.4.4 Wait modes.................................................................................................................................................... 310
15.4.5 Stop modes.....................................................................................................................................................310
15.4.6 Debug in low power modes........................................................................................................................... 313
Chapter 16
Power Management Controller (PMC)
16.1 Introduction...................................................................................................................................................................315
16.2 Features.........................................................................................................................................................................315
16.3 Low-voltage detect (LVD) system................................................................................................................................315
16.3.1 LVD reset operation.......................................................................................................................................316
16.3.2 LVD interrupt operation.................................................................................................................................316
16.3.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 316
16.4 I/O retention..................................................................................................................................................................317
16.5 Memory map and register descriptions.........................................................................................................................317
16.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1).......................................................... 318
16.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2).......................................................... 319
16.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................320
Chapter 17
Low-Leakage Wakeup Unit (LLWU)
17.1 Introduction...................................................................................................................................................................323
17.1.1 Features.......................................................................................................................................................... 323
17.1.2 Modes of operation........................................................................................................................................ 324
17.1.3 Block diagram................................................................................................................................................325
17.2 LLWU signal descriptions............................................................................................................................................ 326
17.3 Memory map/register definition................................................................................................................................... 326
17.3.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................327
17.3.2 LLWU Pin Enable 2 register (LLWU_PE2)..................................................................................................328
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
12 NXP Semiconductors
Section number Title Page
17.3.3 LLWU Pin Enable 3 register (LLWU_PE3)..................................................................................................329
17.3.4 LLWU Pin Enable 4 register (LLWU_PE4)..................................................................................................330
17.3.5 LLWU Module Enable register (LLWU_ME).............................................................................................. 331
17.3.6 LLWU Flag 1 register (LLWU_F1)...............................................................................................................333
17.3.7 LLWU Flag 2 register (LLWU_F2)...............................................................................................................335
17.3.8 LLWU Flag 3 register (LLWU_F3)...............................................................................................................336
17.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................ 338
17.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................ 339
17.4 Functional description...................................................................................................................................................340
17.4.1 LLS mode.......................................................................................................................................................341
17.4.2 VLLS modes.................................................................................................................................................. 341
17.4.3 Initialization................................................................................................................................................... 341
Chapter 18
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................343
18.1.1 Features.......................................................................................................................................................... 343
18.2 Memory map/register descriptions............................................................................................................................... 343
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................344
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 344
18.2.3 Crossbar Switch (AXBS) Control Register (MCM_PLACR)....................................................................... 345
18.2.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................... 345
18.2.5 Compute Operation Control Register (MCM_CPO)..................................................................................... 348
18.3 Functional description...................................................................................................................................................349
18.3.1 Interrupts........................................................................................................................................................ 349
Chapter 19
Crossbar Switch Lite (AXBS-Lite)
19.1 Introduction...................................................................................................................................................................351
19.1.1 Features.......................................................................................................................................................... 351
19.2 Memory Map / Register Definition...............................................................................................................................352
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
NXP Semiconductors 13
Section number Title Page
19.3 Functional Description..................................................................................................................................................352
19.3.1 General operation...........................................................................................................................................352
19.3.2 Arbitration......................................................................................................................................................353
19.4 Initialization/application information........................................................................................................................... 354
Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................355
20.1.1 Features.......................................................................................................................................................... 355
20.1.2 General operation...........................................................................................................................................355
20.2 Memory map/register definition................................................................................................................................... 356
20.3 Functional description...................................................................................................................................................356
20.3.1 Access support............................................................................................................................................... 356
Chapter 21
Direct Memory Access Multiplexer (DMAMUX)
21.1 Introduction...................................................................................................................................................................357
21.1.1 Overview........................................................................................................................................................357
21.1.2 Features.......................................................................................................................................................... 358
21.1.3 Modes of operation........................................................................................................................................ 358
21.2 External signal description............................................................................................................................................359
21.3 Memory map/register definition................................................................................................................................... 359
21.3.1
Channel Configuration register (DMAMUX_CHCFGn).............................................................................. 359
21.4 Functional description...................................................................................................................................................360
21.4.1 DMA channels with periodic triggering capability........................................................................................361
21.4.2 DMA channels with no triggering capability.................................................................................................363
21.4.3 Always-enabled DMA sources...................................................................................................................... 363
21.5 Initialization/application information........................................................................................................................... 365
21.5.1 Reset...............................................................................................................................................................365
21.5.2 Enabling and configuring sources..................................................................................................................365
Chapter 22
Enhanced Direct Memory Access (eDMA)
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
14 NXP Semiconductors
Section number Title Page
22.1 Introduction...................................................................................................................................................................369
22.1.1 eDMA system block diagram........................................................................................................................ 369
22.1.2 Block parts..................................................................................................................................................... 370
22.1.3 Features.......................................................................................................................................................... 371
22.2 Modes of operation....................................................................................................................................................... 372
22.3 Memory map/register definition................................................................................................................................... 373
22.3.1 TCD memory................................................................................................................................................. 373
22.3.2 TCD initialization.......................................................................................................................................... 373
22.3.3 TCD structure.................................................................................................................................................373
22.3.4 Reserved memory and bit fields.....................................................................................................................374
22.3.5 Control Register (DMA_CR).........................................................................................................................378
22.3.6 Error Status Register (DMA_ES).................................................................................................................. 381
22.3.7 Enable Request Register (DMA_ERQ)......................................................................................................... 383
22.3.8 Enable Error Interrupt Register (DMA_EEI).................................................................................................384
22.3.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................... 385
22.3.10 Set Enable Error Interrupt Register (DMA_SEEI)........................................................................................ 386
22.3.11 Clear Enable Request Register (DMA_CERQ).............................................................................................387
22.3.12 Set Enable Request Register (DMA_SERQ).................................................................................................388
22.3.13 Clear DONE Status Bit Register (DMA_CDNE)..........................................................................................389
22.3.14 Set START Bit Register (DMA_SSRT)........................................................................................................ 390
22.3.15 Clear Error Register (DMA_CERR)..............................................................................................................391
22.3.16 Clear Interrupt Request Register (DMA_CINT)........................................................................................... 392
22.3.17 Interrupt Request Register (DMA_INT)........................................................................................................393
22.3.18 Error Register (DMA_ERR).......................................................................................................................... 394
22.3.19 Hardware Request Status Register (DMA_HRS).......................................................................................... 395
22.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS)...................................................................397
22.3.21
Channel n Priority Register (DMA_DCHPRIn)............................................................................................ 398
22.3.22
TCD Source Address (DMA_TCDn_SADDR).............................................................................................399
22.3.23
TCD Signed Source Address Offset (DMA_TCDn_SOFF)..........................................................................399
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
NXP Semiconductors 15
Section number Title Page
22.3.24
TCD Transfer Attributes (DMA_TCDn_ATTR)...........................................................................................400
22.3.25
TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................... 401
22.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMA_TCDn_NBYTES_MLOFFNO).........................................................................................................401
22.3.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMA_TCDn_NBYTES_MLOFFYES)....................................................................................................... 403
22.3.28
TCD Last Source Address Adjustment (DMA_TCDn_SLAST)...................................................................404
22.3.29
TCD Destination Address (DMA_TCDn_DADDR).....................................................................................404
22.3.30
TCD Signed Destination Address Offset (DMA_TCDn_DOFF)..................................................................405
22.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_CITER_ELINKYES).............................................................................................................405
22.3.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_CITER_ELINKNO).............................................................................................................. 407
22.3.33
TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)............ 408
22.3.34
TCD Control and Status (DMA_TCDn_CSR).............................................................................................. 408
22.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMA_TCDn_BITER_ELINKYES).............................................................................................................411
22.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMA_TCDn_BITER_ELINKNO).............................................................................................................. 412
22.4 Functional description...................................................................................................................................................413
22.4.1 eDMA basic data flow................................................................................................................................... 413
22.4.2 Fault reporting and handling..........................................................................................................................416
22.4.3 Channel preemption....................................................................................................................................... 418
22.4.4 Performance................................................................................................................................................... 418
22.5 Initialization/application information........................................................................................................................... 423
22.5.1 eDMA initialization....................................................................................................................................... 423
22.5.2 Programming errors....................................................................................................................................... 425
22.5.3 Arbitration mode considerations....................................................................................................................425
22.5.4 Performing DMA transfers............................................................................................................................ 426
22.5.5 Monitoring transfer descriptor status............................................................................................................. 430
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
16 NXP Semiconductors
Section number Title Page
22.5.6 Channel Linking.............................................................................................................................................432
22.5.7 Dynamic programming.................................................................................................................................. 433
22.5.8 Lockstep.........................................................................................................................................................436
Chapter 23
External Watchdog Monitor (EWM)
23.1 Introduction...................................................................................................................................................................439
23.1.1 Features.......................................................................................................................................................... 439
23.1.2 Modes of Operation....................................................................................................................................... 440
23.1.3 Block Diagram............................................................................................................................................... 441
23.2 EWM Signal Descriptions............................................................................................................................................ 442
23.3 Memory Map/Register Definition.................................................................................................................................442
23.3.1 Control Register (EWM_CTRL)................................................................................................................... 442
23.3.2 Service Register (EWM_SERV)....................................................................................................................443
23.3.3 Compare Low Register (EWM_CMPL)........................................................................................................443
23.3.4 Compare High Register (EWM_CMPH).......................................................................................................444
23.3.5 Clock Prescaler Register (EWM_CLKPRESCALER)..................................................................................445
23.4 Functional Description..................................................................................................................................................445
23.4.1 The EWM_out Signal.................................................................................................................................... 445
23.4.2 The EWM_in Signal...................................................................................................................................... 446
23.4.3 EWM Counter................................................................................................................................................447
23.4.4 EWM Compare Registers.............................................................................................................................. 447
23.4.5 EWM Refresh Mechanism.............................................................................................................................447
23.4.6 EWM Interrupt...............................................................................................................................................448
23.4.7 Counter clock prescaler..................................................................................................................................448
Chapter 24
Watchdog Timer (WDOG)
24.1 Introduction...................................................................................................................................................................449
24.2 Features.........................................................................................................................................................................449
24.3 Functional overview......................................................................................................................................................450
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
NXP Semiconductors 17
Section number Title Page
24.3.1 Unlocking and updating the watchdog...........................................................................................................452
24.3.2 Watchdog configuration time (WCT)............................................................................................................453
24.3.3 Refreshing the watchdog................................................................................................................................454
24.3.4 Windowed mode of operation........................................................................................................................454
24.3.5 Watchdog disabled mode of operation...........................................................................................................454
24.3.6 Debug modes of operation............................................................................................................................. 454
24.4 Testing the watchdog.................................................................................................................................................... 455
24.4.1 Quick test....................................................................................................................................................... 456
24.4.2 Byte test..........................................................................................................................................................456
24.5 Backup reset generator..................................................................................................................................................457
24.6 Generated resets and interrupts.....................................................................................................................................458
24.7 Memory map and register definition.............................................................................................................................458
24.7.1 Watchdog Status and Control Register High (WDOG_STCTRLH)............................................................. 459
24.7.2 Watchdog Status and Control Register Low (WDOG_STCTRLL).............................................................. 461
24.7.3 Watchdog Time-out Value Register High (WDOG_TOVALH)...................................................................461
24.7.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)....................................................................462
24.7.5 Watchdog Window Register High (WDOG_WINH).................................................................................... 462
24.7.6 Watchdog Window Register Low (WDOG_WINL)..................................................................................... 463
24.7.7 Watchdog Refresh register (WDOG_REFRESH)......................................................................................... 463
24.7.8 Watchdog Unlock register (WDOG_UNLOCK)...........................................................................................463
24.7.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................... 464
24.7.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................... 464
24.7.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................... 465
24.7.12 Watchdog Prescaler register (WDOG_PRESC)............................................................................................ 465
24.8 Watchdog operation with 8-bit access.......................................................................................................................... 465
24.8.1 General guideline........................................................................................................................................... 465
24.8.2 Refresh and unlock operations with 8-bit access...........................................................................................466
24.9 Restrictions on watchdog operation..............................................................................................................................467
Chapter 25
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
18 NXP Semiconductors
Section number Title Page
Multipurpose Clock Generator (MCG)
25.1 Introduction...................................................................................................................................................................469
25.1.1 Features.......................................................................................................................................................... 469
25.1.2 Modes of Operation....................................................................................................................................... 471
25.2 External Signal Description.......................................................................................................................................... 472
25.3 Memory Map/Register Definition.................................................................................................................................472
25.3.1 MCG Control 1 Register (MCG_C1).............................................................................................................473
25.3.2 MCG Control 2 Register (MCG_C2).............................................................................................................474
25.3.3 MCG Control 3 Register (MCG_C3).............................................................................................................475
25.3.4 MCG Control 4 Register (MCG_C4).............................................................................................................476
25.3.5 MCG Control 5 Register (MCG_C5).............................................................................................................477
25.3.5 MCG Control 6 Register (MCG_C6).............................................................................................................477
25.3.6 MCG Status Register (MCG_S).................................................................................................................... 478
25.3.7 MCG Status and Control Register (MCG_SC)..............................................................................................479
25.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH).............................................................. 480
25.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)................................................................481
25.3.10 MCG Control 7 Register (MCG_C7).............................................................................................................481
25.3.11 MCG Control 8 Register (MCG_C8).............................................................................................................482
25.3.12 MCG Control 12 Register (MCG_C12).........................................................................................................483
25.3.12 MCG Status 2 Register (MCG_S2)............................................................................................................... 483
25.3.12 MCG Test 3 Register (MCG_T3).................................................................................................................. 483
25.4 Functional description...................................................................................................................................................484
25.4.1 MCG mode state diagram.............................................................................................................................. 484
25.4.2 Low-power bit usage......................................................................................................................................487
25.4.3 MCG Internal Reference Clocks....................................................................................................................487
25.4.4 External Reference Clock.............................................................................................................................. 487
25.4.5 MCG Fixed Frequency Clock .......................................................................................................................488
25.4.6 MCG Auto TRIM (ATM)..............................................................................................................................488
25.5 Initialization / Application information........................................................................................................................ 490
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
NXP Semiconductors 19
Section number Title Page
25.5.1 MCG module initialization sequence.............................................................................................................490
25.5.2 Using a 32.768 kHz reference........................................................................................................................492
25.5.3 MCG mode switching.................................................................................................................................... 493
Chapter 26
Oscillator (OSC)
26.1 Introduction...................................................................................................................................................................501
26.2 Features and Modes...................................................................................................................................................... 501
26.3 Block Diagram..............................................................................................................................................................502
26.4 OSC Signal Descriptions.............................................................................................................................................. 502
26.5 External Crystal / Resonator Connections.................................................................................................................... 503
26.6 External Clock Connections......................................................................................................................................... 504
26.7 Memory Map/Register Definitions...............................................................................................................................505
26.7.1 OSC Memory Map/Register Definition.........................................................................................................505
26.8 Functional Description..................................................................................................................................................507
26.8.1 OSC module states.........................................................................................................................................507
26.8.2 OSC module modes....................................................................................................................................... 509
26.8.3 Counter...........................................................................................................................................................511
26.8.4 Reference clock pin requirements..................................................................................................................511
26.9 Reset..............................................................................................................................................................................511
26.10 Low power modes operation.........................................................................................................................................512
26.11 Interrupts.......................................................................................................................................................................512
Chapter 27
Flash Memory Controller (FMC)
27.1 Introduction...................................................................................................................................................................513
27.1.1 Overview........................................................................................................................................................513
27.1.2 Features.......................................................................................................................................................... 513
27.2 Modes of operation....................................................................................................................................................... 514
27.3 External signal description............................................................................................................................................514
27.4 Memory map and register descriptions.........................................................................................................................514
K02F Sub-Family Reference Manual, Rev. 2, 08/2016
20 NXP Semiconductors
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
-
1
-
2
-
3
-
4
-
5
-
6
-
7
-
8
-
9
-
10
-
11
-
12
-
13
-
14
-
15
-
16
-
17
-
18
-
19
-
20
-
21
-
22
-
23
-
24
-
25
-
26
-
27
-
28
-
29
-
30
-
31
-
32
-
33
-
34
-
35
-
36
-
37
-
38
-
39
-
40
-
41
-
42
-
43
-
44
-
45
-
46
-
47
-
48
-
49
-
50
-
51
-
52
-
53
-
54
-
55
-
56
-
57
-
58
-
59
-
60
-
61
-
62
-
63
-
64
-
65
-
66
-
67
-
68
-
69
-
70
-
71
-
72
-
73
-
74
-
75
-
76
-
77
-
78
-
79
-
80
-
81
-
82
-
83
-
84
-
85
-
86
-
87
-
88
-
89
-
90
-
91
-
92
-
93
-
94
-
95
-
96
-
97
-
98
-
99
-
100
-
101
-
102
-
103
-
104
-
105
-
106
-
107
-
108
-
109
-
110
-
111
-
112
-
113
-
114
-
115
-
116
-
117
-
118
-
119
-
120
-
121
-
122
-
123
-
124
-
125
-
126
-
127
-
128
-
129
-
130
-
131
-
132
-
133
-
134
-
135
-
136
-
137
-
138
-
139
-
140
-
141
-
142
-
143
-
144
-
145
-
146
-
147
-
148
-
149
-
150
-
151
-
152
-
153
-
154
-
155
-
156
-
157
-
158
-
159
-
160
-
161
-
162
-
163
-
164
-
165
-
166
-
167
-
168
-
169
-
170
-
171
-
172
-
173
-
174
-
175
-
176
-
177
-
178
-
179
-
180
-
181
-
182
-
183
-
184
-
185
-
186
-
187
-
188
-
189
-
190
-
191
-
192
-
193
-
194
-
195
-
196
-
197
-
198
-
199
-
200
-
201
-
202
-
203
-
204
-
205
-
206
-
207
-
208
-
209
-
210
-
211
-
212
-
213
-
214
-
215
-
216
-
217
-
218
-
219
-
220
-
221
-
222
-
223
-
224
-
225
-
226
-
227
-
228
-
229
-
230
-
231
-
232
-
233
-
234
-
235
-
236
-
237
-
238
-
239
-
240
-
241
-
242
-
243
-
244
-
245
-
246
-
247
-
248
-
249
-
250
-
251
-
252
-
253
-
254
-
255
-
256
-
257
-
258
-
259
-
260
-
261
-
262
-
263
-
264
-
265
-
266
-
267
-
268
-
269
-
270
-
271
-
272
-
273
-
274
-
275
-
276
-
277
-
278
-
279
-
280
-
281
-
282
-
283
-
284
-
285
-
286
-
287
-
288
-
289
-
290
-
291
-
292
-
293
-
294
-
295
-
296
-
297
-
298
-
299
-
300
-
301
-
302
-
303
-
304
-
305
-
306
-
307
-
308
-
309
-
310
-
311
-
312
-
313
-
314
-
315
-
316
-
317
-
318
-
319
-
320
-
321
-
322
-
323
-
324
-
325
-
326
-
327
-
328
-
329
-
330
-
331
-
332
-
333
-
334
-
335
-
336
-
337
-
338
-
339
-
340
-
341
-
342
-
343
-
344
-
345
-
346
-
347
-
348
-
349
-
350
-
351
-
352
-
353
-
354
-
355
-
356
-
357
-
358
-
359
-
360
-
361
-
362
-
363
-
364
-
365
-
366
-
367
-
368
-
369
-
370
-
371
-
372
-
373
-
374
-
375
-
376
-
377
-
378
-
379
-
380
-
381
-
382
-
383
-
384
-
385
-
386
-
387
-
388
-
389
-
390
-
391
-
392
-
393
-
394
-
395
-
396
-
397
-
398
-
399
-
400
-
401
-
402
-
403
-
404
-
405
-
406
-
407
-
408
-
409
-
410
-
411
-
412
-
413
-
414
-
415
-
416
-
417
-
418
-
419
-
420
-
421
-
422
-
423
-
424
-
425
-
426
-
427
-
428
-
429
-
430
-
431
-
432
-
433
-
434
-
435
-
436
-
437
-
438
-
439
-
440
-
441
-
442
-
443
-
444
-
445
-
446
-
447
-
448
-
449
-
450
-
451
-
452
-
453
-
454
-
455
-
456
-
457
-
458
-
459
-
460
-
461
-
462
-
463
-
464
-
465
-
466
-
467
-
468
-
469
-
470
-
471
-
472
-
473
-
474
-
475
-
476
-
477
-
478
-
479
-
480
-
481
-
482
-
483
-
484
-
485
-
486
-
487
-
488
-
489
-
490
-
491
-
492
-
493
-
494
-
495
-
496
-
497
-
498
-
499
-
500
-
501
-
502
-
503
-
504
-
505
-
506
-
507
-
508
-
509
-
510
-
511
-
512
-
513
-
514
-
515
-
516
-
517
-
518
-
519
-
520
-
521
-
522
-
523
-
524
-
525
-
526
-
527
-
528
-
529
-
530
-
531
-
532
-
533
-
534
-
535
-
536
-
537
-
538
-
539
-
540
-
541
-
542
-
543
-
544
-
545
-
546
-
547
-
548
-
549
-
550
-
551
-
552
-
553
-
554
-
555
-
556
-
557
-
558
-
559
-
560
-
561
-
562
-
563
-
564
-
565
-
566
-
567
-
568
-
569
-
570
-
571
-
572
-
573
-
574
-
575
-
576
-
577
-
578
-
579
-
580
-
581
-
582
-
583
-
584
-
585
-
586
-
587
-
588
-
589
-
590
-
591
-
592
-
593
-
594
-
595
-
596
-
597
-
598
-
599
-
600
-
601
-
602
-
603
-
604
-
605
-
606
-
607
-
608
-
609
-
610
-
611
-
612
-
613
-
614
-
615
-
616
-
617
-
618
-
619
-
620
-
621
-
622
-
623
-
624
-
625
-
626
-
627
-
628
-
629
-
630
-
631
-
632
-
633
-
634
-
635
-
636
-
637
-
638
-
639
-
640
-
641
-
642
-
643
-
644
-
645
-
646
-
647
-
648
-
649
-
650
-
651
-
652
-
653
-
654
-
655
-
656
-
657
-
658
-
659
-
660
-
661
-
662
-
663
-
664
-
665
-
666
-
667
-
668
-
669
-
670
-
671
-
672
-
673
-
674
-
675
-
676
-
677
-
678
-
679
-
680
-
681
-
682
-
683
-
684
-
685
-
686
-
687
-
688
-
689
-
690
-
691
-
692
-
693
-
694
-
695
-
696
-
697
-
698
-
699
-
700
-
701
-
702
-
703
-
704
-
705
-
706
-
707
-
708
-
709
-
710
-
711
-
712
-
713
-
714
-
715
-
716
-
717
-
718
-
719
-
720
-
721
-
722
-
723
-
724
-
725
-
726
-
727
-
728
-
729
-
730
-
731
-
732
-
733
-
734
-
735
-
736
-
737
-
738
-
739
-
740
-
741
-
742
-
743
-
744
-
745
-
746
-
747
-
748
-
749
-
750
-
751
-
752
-
753
-
754
-
755
-
756
-
757
-
758
-
759
-
760
-
761
-
762
-
763
-
764
-
765
-
766
-
767
-
768
-
769
-
770
-
771
-
772
-
773
-
774
-
775
-
776
-
777
-
778
-
779
-
780
-
781
-
782
-
783
-
784
-
785
-
786
-
787
-
788
-
789
-
790
-
791
-
792
-
793
-
794
-
795
-
796
-
797
-
798
-
799
-
800
-
801
-
802
-
803
-
804
-
805
-
806
-
807
-
808
-
809
-
810
-
811
-
812
-
813
-
814
-
815
-
816
-
817
-
818
-
819
-
820
-
821
-
822
-
823
-
824
-
825
-
826
-
827
-
828
-
829
-
830
-
831
-
832
-
833
-
834
-
835
-
836
-
837
-
838
-
839
-
840
-
841
-
842
-
843
-
844
-
845
-
846
-
847
-
848
-
849
-
850
-
851
-
852
-
853
-
854
-
855
-
856
-
857
-
858
-
859
-
860
-
861
-
862
-
863
-
864
-
865
-
866
-
867
-
868
-
869
-
870
-
871
-
872
-
873
-
874
-
875
-
876
-
877
-
878
-
879
-
880
-
881
-
882
-
883
-
884
-
885
-
886
-
887
-
888
-
889
-
890
-
891
-
892
-
893
-
894
-
895
-
896
-
897
-
898
-
899
-
900
-
901
-
902
-
903
-
904
-
905
-
906
-
907
-
908
-
909
-
910
-
911
-
912
-
913
-
914
-
915
-
916
-
917
-
918
-
919
-
920
-
921
-
922
-
923
-
924
-
925
-
926
-
927
-
928
-
929
-
930
-
931
-
932
-
933
-
934
-
935
-
936
-
937
-
938
-
939
-
940
-
941
-
942
-
943
-
944
-
945
-
946
-
947
-
948
-
949
-
950
-
951
-
952
-
953
-
954
-
955
-
956
-
957
-
958
-
959
-
960
-
961
-
962
-
963
-
964
-
965
-
966
-
967
-
968
-
969
-
970
-
971
-
972
-
973
-
974
-
975
-
976
-
977
-
978
-
979
-
980
-
981
-
982
-
983
-
984
-
985
-
986
-
987
-
988
-
989
-
990
-
991
-
992
-
993
-
994
-
995
-
996
-
997
-
998
-
999
-
1000
-
1001
-
1002
-
1003
-
1004
-
1005
-
1006
-
1007
-
1008
-
1009
-
1010
-
1011
-
1012
-
1013
-
1014
-
1015
-
1016
-
1017
-
1018
-
1019
-
1020
-
1021
-
1022
-
1023
-
1024
-
1025
-
1026
-
1027
-
1028
-
1029
-
1030
-
1031
-
1032
-
1033
-
1034
-
1035
-
1036
-
1037
-
1038
-
1039
-
1040
-
1041
-
1042
-
1043
-
1044
-
1045
-
1046
-
1047
-
1048
-
1049
-
1050
-
1051
-
1052
-
1053
-
1054
-
1055
-
1056
-
1057
-
1058
-
1059
-
1060
-
1061
-
1062
-
1063
-
1064
-
1065
-
1066
-
1067
-
1068
-
1069
-
1070
-
1071
-
1072
-
1073
-
1074
-
1075
-
1076
-
1077
-
1078
-
1079
-
1080
-
1081
-
1082
-
1083
-
1084
-
1085
-
1086
-
1087
-
1088
-
1089
-
1090
-
1091
-
1092
-
1093
-
1094
-
1095
Ask a question and I''ll find the answer in the document
Finding information in a document is now easier with AI
Related papers
Other documents
-
Freescale Semiconductor MK22FN256VMP12 Reference guide
-
NXP Semiconductors MC9S12G Reference guide
-
ARM Cortex r1p3 Datasheet
-
Denkovi DAEnetIP3 User manual
-
Infineon ROTATE KNOB 3D 2 GO KIT User manual
-
Silicon Labs EFM32JG1 Reference guide
-
-
ST & T UPSD3212C User manual
-
Vaisala HMM105 User manual
-
