MC56F826xx Reference Manual
Supports MC56F82646VLF, MC56F82643VLC, MC56F82623VLC
Document Number: MC56F826XXRM
Rev. 0, 09/2018
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................33
1.1.1 Purpose...........................................................................................................................................................33
1.1.2 Audience........................................................................................................................................................ 33
1.2 Conventions.................................................................................................................................................................. 33
1.2.1 Numbering systems........................................................................................................................................33
1.2.2 Typographic notation..................................................................................................................................... 34
1.2.3 Special terms..................................................................................................................................................34
Chapter 2
Introduction
2.1 Introduction...................................................................................................................................................................35
2.1.1 Core Overview............................................................................................................................................... 35
2.1.2 Memory Overview......................................................................................................................................... 36
2.1.3 Peripheral Overview...................................................................................................................................... 36
2.2 Application Examples...................................................................................................................................................36
2.3 Features.........................................................................................................................................................................37
2.3.1 MC56F826xx Product Family....................................................................................................................... 37
2.3.2 Block Diagram............................................................................................................................................... 38
2.3.3 56800EX 32-bit Digital Signal Controller (DSC) core..................................................................................39
2.3.4 Operation Parameters.....................................................................................................................................40
2.3.5 Packages.........................................................................................................................................................41
2.3.6 On-Chip Memory and Memory Protection....................................................................................................41
2.3.7 Peripherals......................................................................................................................................................41
2.3.7.1 System Modules...........................................................................................................................41
2.3.7.2 General Purpose I/O (GPIO)........................................................................................................43
2.3.7.3 Timers and PWM modules.......................................................................................................... 43
2.3.7.4 Clock Modules............................................................................................................................. 45
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2.3.7.5 Analog Modules...........................................................................................................................46
2.3.7.6 Communication Interfaces........................................................................................................... 47
2.3.7.7 Power Management......................................................................................................................47
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................49
3.2 Core modules................................................................................................................................................................ 49
3.2.1 Digital Signal Controller (DSC) Core Configuration.................................................................................... 49
3.3 System modules............................................................................................................................................................ 50
3.3.1 System Integration Module (SIM) Configuration..........................................................................................50
3.3.2 MCM Configuration...................................................................................................................................... 51
3.3.3 Inter-Peripheral Crossbar Switch (XBAR) and AND/OR/INVERT (AOI) Configuration........................... 52
3.3.3.1 Number of inputs and outputs......................................................................................................52
3.3.3.2 XBARA and XBARB Inputs....................................................................................................... 52
3.3.3.3 XBAR Interconnections...............................................................................................................53
3.3.3.4 XBARA Outputs..........................................................................................................................54
3.3.3.5 AOI module register write protection.......................................................................................... 55
3.3.4 Interrupt Controller (INTC) Configuration....................................................................................................56
3.3.4.1 Reset/Interrupt Vector Table........................................................................................................56
3.3.5 DMA Controller Configuration..................................................................................................................... 64
3.3.5.1 DMA channel assignments.......................................................................................................... 64
3.3.6 Power Management Controller (PMC) Configuration...................................................................................65
3.4 Clock Modules..............................................................................................................................................................66
3.4.1 On-Chip Clock Synthesis (OCCS) Configuration......................................................................................... 66
3.5 Memories and Memory Interfaces................................................................................................................................67
3.5.1 Flash Memory Controller (FMC) Configuration........................................................................................... 67
3.5.2 Flash Memory Configuration.........................................................................................................................68
3.5.2.1 FTFL_FOPT Register.................................................................................................................. 69
3.6 Security and Integrity....................................................................................................................................................69
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3.6.1 Windowed Computer Operating Properly (WCOP) Module Configuration................................................. 69
3.6.1.1 WCOP low power clocks.............................................................................................................69
3.6.2 External Watchdog Monitor (EWM) Configuration......................................................................................70
3.6.2.1 EWM low power clocks...............................................................................................................70
3.6.2.2 EWM_OUT pin state in Low Power Modes................................................................................71
3.6.2.3 EWM_IN signal........................................................................................................................... 71
3.6.3 Cyclic Redundancy Check (CRC) Configuration..........................................................................................71
3.7 Analog...........................................................................................................................................................................72
3.7.1 Cyclic Analog-to-Digital Converter (ADC) Configuration...........................................................................72
3.7.1.1 Cyclic ADC Instantiation.............................................................................................................73
3.7.1.2 Cyclic ADC SYNC Signal Connections......................................................................................73
3.7.1.3 Cyclic ADC and PWM Connections........................................................................................... 73
3.7.2 Comparator (CMP) Configuration.................................................................................................................73
3.7.2.1 Comparator Channel Assignments...............................................................................................74
3.7.2.2 CMP voltage references...............................................................................................................75
3.8 Timers and PWM..........................................................................................................................................................75
3.8.1 PWM Configuration.......................................................................................................................................75
3.8.2 PIT Configuration.......................................................................................................................................... 76
3.8.2.1 PIT instances................................................................................................................................77
3.8.2.2 PIT low power clocks.................................................................................................................. 77
3.8.2.3 PIT master/slave selection........................................................................................................... 77
3.8.3 TMR Configuration........................................................................................................................................77
3.8.3.1 TMR clock source multiplier option............................................................................................78
3.9 Communication interfaces............................................................................................................................................ 78
3.9.1 SCI Configuration..........................................................................................................................................78
3.10 Human-machine interfaces (HMI)................................................................................................................................79
3.10.1 GPIO Configuration.......................................................................................................................................79
3.10.1.1 GPIO Port D[4:0] configuration.................................................................................................. 80
3.10.1.2 GPIO unbonded pads................................................................................................................... 81
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Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................83
4.2 Program/Data Memory Maps....................................................................................................................................... 83
4.3 Core and System Peripheral Memory Map...................................................................................................................84
4.4 Slave Peripheral Memory Map..................................................................................................................................... 85
Chapter 5
Clock Distribution
5.1 Overview.......................................................................................................................................................................87
5.2 Features.........................................................................................................................................................................87
5.3 Clock definitions...........................................................................................................................................................88
5.4 Dual speed clock modes................................................................................................................................................88
5.4.1 Sequence involving Run mode switching......................................................................................................88
5.5 System clock source configuration............................................................................................................................... 89
5.6 Module clocks...............................................................................................................................................................90
Chapter 6
Reset and Boot
6.1 Reset Configuration...................................................................................................................................................... 93
6.2 System Boot..................................................................................................................................................................94
6.2.1 FOPT boot options.........................................................................................................................................94
6.2.2 Boot Procedure for Operation........................................................................................................................95
6.2.3 Boot sequence................................................................................................................................................ 95
6.2.4 Boot Procedure for Debug Operation............................................................................................................ 96
Chapter 7
Power Management
7.1 Overview.......................................................................................................................................................................99
7.2 Architecture...................................................................................................................................................................99
7.3 External Supplies and Regulation.................................................................................................................................100
7.4 User Power Management Methods...............................................................................................................................100
7.5 Power Modes................................................................................................................................................................ 101
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7.6 Power mode transitions.................................................................................................................................................103
Chapter 8
Signal Multiplexing
8.1 Introduction...................................................................................................................................................................107
8.2 Signal Multiplexing Integration....................................................................................................................................107
8.3 Signal Multiplexing and Pin Assignments....................................................................................................................108
8.4 Pinout diagrams............................................................................................................................................................ 109
8.5 Module Signal Description Tables................................................................................................................................111
8.5.1 Analog............................................................................................................................................................111
8.5.2 Communication Interfaces............................................................................................................................. 113
8.5.3 PWM and Timers...........................................................................................................................................113
8.5.4 Systems Modules........................................................................................................................................... 113
8.5.5 Clock Modules............................................................................................................................................... 114
8.5.6 Human-Machine Interfaces (HMI)................................................................................................................ 114
8.5.7 Systems and Integrity Modules......................................................................................................................115
Chapter 9
Memory Resource Protection (MRP)
9.1 Overview.......................................................................................................................................................................117
9.2 Features.........................................................................................................................................................................118
9.3 Operation.......................................................................................................................................................................118
9.4 Programming Model Overview.................................................................................................................................... 122
9.5 Memory Resource Protection Restrictions................................................................................................................... 122
9.6 Base Address Setup.......................................................................................................................................................122
9.7 Programming Example................................................................................................................................................. 124
Chapter 10
Miscellaneous Control Module (MCM)
10.1 Introduction...................................................................................................................................................................125
10.1.1 Features.......................................................................................................................................................... 125
10.2 Memory Map/Register Descriptions.............................................................................................................................126
10.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)....................................................................127
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10.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)................................................................ 127
10.2.3 Core control register (MCM_CPCR).............................................................................................................128
10.2.4 Core fault address register (MCM_CFADR).................................................................................................130
10.2.5 Core fault attributes register (MCM_CFATR).............................................................................................. 130
10.2.6 Core fault location register (MCM_CFLOC)................................................................................................ 131
10.2.7 Core fault interrupt enable register (MCM_CFIER)......................................................................................132
10.2.8 MCM interrupt status register (MCM_CFISR)............................................................................................. 132
10.2.9 Core fault data register (MCM_CFDTR).......................................................................................................133
10.2.10 Resource Protection Control Register (MCM_RPCR).................................................................................. 133
10.2.11 User Flash Base Address Register (MCM_UFLASHBAR)..........................................................................135
10.2.12 User Program RAM Base Address Register (MCM_UPRAMBAR)............................................................ 135
10.2.13 Resource Protection Other Stack Pointer (MCM_SRPOSP).........................................................................136
10.2.14 Memory Protection Illegal PC (MCM_SRPIPC)...........................................................................................136
10.2.15 Resource Protection Misaligned PC (MCM_SRPMPC)............................................................................... 138
10.3 Functional Description..................................................................................................................................................139
10.3.1 Core Data Fault Recovery Registers..............................................................................................................139
Chapter 11
System Integration Module (SIM)
11.1 Introduction...................................................................................................................................................................141
11.1.1 Overview........................................................................................................................................................141
11.1.2 Features.......................................................................................................................................................... 141
11.1.3 Modes of Operation....................................................................................................................................... 142
11.2 Memory Map and Register Descriptions...................................................................................................................... 143
11.2.1 Control Register (SIM_CTRL)...................................................................................................................... 145
11.2.2 Reset Status Register (SIM_RSTAT)............................................................................................................ 147
11.2.3 Most Significant Half of JTAG ID (SIM_MSHID).......................................................................................148
11.2.4 Least Significant Half of JTAG ID (SIM_LSHID)....................................................................................... 149
11.2.5 Power Control Register (SIM_PWR)............................................................................................................ 149
11.2.6 Clock Output Select Register (SIM_CLKOUT)............................................................................................151
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11.2.7 Peripheral Clock Rate Register (SIM_PCR)..................................................................................................153
11.2.8 Peripheral Clock Enable Register 0 (SIM_PCE0)......................................................................................... 154
11.2.9 Peripheral Clock Enable Register 1 (SIM_PCE1)......................................................................................... 156
11.2.10 Peripheral Clock Enable Register 2 (SIM_PCE2)......................................................................................... 157
11.2.11 Peripheral Clock Enable Register 3 (SIM_PCE3)......................................................................................... 159
11.2.12 STOP Disable Register 0 (SIM_SD0)........................................................................................................... 160
11.2.13 Peripheral Clock STOP Disable Register 1 (SIM_SD1)............................................................................... 162
11.2.14 Peripheral Clock STOP Disable Register 2 (SIM_SD2)............................................................................... 163
11.2.15 Peripheral Clock STOP Disable Register 3 (SIM_SD3)............................................................................... 165
11.2.16 I/O Short Address Location Register (SIM_IOSAHI)...................................................................................167
11.2.17 I/O Short Address Location Register (SIM_IOSALO)..................................................................................168
11.2.18 Protection Register (SIM_PROT)..................................................................................................................169
11.2.19 GPIOA LSBs Peripheral Select Register (SIM_GPSAL)..............................................................................171
11.2.20 GPIOB LSBs Peripheral Select Register (SIM_GPSBL)..............................................................................172
11.2.21 GPIOC LSBs Peripheral Select Register (SIM_GPSCL)..............................................................................173
11.2.22 GPIOC MSBs Peripheral Select Register (SIM_GPSCH)............................................................................ 174
11.2.23 GPIOE LSBs Peripheral Select Register (SIM_GPSEL).............................................................................. 175
11.2.24 GPIOF LSBs Peripheral Select Register (SIM_GPSFL)...............................................................................176
11.2.25 GPIOF MSBs Peripheral Select Register (SIM_GPSFH)............................................................................. 177
11.2.26 Internal Peripheral Select Register (SIM_IPSn)............................................................................................ 178
11.2.27 Miscellaneous Register 0 (SIM_MISC0).......................................................................................................179
11.2.28 Peripheral Software Reset Register 0 (SIM_PSWR0)...................................................................................180
11.2.29 Peripheral Software Reset Register 1 (SIM_PSWR1)...................................................................................181
11.2.30 Peripheral Software Reset Register 2 (SIM_PSWR2)...................................................................................182
11.2.31 Peripheral Software Reset Register 3 (SIM_PSWR3)...................................................................................184
11.2.32 Power Mode Register (SIM_PWRMODE)....................................................................................................185
11.2.33 Non-Volatile Memory Option Register 2 (High) (SIM_NVMOPT2H)........................................................ 186
11.2.34 Non-Volatile Memory Option Register 2 (Low) (SIM_NVMOPT2L)......................................................... 186
11.2.35 Software Control Register (SIM_SCR0)....................................................................................................... 187
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11.2.36 Software Control Register 1 (SIM_SCR1).................................................................................................... 187
11.2.37 Software Control Register 2 (SIM_SCR2).................................................................................................... 188
11.2.38 Software Control Register 3 (SIM_SCR3).................................................................................................... 188
11.2.39 Software Control Register 4 (SIM_SCR4).................................................................................................... 188
11.2.40 Software Control Register (SIM_SCR5)....................................................................................................... 189
11.2.41 Software Control Register 5 (SIM_SCR6).................................................................................................... 189
11.2.42 Software Control Register 6 (SIM_SCR7).................................................................................................... 189
11.3 Functional Description..................................................................................................................................................190
11.3.1 Clock Generation Overview...........................................................................................................................190
11.3.2 Power-Down Modes Overview......................................................................................................................190
11.3.3 STOP and WAIT Mode Disable Function.....................................................................................................192
11.4 Resets............................................................................................................................................................................193
11.5 Clocks........................................................................................................................................................................... 193
11.6 Interrupts.......................................................................................................................................................................193
Chapter 12
Interrupt Controller (INTC)
12.1 Introduction...................................................................................................................................................................195
12.1.1 References......................................................................................................................................................195
12.1.2 Features.......................................................................................................................................................... 195
12.1.3 Modes of Operation....................................................................................................................................... 195
12.1.4 Block Diagram............................................................................................................................................... 196
12.2 Memory Map and Registers..........................................................................................................................................197
12.2.1 Interrupt Priority Register 0 (INTC_IPR0)....................................................................................................198
12.2.2 Interrupt Priority Register 1 (INTC_IPR1)....................................................................................................199
12.2.3 Interrupt Priority Register 2 (INTC_IPR2)....................................................................................................200
12.2.4 Interrupt Priority Register 3 (INTC_IPR3)....................................................................................................202
12.2.5 Interrupt Priority Register 4 (INTC_IPR4)....................................................................................................203
12.2.6 Interrupt Priority Register 5 (INTC_IPR5)....................................................................................................203
12.2.7 Interrupt Priority Register 8 (INTC_IPR8)....................................................................................................205
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12.2.8 Interrupt Priority Register 9 (INTC_IPR9)....................................................................................................206
12.2.9 Interrupt Priority Register 10 (INTC_IPR10)................................................................................................208
12.2.10 Interrupt Priority Register 11 (INTC_IPR11)................................................................................................209
12.2.11 Interrupt Priority Register 12 (INTC_IPR12)................................................................................................210
12.2.12 Vector Base Address Register (INTC_VBA)................................................................................................ 211
12.2.13 Fast Interrupt 0 Match Register (INTC_FIM0)............................................................................................. 212
12.2.14 Fast Interrupt 0 Vector Address Low Register (INTC_FIVAL0)..................................................................212
12.2.15 Fast Interrupt 0 Vector Address High Register (INTC_FIVAH0)................................................................ 213
12.2.16 Fast Interrupt 1 Match Register (INTC_FIM1)............................................................................................. 213
12.2.17 Fast Interrupt 1 Vector Address Low Register (INTC_FIVAL1)..................................................................214
12.2.18 Fast Interrupt 1 Vector Address High Register (INTC_FIVAH1)................................................................ 214
12.2.19 IRQ Pending Register 0 (INTC_IRQP0)....................................................................................................... 214
12.2.20 IRQ Pending Register 1 (INTC_IRQP1)....................................................................................................... 215
12.2.21 IRQ Pending Register 2 (INTC_IRQP2)....................................................................................................... 215
12.2.22 IRQ Pending Register 3 (INTC_IRQP3)....................................................................................................... 216
12.2.23 IRQ Pending Register 4 (INTC_IRQP4)....................................................................................................... 216
12.2.24 IRQ Pending Register 5 (INTC_IRQP5)....................................................................................................... 217
12.2.25 IRQ Pending Register 6 (INTC_IRQP6)....................................................................................................... 217
12.2.26 Control Register (INTC_CTRL)....................................................................................................................218
12.3 Functional Description..................................................................................................................................................219
12.3.1 Normal Interrupt Handling.............................................................................................................................219
12.3.2 Interrupt Nesting............................................................................................................................................ 219
12.3.3 Fast Interrupt Handling.................................................................................................................................. 220
12.4 Interrupts.......................................................................................................................................................................220
Chapter 13
DMA Controller
13.1 Introduction...................................................................................................................................................................221
13.1.1 Overview........................................................................................................................................................221
13.1.2 Features.......................................................................................................................................................... 223
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13.2 DMA Transfer Overview..............................................................................................................................................223
13.3 Memory Map/Register Definition.................................................................................................................................225
13.3.1 DMA Request Control Register (DMA_REQC)........................................................................................... 226
13.3.2
Source Address Register (DMA_SARn)....................................................................................................... 230
13.3.3
Destination Address Register (DMA_DARn)............................................................................................... 230
13.3.4
DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............................................................230
13.3.5
DMA Control Register (DMA_DCRn)..........................................................................................................233
13.4 Functional Description..................................................................................................................................................236
13.4.1 Transfer requests (Cycle-Steal and Continuous modes)................................................................................237
13.4.2 Channel initialization and startup.................................................................................................................. 237
13.4.2.1 Channel prioritization.................................................................................................................. 237
13.4.2.2 Programming the DMA Controller Module.................................................................................238
13.4.3 Dual-Address Data Transfer Mode................................................................................................................239
13.4.4 Advanced Data Transfer Controls: Auto-Alignment.....................................................................................240
13.4.5 Termination....................................................................................................................................................241
Chapter 14
Power Management Controller (PMC)
14.1 Introduction...................................................................................................................................................................243
14.1.1 Overview........................................................................................................................................................243
14.1.2 Features.......................................................................................................................................................... 243
14.1.3 Modes of Operation....................................................................................................................................... 244
14.1.4 Block Diagram............................................................................................................................................... 245
14.2 Memory Map and Register Descriptions...................................................................................................................... 246
14.2.1 Control Register (PMC_CTRL).....................................................................................................................247
14.2.2 Status Register (PMC_STS)...........................................................................................................................248
14.3 Functional Description..................................................................................................................................................250
14.4 Resets............................................................................................................................................................................251
14.5 Clocks........................................................................................................................................................................... 251
14.6 Interrupts.......................................................................................................................................................................252
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Chapter 15
Inter-Peripheral Crossbar Switch A (XBARA)
15.1 Introduction...................................................................................................................................................................253
15.1.1 Overview........................................................................................................................................................253
15.1.2 Features.......................................................................................................................................................... 253
15.1.3 Modes of Operation....................................................................................................................................... 254
15.1.4 Block Diagram............................................................................................................................................... 254
15.2 Signal Descriptions.......................................................................................................................................................255
15.2.1 XBAR_OUT[0:NUM_OUT-1] - MUX Outputs........................................................................................... 255
15.2.2 XBAR_IN[0:NUM_IN-1] - MUX Inputs......................................................................................................255
15.2.3 DMA_REQ[n] - DMA Request Output(s).....................................................................................................255
15.2.4 DMA_ACK[n] - DMA Acknowledge Input(s)..............................................................................................255
15.2.5 INT_REQ[n] - Interrupt Request Output(s)...................................................................................................256
15.3 Memory Map and Register Descriptions...................................................................................................................... 256
15.3.1 Crossbar A Select Register 0 (XBARA_SEL0).............................................................................................257
15.3.2 Crossbar A Select Register 1 (XBARA_SEL1).............................................................................................258
15.3.3 Crossbar A Select Register 2 (XBARA_SEL2).............................................................................................258
15.3.4 Crossbar A Select Register 3 (XBARA_SEL3).............................................................................................259
15.3.5 Crossbar A Select Register 4 (XBARA_SEL4).............................................................................................259
15.3.6 Crossbar A Select Register 5 (XBARA_SEL5).............................................................................................260
15.3.7 Crossbar A Select Register 6 (XBARA_SEL6).............................................................................................260
15.3.8 Crossbar A Select Register 7 (XBARA_SEL7).............................................................................................261
15.3.9 Crossbar A Select Register 8 (XBARA_SEL8).............................................................................................261
15.3.10 Crossbar A Select Register 9 (XBARA_SEL9).............................................................................................262
15.3.11 Crossbar A Select Register 10 (XBARA_SEL10).........................................................................................262
15.3.12 Crossbar A Select Register 11 (XBARA_SEL11).........................................................................................263
15.3.13 Crossbar A Select Register 12 (XBARA_SEL12).........................................................................................263
15.3.14 Crossbar A Select Register 13 (XBARA_SEL13).........................................................................................264
15.3.15 Crossbar A Select Register 14 (XBARA_SEL14).........................................................................................264
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15.3.16 Crossbar A Select Register 15 (XBARA_SEL15).........................................................................................265
15.3.17 Crossbar A Select Register 16 (XBARA_SEL16).........................................................................................265
15.3.18 Crossbar A Select Register 17 (XBARA_SEL17).........................................................................................266
15.3.19 Crossbar A Select Register 18 (XBARA_SEL18).........................................................................................266
15.3.20 Crossbar A Select Register 19 (XBARA_SEL19).........................................................................................267
15.3.21 Crossbar A Select Register 20 (XBARA_SEL20).........................................................................................267
15.3.22 Crossbar A Control Register 0 (XBARA_CTRL0)....................................................................................... 268
15.3.23 Crossbar A Control Register 1 (XBARA_CTRL1)....................................................................................... 270
15.4 Functional Description..................................................................................................................................................272
15.4.1 General...........................................................................................................................................................272
15.4.2 Functional Mode............................................................................................................................................ 272
15.5 Resets............................................................................................................................................................................273
15.6 Clocks........................................................................................................................................................................... 273
15.7 Interrupts and DMA Requests...................................................................................................................................... 273
Chapter 16
Inter-Peripheral Crossbar Switch B (XBARB): AOI Input
16.1 Introduction...................................................................................................................................................................275
16.2 Memory Map and Register Descriptions...................................................................................................................... 275
Chapter 17
Crossbar AND/OR/INVERT (AOI) Module
17.1 Introduction...................................................................................................................................................................277
17.1.1 Overview........................................................................................................................................................277
17.1.2 Features.......................................................................................................................................................... 279
17.1.3 Modes of Operation....................................................................................................................................... 279
17.2 External Signal Description.......................................................................................................................................... 279
17.3 Memory Map and Register Descriptions...................................................................................................................... 279
17.3.1
Boolean Function Term 0 and 1 Configuration Register for EVENTn (AOI_BFCRT01n)..........................281
17.3.2
Boolean Function Term 2 and 3 Configuration Register for EVENTn (AOI_BFCRT23n)..........................282
17.4 Functional Description..................................................................................................................................................284
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17.4.1 Configuration Examples for the Boolean Function Evaluation.....................................................................285
17.4.2 AOI Timing Between Inputs and Outputs..................................................................................................... 286
Chapter 18
On-Chip Clock Synthesis (OCCS)
18.1 Introduction...................................................................................................................................................................289
18.1.1 Overview........................................................................................................................................................289
18.1.2 Features.......................................................................................................................................................... 289
18.2 Modes of Operation...................................................................................................................................................... 290
18.2.1 Internal Clock Sources...................................................................................................................................291
18.2.2 Loop Controlled Pierce Crystal Oscillator.....................................................................................................291
18.2.3 External Clock Source - Crystal Oscillator Bypass Option........................................................................... 292
18.2.4 External Clock Source - CLKIN....................................................................................................................292
18.3 Block Diagram..............................................................................................................................................................294
18.4 Pin Description..............................................................................................................................................................295
18.4.1 External Clock Reference.............................................................................................................................. 295
18.4.2 Oscillator IO (XTAL, EXTAL)..................................................................................................................... 295
18.4.3 CLKO - Output Pins...................................................................................................................................... 295
18.5 Memory Map and Register Descriptions...................................................................................................................... 296
18.5.1 PLL Control Register (OCCS_CTRL)...........................................................................................................296
18.5.2 PLL Divide-By Register (OCCS_DIVBY)....................................................................................................298
18.5.3 OCCS Status Register (OCCS_STAT)..........................................................................................................299
18.5.4 Oscillator Control Register 1 (OCCS_OSCTL1)...........................................................................................301
18.5.5 Oscillator Control Register 2 (OCCS_OSCTL2)...........................................................................................303
18.5.6 External Clock Check Reference (OCCS_CLKCHKR)................................................................................304
18.5.7 External Clock Check Target (OCCS_CLKCHKT)......................................................................................305
18.5.8 Protection Register (OCCS_PROT)...............................................................................................................305
18.6 Functional Description..................................................................................................................................................306
18.7 Relaxation Oscillators...................................................................................................................................................310
18.7.1 Trimming Frequency on the Internal 8 MHz Relaxation Oscillator..............................................................310
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18.7.2 Trimming Frequency on the Internal 200 kHz Relaxation Oscillator........................................................... 310
18.8 External Reference........................................................................................................................................................311
18.9 Crystal Oscillator.......................................................................................................................................................... 311
18.9.1 Switching Clock Sources............................................................................................................................... 311
18.10 Phase Locked Loop.......................................................................................................................................................313
18.10.1 PLL Recommended Range of Operation.......................................................................................................313
18.10.2 PLL Lock Time Specification........................................................................................................................313
18.10.2.1 Lock Time Definition...................................................................................................................313
18.10.2.2 Parametric Influences on Reaction Time.....................................................................................313
18.11 PLL Frequency Lock Detector Block...........................................................................................................................314
18.12 Loss of Reference Clock Detector................................................................................................................................ 314
18.13 Resets............................................................................................................................................................................315
18.14 Clocks........................................................................................................................................................................... 315
18.15 Interrupts.......................................................................................................................................................................316
Chapter 19
Flash Memory Controller (FMC)
19.1 Introduction...................................................................................................................................................................317
19.1.1 Overview........................................................................................................................................................317
19.1.2 Features.......................................................................................................................................................... 317
19.2 Modes of operation....................................................................................................................................................... 318
19.3 External signal description............................................................................................................................................318
19.4 Memory map and register descriptions.........................................................................................................................318
19.4.1 Flash Access Protection Register (FMC_PFAPR).........................................................................................321
19.4.2 Flash Control Register (FMC_PFB0CR).......................................................................................................323
19.4.3
Cache Tag Storage (FMC_TAGVDW0Sn)................................................................................................... 326
19.4.4
Cache Tag Storage (FMC_TAGVDW1Sn)................................................................................................... 327
19.4.5
Cache Tag Storage (FMC_TAGVDW2Sn)................................................................................................... 328
19.4.6
Cache Tag Storage (FMC_TAGVDW3Sn)................................................................................................... 329
19.4.7
Cache Data Storage (FMC_DATAW0Sn).....................................................................................................329
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Section number Title Page
19.4.8
Cache Data Storage (FMC_DATAW1Sn).....................................................................................................330
19.4.9
Cache Data Storage (FMC_DATAW2Sn).....................................................................................................330
19.4.10
Cache Data Storage (FMC_DATAW3Sn).....................................................................................................331
19.5 Functional description...................................................................................................................................................331
Chapter 20
Flash Memory Module (FTFA)
20.1 Introduction...................................................................................................................................................................333
20.1.1 Features.......................................................................................................................................................... 334
20.1.1.1 Program Flash Memory Features.................................................................................................334
20.1.1.2 Other Flash Memory Module Features........................................................................................ 334
20.1.2 Block Diagram............................................................................................................................................... 334
20.1.3 Glossary......................................................................................................................................................... 335
20.2 External Signal Description.......................................................................................................................................... 336
20.3 Memory Map and Registers..........................................................................................................................................336
20.3.1 Flash Configuration Field Description...........................................................................................................336
20.3.2 Program Flash IFR Map.................................................................................................................................337
20.3.2.1 Program Once Field..................................................................................................................... 337
20.3.3 Register Descriptions..................................................................................................................................... 338
20.3.3.1 Flash Status Register (FTFA_FSTAT)........................................................................................ 339
20.3.3.2 Flash Configuration Register (FTFA_FCNFG)...........................................................................341
20.3.3.3 Flash Security Register (FTFA_FSEC)....................................................................................... 342
20.3.3.4 Flash Option Register (FTFA_FOPT)......................................................................................... 343
20.3.3.5
Flash Common Command Object Registers (FTFA_FCCOBn)................................................. 344
20.3.3.6
Program Flash Protection Registers (FTFA_FPROTn)...............................................................345
20.4 Functional Description..................................................................................................................................................347
20.4.1 Flash Protection..............................................................................................................................................347
20.4.2 Interrupts........................................................................................................................................................ 348
20.4.3 Flash Operation in Low-Power Modes.......................................................................................................... 348
20.4.3.1 Wait Mode....................................................................................................................................348
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20.4.3.2 Stop Mode....................................................................................................................................348
20.4.4 Flash Reads and Ignored Writes.................................................................................................................... 349
20.4.5 Read While Write (RWW).............................................................................................................................349
20.4.6 Flash Program and Erase................................................................................................................................349
20.4.7 Flash Command Operations...........................................................................................................................349
20.4.7.1 Command Write Sequence...........................................................................................................350
20.4.7.2 Flash Commands..........................................................................................................................352
20.4.8 Margin Read Commands............................................................................................................................... 353
20.4.9 Flash Command Description..........................................................................................................................354
20.4.9.1 Read 1s Section Command.......................................................................................................... 355
20.4.9.2 Program Check Command...........................................................................................................356
20.4.9.3 Read Resource Command............................................................................................................357
20.4.9.4 Program Longword Command.....................................................................................................358
20.4.9.5 Erase Flash Sector Command...................................................................................................... 359
20.4.9.6 Read 1s All Blocks Command.....................................................................................................362
20.4.9.7 Read Once Command.................................................................................................................. 363
20.4.9.8 Program Once Command.............................................................................................................364
20.4.9.9 Erase All Blocks Command.........................................................................................................365
20.4.9.10 Verify Backdoor Access Key Command.....................................................................................366
20.4.10 Security.......................................................................................................................................................... 367
20.4.10.1 Changing the Security State.........................................................................................................368
20.4.11 Reset Sequence.............................................................................................................................................. 369
Chapter 21
Windowed Computer Operating Properly (WCOP) Watchdog
21.1 Introduction...................................................................................................................................................................371
21.1.1 Features.......................................................................................................................................................... 371
21.1.2 Block Diagram............................................................................................................................................... 372
21.2 Memory Map and Registers..........................................................................................................................................373
21.2.1 COP Control Register (COP_CTRL).............................................................................................................373
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21.2.2 COP Timeout Register (COP_TOUT)...........................................................................................................375
21.2.3 COP Counter Register (COP_CNTR)............................................................................................................376
21.2.4 COP Interrupt Value Register (COP_INTVAL)............................................................................................376
21.2.5 COP Window Timeout Register (COP_WINDOW)..................................................................................... 377
21.3 Functional Description..................................................................................................................................................377
21.3.1 COP after Reset..............................................................................................................................................377
21.3.2 Wait Mode Operation.....................................................................................................................................378
21.3.3 Stop Mode Operation.....................................................................................................................................378
21.3.4 Debug Mode Operation..................................................................................................................................378
21.3.5 Loss of Reference Operation..........................................................................................................................378
21.4 Resets............................................................................................................................................................................379
21.5 Clocks........................................................................................................................................................................... 379
21.6 Interrupts.......................................................................................................................................................................379
Chapter 22
External Watchdog Monitor (EWM)
22.1 Introduction...................................................................................................................................................................381
22.1.1 Features.......................................................................................................................................................... 381
22.1.2 Modes of Operation....................................................................................................................................... 382
22.1.2.1 Stop Mode....................................................................................................................................382
22.1.2.2 Wait Mode....................................................................................................................................382
22.1.2.3 Debug Mode.................................................................................................................................383
22.1.3 Block Diagram............................................................................................................................................... 383
22.2 EWM Signal Descriptions............................................................................................................................................ 384
22.3 Memory Map/Register Definition.................................................................................................................................384
22.3.1 Control Register (EWM_CTRL)................................................................................................................... 384
22.3.2 Service Register (EWM_SERV)....................................................................................................................386
22.3.3 Compare Low Register (EWM_CMPL)........................................................................................................386
22.3.4 Compare High Register (EWM_CMPH).......................................................................................................387
22.3.5 Clock Control Register (EWM_CLKCTRL).................................................................................................387
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22.3.6 Clock Prescaler Register (EWM_CLKPRESCALER)..................................................................................388
22.4 Functional Description..................................................................................................................................................389
22.4.1 The EWM_out Signal.................................................................................................................................... 389
22.4.2 The EWM_in Signal...................................................................................................................................... 390
22.4.3 EWM Counter................................................................................................................................................390
22.4.4 EWM Compare Registers.............................................................................................................................. 391
22.4.5 EWM Refresh Mechanism.............................................................................................................................391
22.4.6 EWM Interrupt...............................................................................................................................................391
22.4.7 Selecting the EWM counter clock................................................................................................................. 392
22.4.8 Counter clock prescaler..................................................................................................................................392
Chapter 23
Cyclic Redundancy Check (CRC)
23.1 Introduction...................................................................................................................................................................393
23.1.1 Features ......................................................................................................................................................... 393
23.1.2 Modes of Operation....................................................................................................................................... 393
23.1.3 Block Diagram .............................................................................................................................................. 394
23.2 External Signal Description ......................................................................................................................................... 394
23.3 Memory Map and Registers..........................................................................................................................................395
23.3.1 CRC High Register (CRC_CRCH)................................................................................................................395
23.3.2 CRC Low Register (CRC_CRCL).................................................................................................................395
23.3.3 CRC Transpose Register (CRC_TRANSPOSE)........................................................................................... 396
23.4 Functional Description .................................................................................................................................................396
23.4.1 ITU-T (CCITT) Recommendations and Expected CRC Results...................................................................397
23.4.2 Transpose feature........................................................................................................................................... 398
23.5 Initialization Information .............................................................................................................................................398
Chapter 24
12-bit Cyclic Analog-to-Digital Converter
24.1 Introduction...................................................................................................................................................................401
24.1.1 Overview........................................................................................................................................................401
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