MC56F81xxx Reference Manual
Supports MC56F817xx and MC56F816xx
Document Number: MC56F81XXXRM
Rev. 1, 11/2020
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................53
1.1.1 Purpose...........................................................................................................................................................53
1.1.2 Audience........................................................................................................................................................ 53
1.2 Conventions.................................................................................................................................................................. 53
1.2.1 Numbering systems........................................................................................................................................53
1.2.2 Typographic notation..................................................................................................................................... 54
1.2.3 Special terms..................................................................................................................................................54
Chapter 2
Introduction
2.1 Target Applications.......................................................................................................................................................55
2.2 System Block Diagram................................................................................................................................................. 55
2.3 Product Family..............................................................................................................................................................57
Chapter 3
Memory Map
3.1 Introduction...................................................................................................................................................................59
3.2 Program/Data Memory Maps....................................................................................................................................... 59
3.3 Core and System Peripheral Memory Map...................................................................................................................60
3.4 Slave Peripheral Memory Map..................................................................................................................................... 61
Chapter 4
Clock Distribution
4.1 Overview.......................................................................................................................................................................65
4.2 Clock Distribution.........................................................................................................................................................66
4.3 Dual speed clock modes................................................................................................................................................67
4.3.1 Sequence involving Run mode switching......................................................................................................68
Chapter 5
ROM Bootloader
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5.1 Chip-specific Information.............................................................................................................................................69
5.1.1 Bootloader Peripheral Pinmux.......................................................................................................................69
5.1.2 Bootloader Memory Access...........................................................................................................................70
5.2 Introduction...................................................................................................................................................................70
5.3 Functional Description..................................................................................................................................................72
5.3.1 The Bootloader Configuration Area (BCA)...................................................................................................72
5.3.2 Start-up Process..............................................................................................................................................74
5.3.3 Bootloader Entry Point / API Tree.................................................................................................................76
5.3.4 Bootloader Protocol....................................................................................................................................... 77
5.3.4.1 Command with no data phase.................................................................................................... 78
5.3.4.2 Command with incoming data phase.........................................................................................78
5.3.4.3 Command with outgoing data phase..........................................................................................80
5.3.5 Bootloader Packet Types............................................................................................................................... 82
5.3.5.1 Ping packet.................................................................................................................................82
5.3.5.2 Ping Response Packet................................................................................................................ 83
5.3.5.3 Framing Packet.......................................................................................................................... 83
5.3.5.4 Command packet........................................................................................................................85
5.3.5.5 Data packet.................................................................................................................................87
5.3.5.6 Response packet.........................................................................................................................88
5.3.6 Bootloader Command API.............................................................................................................................90
5.3.6.1 Execute command......................................................................................................................90
5.3.6.2 Reset command..........................................................................................................................91
5.3.6.3 GetProperty command............................................................................................................... 92
5.3.6.4 FlashEraseAll command............................................................................................................ 93
5.3.6.5 FlashEraseRegion command......................................................................................................95
5.3.6.6 FlashEraseAllUnsecure command............................................................................................. 97
5.3.6.7 FlashProgramOnce command....................................................................................................98
5.3.6.8 FlashReadOnce command..........................................................................................................100
5.3.6.9 FlashReadResource command................................................................................................... 101
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5.3.6.10 FlashSecurityDisable command.................................................................................................103
5.3.6.11 WriteMemory command............................................................................................................105
5.3.6.12 ReadMemory command.............................................................................................................107
5.3.7 Bootloader Exit state......................................................................................................................................109
5.4 Peripherals Supported................................................................................................................................................... 109
5.4.1 LPI2C Peripheral............................................................................................................................................109
5.4.2 UART Peripheral........................................................................................................................................... 111
5.5 Get/SetProperty Command Properties..........................................................................................................................114
5.5.1 Property Definitions.......................................................................................................................................115
5.5.1.1 CurrentVersion Property............................................................................................................115
5.5.1.2 AvailablePeripherals Property................................................................................................... 116
5.5.1.3 AvailableCommands Property................................................................................................... 116
5.6 Verifying the application in flash using CRC-32......................................................................................................... 117
5.7 Bootloader Status Error Codes......................................................................................................................................118
5.8 ROM flash driver API...................................................................................................................................................119
5.8.1 Introduction....................................................................................................................................................119
5.8.2 Struct of FlashDriverInterface....................................................................................................................... 119
5.8.3 Details of structs.............................................................................................................................................120
5.8.4 Flash Driver APIs...........................................................................................................................................121
5.8.5 Integrate flash driver API to user project.......................................................................................................122
Chapter 6
Power Management
6.1 Introduction...................................................................................................................................................................125
6.2 Function Description.....................................................................................................................................................125
6.3 User Power Management Methods...............................................................................................................................126
6.4 Power Modes................................................................................................................................................................ 127
6.5 Power mode transitions.................................................................................................................................................130
Chapter 7
Memory Resource Protection (MRP)
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7.1 Overview.......................................................................................................................................................................135
7.2 Features.........................................................................................................................................................................136
7.3 Operation.......................................................................................................................................................................136
7.4 Programming Model Overview.................................................................................................................................... 140
7.5 Memory Resource Protection Restrictions................................................................................................................... 140
7.6 Base Address Setup.......................................................................................................................................................140
7.7 Programming Example................................................................................................................................................. 142
Chapter 8
Miscellaneous Control Module (MCM)
8.1 Introduction...................................................................................................................................................................145
8.1.1 Features.......................................................................................................................................................... 145
8.2 Memory Map/Register Descriptions.............................................................................................................................146
8.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)....................................................................147
8.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)................................................................ 147
8.2.3 Core control register (MCM_CPCR).............................................................................................................148
8.2.4 Core fault address register (MCM_CFADR).................................................................................................150
8.2.5 Core fault attributes register (MCM_CFATR).............................................................................................. 151
8.2.6 Core fault location register (MCM_CFLOC)................................................................................................ 152
8.2.7 Core fault interrupt enable register (MCM_CFIER)......................................................................................152
8.2.8 MCM interrupt status register (MCM_CFISR)............................................................................................. 153
8.2.9 Core fault data register (MCM_CFDTR).......................................................................................................154
8.2.10 Resource Protection Control Register (MCM_RPCR).................................................................................. 154
8.2.11 User Flash Base Address Register (MCM_UFLASHBAR)..........................................................................155
8.2.12 User Program RAM Base Address Register (MCM_UPRAMBAR)............................................................ 156
8.2.13 User Boot ROM Base Address Register (MCM_UBROMBAR)..................................................................156
8.2.14 Resource Protection Other Stack Pointer (MCM_SRPOSP).........................................................................157
8.2.15 Memory Protection Illegal PC (MCM_SRPIPC)...........................................................................................157
8.2.16 Resource Protection Misaligned PC (MCM_SRPMPC)............................................................................... 159
8.3 Functional Description..................................................................................................................................................160
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8.3.1 Core Data Fault Recovery Registers..............................................................................................................160
Chapter 9
System Integration Module (SIM)
9.1 Introduction...................................................................................................................................................................161
9.1.1 Overview........................................................................................................................................................161
9.1.2 Features.......................................................................................................................................................... 161
9.1.3 Modes of Operation....................................................................................................................................... 162
9.2 Memory Map and Register Descriptions...................................................................................................................... 163
9.2.1 Control Register (SIM_CTRL)...................................................................................................................... 165
9.2.2 Reset Status Register (SIM_RSTAT)............................................................................................................ 167
9.2.3 Most Significant Half of JTAG ID (SIM_MSHID).......................................................................................168
9.2.4 Least Significant Half of JTAG ID (SIM_LSHID)....................................................................................... 169
9.2.5 Power Control Register (SIM_PWR)............................................................................................................ 170
9.2.6 Clock Output Select Register (SIM_CLKOUT)............................................................................................172
9.2.7 Peripheral Clock Rate Register (SIM_PCR)..................................................................................................173
9.2.8 Peripheral Clock Enable Register 0 (SIM_PCE0)......................................................................................... 175
9.2.9 Peripheral Clock Enable Register 1 (SIM_PCE1)......................................................................................... 177
9.2.10 Peripheral Clock Enable Register 2 (SIM_PCE2)......................................................................................... 178
9.2.11 Peripheral Clock Enable Register 3 (SIM_PCE3)......................................................................................... 180
9.2.12 Peripheral Clock STOP Disable Register 0 (SIM_SD0)............................................................................... 181
9.2.13 Peripheral Clock STOP Disable Register 1 (SIM_SD1)............................................................................... 183
9.2.14 Peripheral Clock STOP Disable Register 2 (SIM_SD2)............................................................................... 185
9.2.15 Peripheral Clock STOP Disable Register 3 (SIM_SD3)............................................................................... 187
9.2.16 I/O Short Address Location Register (SIM_IOSAHI)...................................................................................189
9.2.17 I/O Short Address Location Register (SIM_IOSALO)..................................................................................190
9.2.18 Protection Register (SIM_PROT)..................................................................................................................191
9.2.19 GPIOA LSBs Peripheral Select Register (SIM_GPSAL)..............................................................................193
9.2.20 GPIOB LSBs Peripheral Select Register (SIM_GPSBL)..............................................................................194
9.2.21 GPIOC LSBs Peripheral Select Register (SIM_GPSCL)..............................................................................195
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9.2.22 GPIOC MSBs Peripheral Select Register (SIM_GPSCH)............................................................................ 196
9.2.23 GPIOE LSBs Peripheral Select Register (SIM_GPSEL).............................................................................. 197
9.2.24 GPIOF LSBs Peripheral Select Register (SIM_GPSFL)...............................................................................199
9.2.25 GPIOF MSBs Peripheral Select Register (SIM_GPSFH)............................................................................. 200
9.2.26 Internal Peripheral Select Register 0 (SIM_IPS0)......................................................................................... 200
9.2.27 Miscellaneous Register 0 (SIM_MISC0).......................................................................................................202
9.2.28 Peripheral Software Reset Register 0 (SIM_PSWR0)...................................................................................204
9.2.29 Peripheral Software Reset Register 1 (SIM_PSWR1)...................................................................................205
9.2.30 Peripheral Software Reset Register 2 (SIM_PSWR2)...................................................................................206
9.2.31 Peripheral Software Reset Register 3 (SIM_PSWR3)...................................................................................208
9.2.32 Power Mode Register (SIM_PWRMODE)....................................................................................................209
9.2.33 Software Control Register (SIM_SCR0)....................................................................................................... 210
9.2.34 Software Control Register (SIM_SCR1)....................................................................................................... 210
9.2.35 Software Control Register (SIM_SCR2)....................................................................................................... 211
9.2.36 Software Control Register (SIM_SCR3)....................................................................................................... 211
9.2.37 Software Control Register (SIM_SCR4)....................................................................................................... 211
9.2.38 Software Control Register (SIM_SCR5)....................................................................................................... 212
9.2.39 Software Control Register (SIM_SCR6)....................................................................................................... 212
9.2.40 Software Control Register (SIM_SCR7)....................................................................................................... 212
9.2.41 ADC and TMR Select Register (SIM_ADC_TMR_SEL).............................................................................213
9.2.42 Boot Mode Override Register (SIM_BOOT_MODE_OVERRIDE)............................................................ 214
9.3 Functional Description..................................................................................................................................................214
9.3.1 Clock Generation Overview...........................................................................................................................214
9.3.2 Power-Down Modes Overview......................................................................................................................215
9.3.3 STOP and WAIT Mode Disable Function.....................................................................................................217
9.4 Resets............................................................................................................................................................................218
9.5 Clocks........................................................................................................................................................................... 218
9.6 Interrupts.......................................................................................................................................................................218
Chapter 10
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Interrupt Controller (INTC)
10.1 Chip-specific information for this module....................................................................................................................219
10.1.1 Reset/Interrupt Vector Table..........................................................................................................................219
10.2 Introduction...................................................................................................................................................................227
10.2.1 References......................................................................................................................................................227
10.2.2 Features.......................................................................................................................................................... 227
10.2.3 Modes of Operation....................................................................................................................................... 228
10.2.4 Block Diagram............................................................................................................................................... 228
10.3 Memory Map and Registers..........................................................................................................................................229
10.3.1 Interrupt Priority Register 0 (INTC_IPR0)....................................................................................................230
10.3.2 Interrupt Priority Register 1 (INTC_IPR1)....................................................................................................232
10.3.3 Interrupt Priority Register 2 (INTC_IPR2)....................................................................................................233
10.3.4 Interrupt Priority Register 3 (INTC_IPR3)....................................................................................................234
10.3.5 Interrupt Priority Register 4 (INTC_IPR4)....................................................................................................235
10.3.6 Interrupt Priority Register 5 (INTC_IPR5)....................................................................................................236
10.3.7 Interrupt Priority Register 6 (INTC_IPR6)....................................................................................................238
10.3.8 Interrupt Priority Register 8 (INTC_IPR8)....................................................................................................239
10.3.9 Interrupt Priority Register 9 (INTC_IPR9)....................................................................................................240
10.3.10 Interrupt Priority Register 10 (INTC_IPR10)................................................................................................241
10.3.11 Interrupt Priority Register 11 (INTC_IPR11)................................................................................................243
10.3.12 Interrupt Priority Register 12 (INTC_IPR12)................................................................................................244
10.3.13 Vector Base Address Register (INTC_VBA)................................................................................................ 246
10.3.14 Fast Interrupt 0 Match Register (INTC_FIM0)............................................................................................. 246
10.3.15 Fast Interrupt 0 Vector Address Low Register (INTC_FIVAL0)..................................................................247
10.3.16 Fast Interrupt 0 Vector Address High Register (INTC_FIVAH0)................................................................ 247
10.3.17 Fast Interrupt 1 Match Register (INTC_FIM1)............................................................................................. 247
10.3.18 Fast Interrupt 1 Vector Address Low Register (INTC_FIVAL1)..................................................................248
10.3.19 Fast Interrupt 1 Vector Address High Register (INTC_FIVAH1)................................................................ 248
10.3.20 IRQ Pending Register 0 (INTC_IRQP0)....................................................................................................... 249
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10.3.21 IRQ Pending Register 1 (INTC_IRQP1)....................................................................................................... 249
10.3.22 IRQ Pending Register 2 (INTC_IRQP2)....................................................................................................... 250
10.3.23 IRQ Pending Register 3 (INTC_IRQP3)....................................................................................................... 250
10.3.24 IRQ Pending Register 4 (INTC_IRQP4)....................................................................................................... 251
10.3.25 IRQ Pending Register 5 (INTC_IRQP5)....................................................................................................... 251
10.3.26 IRQ Pending Register 6 (INTC_IRQP6)....................................................................................................... 252
10.3.27 Control Register (INTC_CTRL)....................................................................................................................252
10.4 Functional Description..................................................................................................................................................253
10.4.1 Normal Interrupt Handling.............................................................................................................................253
10.4.2 Interrupt Nesting............................................................................................................................................ 253
10.4.3 Fast Interrupt Handling.................................................................................................................................. 254
10.5 Interrupts.......................................................................................................................................................................255
Chapter 11
Enhanced Direct Memory Access (eDMA)
11.1 Introduction...................................................................................................................................................................257
11.1.1 eDMA system block diagram........................................................................................................................ 257
11.1.2 Block parts..................................................................................................................................................... 258
11.1.3 Features.......................................................................................................................................................... 259
11.2 Modes of operation....................................................................................................................................................... 260
11.3 Memory map/register definition................................................................................................................................... 261
11.3.1 TCD memory................................................................................................................................................. 261
11.3.2 TCD initialization.......................................................................................................................................... 261
11.3.3 TCD structure.................................................................................................................................................261
11.3.4 Reserved memory and bit fields.....................................................................................................................262
11.3.5 DMA register descriptions.............................................................................................................................262
11.3.5.1 DMA Memory map....................................................................................................................262
11.3.5.2 Control Register (CR)................................................................................................................ 264
11.3.5.3 Error Status Register (ES)..........................................................................................................267
11.3.5.4 Enable Request Register (ERQ).................................................................................................269
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11.3.5.5 Enable Error Interrupt Register (EEI)........................................................................................270
11.3.5.6 Clear Enable Error Interrupt Register (CEEI)............................................................................271
11.3.5.7 Set Enable Error Interrupt Register (SEEI)................................................................................273
11.3.5.8 Clear Enable Request Register (CERQ).................................................................................... 274
11.3.5.9 Set Enable Request Register (SERQ)........................................................................................ 275
11.3.5.10 Clear DONE Status Bit Register (CDNE)................................................................................. 276
11.3.5.11 Set START Bit Register (SSRT)............................................................................................... 277
11.3.5.12 Clear Error Register (CERR)..................................................................................................... 279
11.3.5.13 Clear Interrupt Request Register (CINT)...................................................................................280
11.3.5.14 Interrupt Request Register (INT)............................................................................................... 281
11.3.5.15 Error Register (ERR)................................................................................................................. 282
11.3.5.16 Hardware Request Status Register (HRS)................................................................................. 284
11.3.5.17 Enable Asynchronous Request in Stop Register (EARS)..........................................................285
11.3.5.18 Channel Priority Register (DCHPRI3 - DCHPRI0).................................................................. 287
11.3.5.19 TCD Source Address (TCD0_SADDR - TCD3_SADDR)....................................................... 288
11.3.5.20 TCD Signed Source Address Offset (TCD0_SOFF - TCD3_SOFF)........................................ 289
11.3.5.21 TCD Transfer Attributes (TCD0_ATTR - TCD3_ATTR)........................................................ 289
11.3.5.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(TCD0_NBYTES_MLOFFNO - TCD3_NBYTES_MLOFFNO)............................................ 290
11.3.5.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD0_NBY
TES_MLOFFYES - TCD3_NBYTES_MLOFFYES)...............................................................292
11.3.5.24 TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0_NBYTES_MLNO -
TCD3_NBYTES_MLNO).........................................................................................................293
11.3.5.25 TCD Last Source Address Adjustment (TCD0_SLAST - TCD3_SLAST).............................. 295
11.3.5.26 TCD Destination Address (TCD0_DADDR - TCD3_DADDR)...............................................296
11.3.5.27 TCD Signed Destination Address Offset (TCD0_DOFF - TCD3_DOFF)................................296
11.3.5.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0_
CITER_ELINKNO - TCD3_CITER_ELINKNO).................................................................... 297
11.3.5.29 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0_CIT
ER_ELINKYES - TCD3_CITER_ELINKYES)....................................................................... 298
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11.3.5.30 TCD Last Destination Address Adjustment/Scatter Gather Address (TCD0_DLASTSGA -
TCD3_DLASTSGA)................................................................................................................. 300
11.3.5.31 TCD Control and Status (TCD0_CSR - TCD3_CSR)...............................................................301
11.3.5.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0_
BITER_ELINKYES - TCD3_BITER_ELINKYES).................................................................303
11.3.5.33 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0_
BITER_ELINKNO - TCD3_BITER_ELINKNO).................................................................... 304
11.4 Functional description...................................................................................................................................................306
11.4.1 eDMA basic data flow................................................................................................................................... 306
11.4.2 Fault reporting and handling..........................................................................................................................309
11.4.3 Channel preemption....................................................................................................................................... 312
11.5 Initialization/application information........................................................................................................................... 312
11.5.1 eDMA initialization....................................................................................................................................... 312
11.5.2 Programming errors....................................................................................................................................... 314
11.5.3 Arbitration mode considerations....................................................................................................................315
11.5.3.1 Fixed channel arbitration........................................................................................................... 315
11.5.3.2 Round-robin channel arbitration................................................................................................ 315
11.5.4 Performing DMA transfers............................................................................................................................ 315
11.5.4.1 Single request.............................................................................................................................315
11.5.4.2 Multiple requests........................................................................................................................317
11.5.4.3 Using the modulo feature...........................................................................................................319
11.5.5 Monitoring transfer descriptor status............................................................................................................. 319
11.5.5.1 Testing for minor loop completion............................................................................................ 319
11.5.5.2 Reading the transfer descriptors of active channels...................................................................320
11.5.5.3 Checking channel preemption status..........................................................................................321
11.5.6 Channel Linking.............................................................................................................................................321
11.5.7 Dynamic programming.................................................................................................................................. 322
11.5.7.1 Dynamically changing the channel priority...............................................................................322
11.5.7.2 Dynamic channel linking........................................................................................................... 323
11.5.7.3 Dynamic scatter/gather.............................................................................................................. 323
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11.5.8 Suspend/resume a DMA channel with active hardware service requests......................................................326
11.5.8.1 Suspend an active DMA channel...............................................................................................326
11.5.8.2 Resume a DMA channel............................................................................................................ 326
Chapter 12
DMA Channel Multiplexer (DMAMUX)
12.1 Chip-specific information for this module....................................................................................................................329
12.1.1 eDMA.............................................................................................................................................................329
12.2 Introduction...................................................................................................................................................................331
12.2.1 Overview........................................................................................................................................................332
12.2.2 Features.......................................................................................................................................................... 332
12.2.3 Modes of operation........................................................................................................................................ 333
12.3 Memory map/register definition................................................................................................................................... 333
12.3.1 DMAMUX register descriptions....................................................................................................................333
12.3.1.1 DMAMUX memory map...........................................................................................................333
12.3.1.2 Channel Configuration register (CHCFG0 - CHCFG3)............................................................ 333
12.4 Functional description...................................................................................................................................................335
12.4.1 Always-enabled DMA sources...................................................................................................................... 335
12.4.2 DMA sources with cancel_rewind capability................................................................................................ 336
12.5 Initialization/application information........................................................................................................................... 336
12.5.1 Reset...............................................................................................................................................................337
12.5.2 Enabling and configuring sources..................................................................................................................337
Chapter 13
Power Management Controller (PMC)
13.1 Introduction...................................................................................................................................................................339
13.1.1 Overview........................................................................................................................................................339
13.1.2 Features.......................................................................................................................................................... 339
13.1.3 Modes of Operation....................................................................................................................................... 340
13.1.4 Block Diagram............................................................................................................................................... 340
13.2 Memory Map and Register Descriptions...................................................................................................................... 341
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13.2.1 Control Register (PMC_CTRL).....................................................................................................................342
13.2.2 Status Register (PMC_STS)...........................................................................................................................343
13.3 Functional Description..................................................................................................................................................345
13.4 Resets............................................................................................................................................................................346
13.5 Clocks........................................................................................................................................................................... 346
13.6 Interrupts.......................................................................................................................................................................347
Chapter 14
Event Generator (EVTG)
14.1 About this module.........................................................................................................................................................349
14.1.1 Introduction....................................................................................................................................................349
14.1.2 Features.......................................................................................................................................................... 349
14.1.3 Block diagram................................................................................................................................................350
14.2 Signals...........................................................................................................................................................................350
14.3 Memory Map and register definition............................................................................................................................ 351
14.3.1 EVTG register descriptions............................................................................................................................351
14.3.1.1 EVTG memory map...................................................................................................................351
14.3.1.2 AOI0 Boolean Function Term 0 and 1 Configuration Register (EVTG0_AOI0_BFT01 -
EVTG3_AOI0_BFT01)............................................................................................................. 352
14.3.1.3 AOI0 Boolean Function Term 2 and 3 Configuration Register (EVTG0_AOI0_BFT23 -
EVTG3_AOI0_BFT23)............................................................................................................. 354
14.3.1.4 AOI1 Boolean Function Term 0 and 1 Configuration Register (EVTG0_AOI1_BFT01 -
EVTG3_AOI1_BFT01)............................................................................................................. 356
14.3.1.5 AOI1 Boolean Function Term 2 and 3 Configuration Register (EVTG0_AOI1_BFT23 -
EVTG3_AOI1_BFT23)............................................................................................................. 358
14.3.1.6 Control/Status Register (EVTG0_CTRL - EVTG3_CTRL)..................................................... 360
14.3.1.7 AOI0 Input Filter Register (EVTG0_AOI0_FILT - EVTG3_AOI0_FILT)..............................362
14.3.1.8 AOI1 Input Filter Register (EVTG0_AOI1_FILT - EVTG3_AOI1_FILT)..............................362
14.4 Functional description...................................................................................................................................................363
14.4.1 Configuration Examples for AOI Combinational function............................................................................363
14.4.2 Input Sync and Filter Logic Description .......................................................................................................365
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14.4.3 Flip-Flop mode configuration........................................................................................................................ 366
14.4.3.1 Bypass Mode..............................................................................................................................366
14.4.3.2 RS Trigger Mode....................................................................................................................... 367
14.4.3.3 T-FF Mode................................................................................................................................. 368
14.4.3.4 D-FF Mode.................................................................................................................................369
14.4.3.5 JK-FF Mode............................................................................................................................... 370
14.4.3.6 Latch Mode................................................................................................................................ 371
14.4.4 EVTG Timing Between Inputs and Outputs..................................................................................................372
14.5 Application information................................................................................................................................................373
Chapter 15
Inter-Peripheral Crossbar Switch (XBAR)
15.1 Chip-specific information for this module....................................................................................................................375
15.1.1 Number of inputs and outputs........................................................................................................................375
15.1.2 XBARA Inputs...............................................................................................................................................376
15.1.3 XBARA Outputs............................................................................................................................................378
15.2 Overview.......................................................................................................................................................................380
15.2.1 Block Diagram............................................................................................................................................... 380
15.2.2 Features.......................................................................................................................................................... 381
15.2.3 Modes of Operation....................................................................................................................................... 381
15.3 Functional Description..................................................................................................................................................382
15.3.1 General...........................................................................................................................................................382
15.3.2 Functional Mode............................................................................................................................................ 382
15.3.3 Clocks.............................................................................................................................................................382
15.3.4 Resets............................................................................................................................................................. 383
15.3.5 Interrupts and DMA Requests........................................................................................................................383
15.4 External Signals............................................................................................................................................................ 383
15.4.1 XBAR_OUT[0:NUM_OUT-1] - MUX Outputs........................................................................................... 384
15.4.2 XBAR_IN[0:NUM_IN-1] - MUX Inputs......................................................................................................384
15.4.3 DMA_REQ[n] - DMA Request Output(s).....................................................................................................384
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15.4.4 DMA_ACK[n] - DMA Acknowledge Input(s)..............................................................................................384
15.4.5 INT_REQ[n] - Interrupt Request Output(s)...................................................................................................384
15.5 Memory Map and Register Descriptions...................................................................................................................... 384
15.5.1 Crossbar A Select Register 0 (XBARA_SEL0).............................................................................................386
15.5.2 Crossbar A Select Register 1 (XBARA_SEL1).............................................................................................386
15.5.3 Crossbar A Select Register 2 (XBARA_SEL2).............................................................................................387
15.5.4 Crossbar A Select Register 3 (XBARA_SEL3).............................................................................................387
15.5.5 Crossbar A Select Register 4 (XBARA_SEL4).............................................................................................388
15.5.6 Crossbar A Select Register 5 (XBARA_SEL5).............................................................................................388
15.5.7 Crossbar A Select Register 6 (XBARA_SEL6).............................................................................................389
15.5.8 Crossbar A Select Register 7 (XBARA_SEL7).............................................................................................389
15.5.9 Crossbar A Select Register 8 (XBARA_SEL8).............................................................................................390
15.5.10 Crossbar A Select Register 9 (XBARA_SEL9).............................................................................................390
15.5.11 Crossbar A Select Register 10 (XBARA_SEL10).........................................................................................391
15.5.12 Crossbar A Select Register 11 (XBARA_SEL11).........................................................................................391
15.5.13 Crossbar A Select Register 12 (XBARA_SEL12).........................................................................................392
15.5.14 Crossbar A Select Register 13 (XBARA_SEL13).........................................................................................392
15.5.15 Crossbar A Select Register 14 (XBARA_SEL14).........................................................................................393
15.5.16 Crossbar A Select Register 15 (XBARA_SEL15).........................................................................................393
15.5.17 Crossbar A Select Register 16 (XBARA_SEL16).........................................................................................394
15.5.18 Crossbar A Select Register 17 (XBARA_SEL17).........................................................................................394
15.5.19 Crossbar A Select Register 18 (XBARA_SEL18).........................................................................................395
15.5.20 Crossbar A Select Register 19 (XBARA_SEL19).........................................................................................395
15.5.21 Crossbar A Select Register 20 (XBARA_SEL20).........................................................................................396
15.5.22 Crossbar A Select Register 21 (XBARA_SEL21).........................................................................................396
15.5.23 Crossbar A Select Register 22 (XBARA_SEL22).........................................................................................397
15.5.24 Crossbar A Select Register 23 (XBARA_SEL23).........................................................................................397
15.5.25 Crossbar A Select Register 24 (XBARA_SEL24).........................................................................................398
15.5.26 Crossbar A Select Register 25 (XBARA_SEL25).........................................................................................398
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Section number Title Page
15.5.27 Crossbar A Select Register 26 (XBARA_SEL26).........................................................................................399
15.5.28 Crossbar A Select Register 27 (XBARA_SEL27).........................................................................................399
15.5.29 Crossbar A Select Register 28 (XBARA_SEL28).........................................................................................400
15.5.30 Crossbar A Select Register 29 (XBARA_SEL29).........................................................................................400
15.5.31 Crossbar A Select Register 30 (XBARA_SEL30).........................................................................................401
15.5.32 Crossbar A Select Register 31 (XBARA_SEL31).........................................................................................401
15.5.33 Crossbar A Select Register 31 (XBARA_SEL32).........................................................................................402
15.5.34 Crossbar A Control Register 0 (XBARA_CTRL0)....................................................................................... 402
15.5.35 Crossbar A Control Register 1 (XBARA_CTRL1)....................................................................................... 404
Chapter 16
On-Chip Clock Synthesis (OCCS)
16.1 Introduction...................................................................................................................................................................407
16.1.1 Overview........................................................................................................................................................407
16.1.2 Features.......................................................................................................................................................... 407
16.2 Modes of Operation...................................................................................................................................................... 408
16.2.1 Internal Clock Sources...................................................................................................................................409
16.2.2 Loop Controlled Pierce Crystal Oscillator.....................................................................................................410
16.2.2.1 External Clock Source - Crystal Oscillator Bypass Option....................................................... 410
16.2.3 External Clock Source - CLKIN....................................................................................................................411
16.3 Block Diagram..............................................................................................................................................................412
16.4 Pin Description..............................................................................................................................................................413
16.4.1 External Clock Reference.............................................................................................................................. 413
16.4.2 Oscillator IO (XTAL, EXTAL)..................................................................................................................... 413
16.4.3 CLKO - Output Pins...................................................................................................................................... 413
16.5 Memory Map and Register Descriptions...................................................................................................................... 413
16.5.1 OCCS register descriptions............................................................................................................................414
16.5.1.1 OCCS memory map...................................................................................................................414
16.5.1.2 PLL Control Register (CTRL)................................................................................................... 414
16.5.1.3 PLL Divide-By Register (DIVBY)............................................................................................416
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NXP Semiconductors 17
Section number Title Page
16.5.1.4 OCCS Status Register (STAT).................................................................................................. 417
16.5.1.5 Oscillator Control Register 1 (OSCTL1)...................................................................................419
16.5.1.6 Oscillator Control Register 2 (OSCTL2)...................................................................................421
16.5.1.7 External Clock Check Reference (CLKCHKR)........................................................................ 422
16.5.1.8 External Clock Check Target (CLKCHKT).............................................................................. 423
16.5.1.9 Protection Register (PROT).......................................................................................................424
16.5.1.10 Oscillator Control Register 3 (OSCTL3)...................................................................................426
16.5.1.11 Oscillator Control Register 4 (OSCTL4)...................................................................................426
16.6 Functional Description..................................................................................................................................................427
16.7 RC Oscillators...............................................................................................................................................................431
16.7.1 Trimming Frequency on the Internal 8 MHz RC Oscillator..........................................................................431
16.7.2 Trimming Frequency on the Internal 200 kHz RC Oscillator....................................................................... 431
16.8 External Reference........................................................................................................................................................431
16.9 Crystal Oscillator.......................................................................................................................................................... 432
16.9.1 Switching Clock Sources............................................................................................................................... 432
16.10 Phase Locked Loop.......................................................................................................................................................433
16.10.1 PLL Recommended Range of Operation.......................................................................................................433
16.10.2 PLL Lock Time Specification........................................................................................................................434
16.10.2.1 Lock Time Definition.................................................................................................................434
16.10.2.2 Parametric Influences on Reaction Time...................................................................................434
16.11 PLL Frequency Lock Detector Block...........................................................................................................................435
16.12 Loss of Reference Clock Detector................................................................................................................................ 435
16.13 Resets............................................................................................................................................................................436
16.14 Clocks........................................................................................................................................................................... 436
16.15 Interrupts.......................................................................................................................................................................437
Chapter 17
Flash Memory Controller (FMC)
17.1 Introduction...................................................................................................................................................................439
17.1.1 Overview........................................................................................................................................................439
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17.1.2 Features.......................................................................................................................................................... 439
17.2 Modes of operation....................................................................................................................................................... 440
17.3 External signal description............................................................................................................................................441
17.4 Memory map and register descriptions.........................................................................................................................441
17.4.1 FMC register descriptions..............................................................................................................................441
17.4.1.1 FMC memory map.....................................................................................................................441
17.4.1.2 Flash Cache Control Register (FCCR).......................................................................................441
17.4.1.3 Flash Cache Access Register (FCAR)....................................................................................... 442
17.4.1.4 Flash Cache Tag (FCTG)...........................................................................................................443
17.4.1.5 Flash Cache Line0 (FCLN0)......................................................................................................444
17.5 Functional description...................................................................................................................................................445
17.5.1 Default configuration..................................................................................................................................... 445
17.5.2 Configuration options.................................................................................................................................... 446
17.5.3 Speculative reads............................................................................................................................................446
17.6 Initialization and application information.....................................................................................................................447
Chapter 18
Flash Memory Module (FTFA)
18.1 Chip-specific information for this module....................................................................................................................449
18.1.1 Flash memory types and terminology............................................................................................................449
18.1.2 FOPT Register................................................................................................................................................449
18.2 Introduction...................................................................................................................................................................450
18.2.1 Features.......................................................................................................................................................... 450
18.2.1.1 Program Flash Memory Features...............................................................................................450
18.2.1.2 Other Flash Memory Module Features...................................................................................... 451
18.2.2 Block Diagram............................................................................................................................................... 451
18.2.3 Glossary......................................................................................................................................................... 451
18.3 External Signal Description.......................................................................................................................................... 453
18.4 Memory Map and Registers..........................................................................................................................................453
18.4.1 Flash Configuration Field Description...........................................................................................................453
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NXP Semiconductors 19
Section number Title Page
18.4.2 Program Flash IFR Map.................................................................................................................................453
18.4.2.1 Program Once Field................................................................................................................... 454
18.4.3 Register Descriptions..................................................................................................................................... 454
18.4.3.1 Flash Status Register (FTFA_FSTAT)...................................................................................... 456
18.4.3.2 Flash Configuration Register (FTFA_FCNFG).........................................................................457
18.4.3.3 Flash Security Register (FTFA_FSEC)..................................................................................... 458
18.4.3.4 Flash Option Register (FTFA_FOPT)....................................................................................... 460
18.4.3.5
Flash Common Command Object Registers (FTFA_FCCOBn)............................................... 461
18.4.3.6
Program Flash Protection Registers (FTFA_FPROTn).............................................................462
18.5 Functional Description..................................................................................................................................................463
18.5.1 Flash Protection..............................................................................................................................................463
18.5.2 Interrupts........................................................................................................................................................ 464
18.5.3 Flash Operation in Low-Power Modes.......................................................................................................... 465
18.5.3.1 Wait Mode..................................................................................................................................465
18.5.3.2 Stop Mode..................................................................................................................................465
18.5.4 Functional Modes of Operation..................................................................................................................... 465
18.5.5 Flash Reads and Ignored Writes.................................................................................................................... 465
18.5.6 Read While Write (RWW).............................................................................................................................466
18.5.7 Flash Program and Erase................................................................................................................................466
18.5.8 Flash Command Operations...........................................................................................................................466
18.5.8.1 Command Write Sequence.........................................................................................................466
18.5.8.2 Flash Commands........................................................................................................................469
18.5.8.3 Flash Commands by Mode........................................................................................................ 470
18.5.9 Margin Read Commands............................................................................................................................... 471
18.5.10 Flash Command Description..........................................................................................................................472
18.5.10.1 Read 1s Section Command........................................................................................................ 473
18.5.10.2 Program Check Command.........................................................................................................474
18.5.10.3 Read Resource Command..........................................................................................................475
18.5.10.4 Program Longword Command...................................................................................................476
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20 NXP Semiconductors
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