K32 L2A Reference Manual
K32L2A41VLL1A, K32L2A31VLL1A, K32L2A41VLH1A,
K32L2A31VLH1A
Document Number: K32L2AxRM
Rev. 2, 01/2020
K32 L2A Reference Manual, Rev. 2, 01/2020
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................43
1.1.1 Purpose...........................................................................................................................................................43
1.1.2 Audience........................................................................................................................................................ 43
1.2 Conventions.................................................................................................................................................................. 43
1.2.1 Numbering systems........................................................................................................................................43
1.2.2 Typographic notation..................................................................................................................................... 44
1.2.3 Special terms..................................................................................................................................................44
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................45
2.2 K32 L2A introduction...................................................................................................................................................45
2.3 Feature Summary..........................................................................................................................................................45
2.4 Block Diagram..............................................................................................................................................................49
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................51
3.2 Clock gating..................................................................................................................................................................51
3.3 Module to Module Interconnects..................................................................................................................................52
3.3.1 Interconnection overview...............................................................................................................................52
3.3.2 Analog reference options............................................................................................................................... 52
3.4 Core Modules................................................................................................................................................................53
3.4.1 Introduction....................................................................................................................................................53
3.4.2 Arm Cortex M0+ core ...................................................................................................................................53
3.4.3 Debug facilities.............................................................................................................................................. 54
3.4.4 Buses, interconnects, and interfaces.............................................................................................................. 54
3.4.5 System tick timer........................................................................................................................................... 54
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3.4.6 Caches............................................................................................................................................................ 54
3.4.7 Interrupt connections......................................................................................................................................55
3.4.8 Asynchronous Wake-up Interrupt Controller (AWIC).................................................................................. 59
3.5 System Modules............................................................................................................................................................60
3.5.1 Crossbar Switch............................................................................................................................................. 60
3.5.2 Low-Leakage Wake-up Unit (LLWU)...........................................................................................................61
3.5.3 DMAMUX.....................................................................................................................................................62
3.5.4 Watchdog (WDOG)....................................................................................................................................... 64
3.5.5 System Register File Configuration...............................................................................................................64
3.5.6 Peripheral Clock Control (PCC) Configuration.............................................................................................65
3.5.7 System Register File Configuration...............................................................................................................66
3.6 Security......................................................................................................................................................................... 67
3.6.1 CAU Configuration........................................................................................................................................67
3.7 Analog...........................................................................................................................................................................68
3.7.1 16-bit SAR ADC configuration..................................................................................................................... 68
3.7.2 CMP configuration.........................................................................................................................................70
3.7.3 VREF............................................................................................................................................................. 72
3.7.4 12-bit DAC configuration.............................................................................................................................. 74
3.8 Timers........................................................................................................................................................................... 75
3.8.1 Timer/PWM module configuration................................................................................................................75
3.8.2 LPIT............................................................................................................................................................... 77
3.8.3 Low Power Timer (LPTMR)......................................................................................................................... 78
3.8.4 RTC configuration......................................................................................................................................... 79
3.9 Communication interfaces............................................................................................................................................ 80
3.9.1 Universal Serial Bus (USB) FS Subsystem................................................................................................... 80
3.9.2 LPSPI configuration.......................................................................................................................................86
3.9.3 LPI2C.............................................................................................................................................................87
3.9.4 LPUART configuration..................................................................................................................................88
3.9.5 EMVSIM Configuration................................................................................................................................ 89
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3.9.6 FlexIO ........................................................................................................................................................... 89
3.10 Human-machine interfaces (HMI)................................................................................................................................90
3.10.1 GPIO configuration........................................................................................................................................90
3.10.2 TSI configuration........................................................................................................................................... 91
3.11 Signal multiplexing integration.................................................................................................................................... 93
3.11.1 Signal multiplexing configuration................................................................................................................. 93
Chapter 4
Memory Map
4.1 Memory Map ............................................................................................................................................................... 95
4.2 SRAM sizes.................................................................................................................................................................. 95
4.3 System Memory Map....................................................................................................................................................95
4.3.1 Memory Map .................................................................................................................................................95
4.4 Flash Memory Maps..................................................................................................................................................... 97
4.4.1 Flash Memory Map........................................................................................................................................97
4.5 SRAM Memory Map....................................................................................................................................................98
4.6 Bit Manipulation Engine...............................................................................................................................................98
4.7 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................99
4.7.1 AIPS0 Peripheral Slot Assignments.............................................................................................................. 99
4.7.2 AIPS1 Peripheral Slot Assignments.............................................................................................................. 103
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................107
5.2 Clock Sources............................................................................................................................................................... 108
5.3 SCG Output Clocks...................................................................................................................................................... 109
5.3.1 DIVCORE_CLK............................................................................................................................................109
5.3.2 DIVSLOW_CLK........................................................................................................................................... 109
5.3.3 Peripheral functional clocks...........................................................................................................................109
5.4 Peripheral Clock Summary...........................................................................................................................................112
5.5 DIV3 Peripheral Clocking............................................................................................................................................ 114
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5.6 DIV1 Peripheral Clocking............................................................................................................................................ 115
5.7 Programming model......................................................................................................................................................116
5.8 Other Clock Sources..................................................................................................................................................... 117
5.8.1 OSC32KCLK.................................................................................................................................................117
5.8.2 LPO Low Power Oscillator............................................................................................................................117
5.9 Clock definitions...........................................................................................................................................................117
5.10 Clocking details............................................................................................................................................................ 118
5.11 Internal Clocking Requirements................................................................................................................................... 119
5.12 Clock divider values after reset.....................................................................................................................................120
5.13 Clock gating..................................................................................................................................................................121
5.14 Flash Memory Clock.....................................................................................................................................................121
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................123
6.2 Reset..............................................................................................................................................................................124
6.2.1 Power-on reset (POR).................................................................................................................................... 124
6.2.2 System reset sources...................................................................................................................................... 124
6.2.3 MCU resets.................................................................................................................................................... 127
6.2.4 RESET_b pin ................................................................................................................................................ 128
6.2.5 Debug resets...................................................................................................................................................129
6.3 Boot...............................................................................................................................................................................129
6.3.1 Boot sources...................................................................................................................................................129
6.3.2 FOPT boot options.........................................................................................................................................130
6.3.3 Boot sequence................................................................................................................................................ 131
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................135
7.2 Clocking modes............................................................................................................................................................ 135
7.2.1 Partial Stop.....................................................................................................................................................135
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7.2.2 DMA Wakeup................................................................................................................................................136
7.2.3 Compute Operation........................................................................................................................................137
7.2.4 Peripheral Doze..............................................................................................................................................138
7.2.5 Clock gating................................................................................................................................................... 139
7.3 Power Mode Architecture.............................................................................................................................................139
7.4 Power modes.................................................................................................................................................................139
7.5 Entering and exiting power modes............................................................................................................................... 142
7.6 Module operation in low-power modes........................................................................................................................ 142
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................147
8.1.1 Debug security............................................................................................................................................... 147
8.1.2 Flash security................................................................................................................................................. 147
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................149
9.2 Debug port pin descriptions..........................................................................................................................................149
9.3 Debug and Trace Block diagram.................................................................................................................................. 150
9.4 SWD status and control registers..................................................................................................................................151
9.4.1 MDM-AP Control Register............................................................................................................................152
9.4.2 MDM-AP Status Register.............................................................................................................................. 153
9.5 Debug resets..................................................................................................................................................................155
9.6 Micro Trace Buffer (MTB)...........................................................................................................................................156
9.7 Debug in low-power modes..........................................................................................................................................156
9.8 Debug and security....................................................................................................................................................... 157
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................159
10.2 Pinout............................................................................................................................................................................159
10.2.1 Package types.................................................................................................................................................159
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10.2.2 Signal Multiplexing and Pin Assignments.....................................................................................................159
10.2.3 K32 L2A Pinouts........................................................................................................................................... 164
10.3 Module Signal Description Tables................................................................................................................................166
10.3.1 Core modules................................................................................................................................................. 166
10.3.2 System modules............................................................................................................................................. 167
10.3.3 Clock modules................................................................................................................................................167
10.3.4 Memories and memory interfaces..................................................................................................................167
10.3.5 Analog............................................................................................................................................................168
10.3.6 Timer Modules...............................................................................................................................................168
10.3.7 Communication interfaces............................................................................................................................. 169
10.3.8 Human-machine interfaces (HMI).................................................................................................................173
Chapter 11
Analog-to-Digital Converter (ADC)
11.1 Introduction...................................................................................................................................................................175
11.1.1 Features.......................................................................................................................................................... 175
11.1.2 Block diagram................................................................................................................................................176
11.2 ADC signal descriptions............................................................................................................................................... 177
11.2.1 Analog Power (VDDA)................................................................................................................................. 178
11.2.2 Analog Ground (VSSA).................................................................................................................................178
11.2.3 Voltage Reference Select...............................................................................................................................178
11.2.4 Analog Channel Inputs (ADx)....................................................................................................................... 179
11.2.5 Differential Analog Channel Inputs (DADx).................................................................................................179
11.3 Memory map and register definitions...........................................................................................................................179
11.3.1
ADC Status and Control Registers 1 (ADCx_SC1n).....................................................................................180
11.3.2
ADC Configuration Register 1 (ADCx_CFG1).............................................................................................184
11.3.3
ADC Configuration Register 2 (ADCx_CFG2).............................................................................................185
11.3.4
ADC Data Result Register (ADCx_Rn).........................................................................................................186
11.3.5
Compare Value Registers (ADCx_CVn)....................................................................................................... 188
11.3.6
Status and Control Register 2 (ADCx_SC2)..................................................................................................189
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11.3.7
Status and Control Register 3 (ADCx_SC3)..................................................................................................191
11.3.8
ADC Offset Correction Register (ADCx_OFS).............................................................................................192
11.3.9
ADC Plus-Side Gain Register (ADCx_PG)...................................................................................................193
11.3.10
ADC Minus-Side Gain Register (ADCx_MG).............................................................................................. 193
11.3.11
ADC Plus-Side General Calibration Value Register (ADCx_CLPD)........................................................... 194
11.3.12
ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............................................................195
11.3.13
ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............................................................ 195
11.3.14
ADC Plus-Side General Calibration Value Register (ADCx_CLP3)............................................................ 196
11.3.15
ADC Plus-Side General Calibration Value Register (ADCx_CLP2)............................................................ 196
11.3.16
ADC Plus-Side General Calibration Value Register (ADCx_CLP1)............................................................ 197
11.3.17
ADC Plus-Side General Calibration Value Register (ADCx_CLP0)............................................................ 197
11.3.18
ADC Minus-Side General Calibration Value Register (ADCx_CLMD).......................................................198
11.3.19
ADC Minus-Side General Calibration Value Register (ADCx_CLMS)....................................................... 198
11.3.20
ADC Minus-Side General Calibration Value Register (ADCx_CLM4)....................................................... 199
11.3.21
ADC Minus-Side General Calibration Value Register (ADCx_CLM3)....................................................... 199
11.3.22
ADC Minus-Side General Calibration Value Register (ADCx_CLM2)....................................................... 200
11.3.23
ADC Minus-Side General Calibration Value Register (ADCx_CLM1)....................................................... 200
11.3.24
ADC Minus-Side General Calibration Value Register (ADCx_CLM0)....................................................... 201
11.4 Functional description...................................................................................................................................................201
11.4.1 Clock select and divide control......................................................................................................................202
11.4.2 Voltage reference selection............................................................................................................................203
11.4.3 Hardware trigger and channel selects............................................................................................................ 203
11.4.4 Conversion control.........................................................................................................................................204
11.4.5 Automatic compare function..........................................................................................................................212
11.4.6 Calibration function....................................................................................................................................... 213
11.4.7 User-defined offset function.......................................................................................................................... 215
11.4.8 Temperature sensor........................................................................................................................................216
11.4.9 MCU wait mode operation.............................................................................................................................217
11.4.10 MCU Normal Stop mode operation...............................................................................................................217
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11.5 Initialization information.............................................................................................................................................. 218
11.5.1 ADC module initialization example.............................................................................................................. 219
11.6 Application information................................................................................................................................................221
11.6.1 External pins and routing............................................................................................................................... 221
11.6.2 Sources of error..............................................................................................................................................223
Chapter 12
Crossbar Switch Lite (AXBS-Lite)
12.1 Introduction...................................................................................................................................................................227
12.1.1 Features.......................................................................................................................................................... 227
12.2 Memory Map / Register Definition...............................................................................................................................228
12.3 Functional Description..................................................................................................................................................228
12.3.1 General operation...........................................................................................................................................228
Chapter 13
Bit Manipulation Engine2 (BME2)
13.1 Introduction...................................................................................................................................................................229
13.1.1 Features.......................................................................................................................................................... 230
13.1.2 Modes of operation........................................................................................................................................ 230
13.2 Memory map and register definition.............................................................................................................................230
13.3 Functional description...................................................................................................................................................231
13.3.1 BME decorated stores.................................................................................................................................... 231
13.3.2 BME decorated loads.....................................................................................................................................238
13.4 Application information................................................................................................................................................244
Chapter 14
Kinetis ROM Bootloader
14.1 Chip-Specific Information............................................................................................................................................ 247
14.1.1 Kinetis Bootloader Peripheral Pinmux.......................................................................................................... 247
14.1.2 Bootloader Memory Access...........................................................................................................................248
14.2 Introduction...................................................................................................................................................................248
14.3 Functional Description..................................................................................................................................................250
14.3.1 Memory Maps................................................................................................................................................250
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14.3.2 The Kinetis Bootloader Configuration Area (BCA)......................................................................................251
14.3.3 Start-up Process..............................................................................................................................................253
14.3.4 Clock Configuration.......................................................................................................................................255
14.3.5 Bootloader Entry Point / API Tree.................................................................................................................256
14.3.6 Bootloader Protocol....................................................................................................................................... 257
14.3.7 Bootloader Packet Types............................................................................................................................... 262
14.3.8 Bootloader Command API.............................................................................................................................270
14.3.9 Bootloader Exit state......................................................................................................................................293
14.4 Peripherals Supported................................................................................................................................................... 294
14.4.1 LPI2C Peripheral............................................................................................................................................294
14.4.2 LPSPI Peripheral............................................................................................................................................296
14.4.3 QuadSPI Peripheral .......................................................................................................................................298
14.4.4 LPUART Peripheral.......................................................................................................................................307
14.4.5 USB peripheral...............................................................................................................................................309
14.5 Get/SetProperty Command Properties..........................................................................................................................313
14.5.1 Property Definitions.......................................................................................................................................314
14.6 SB File Decryption Support..........................................................................................................................................316
14.6.1 Decryption using MMCAU........................................................................................................................... 317
14.7 Verifying the application in flash using CRC-32......................................................................................................... 318
14.8 Kinetis Bootloader Status Error Codes.........................................................................................................................319
Chapter 15
Cryptographic Acceleration Unit (CAU)
15.1 Introduction...................................................................................................................................................................323
15.2 CAU Block Diagram.....................................................................................................................................................323
15.3 Overview.......................................................................................................................................................................325
15.4 Features.........................................................................................................................................................................326
15.5 Memory map/Register definition..................................................................................................................................326
15.5.1
Status Register (CAUx_CASR)..................................................................................................................... 328
15.5.2
Accumulator (CAUx_CAA).......................................................................................................................... 329
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15.5.3
General Purpose Register (CAUx_CAn)....................................................................................................... 329
15.6 Functional description...................................................................................................................................................330
15.6.1 CAU programming model............................................................................................................................. 330
15.6.2 CAU integrity checks.....................................................................................................................................332
15.6.3 CAU commands.............................................................................................................................................334
15.7 Application/initialization information.......................................................................................................................... 341
15.7.1 Code example.................................................................................................................................................341
15.7.2 Assembler equate values................................................................................................................................342
Chapter 16
Comparator (CMP)
16.1 Introduction...................................................................................................................................................................345
16.1.1 CMP features..................................................................................................................................................345
16.1.2 6-bit DAC key features.................................................................................................................................. 346
16.1.3 ANMUX key features.................................................................................................................................... 346
16.1.4 CMP, DAC and ANMUX diagram................................................................................................................347
16.1.5 CMP block diagram....................................................................................................................................... 348
16.2 Memory map/register definitions..................................................................................................................................350
16.2.1
CMP Control Register 0 (CMPx_CR0)......................................................................................................... 350
16.2.2
CMP Control Register 1 (CMPx_CR1)......................................................................................................... 351
16.2.3
CMP Filter Period Register (CMPx_FPR).....................................................................................................353
16.2.4
CMP Status and Control Register (CMPx_SCR)...........................................................................................353
16.2.5
DAC Control Register (CMPx_DACCR)......................................................................................................354
16.2.6
MUX Control Register (CMPx_MUXCR).................................................................................................... 355
16.3 Functional description...................................................................................................................................................356
16.3.1 CMP functional modes...................................................................................................................................356
16.3.2 Power modes..................................................................................................................................................366
16.3.3 Startup and operation..................................................................................................................................... 367
16.3.4 Low-pass filter............................................................................................................................................... 368
16.4 CMP interrupts..............................................................................................................................................................370
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16.5 DMA support................................................................................................................................................................ 370
16.6 CMP Asynchronous DMA support...............................................................................................................................371
16.7 Digital-to-analog converter...........................................................................................................................................372
16.8 DAC functional description.......................................................................................................................................... 372
16.8.1 Voltage reference source select......................................................................................................................372
16.9 DAC resets....................................................................................................................................................................373
16.10 DAC clocks...................................................................................................................................................................373
16.11 DAC interrupts..............................................................................................................................................................373
16.12 CMP Trigger Mode.......................................................................................................................................................373
Chapter 17
Cyclic Redundancy Check (CRC)
17.1 Introduction...................................................................................................................................................................375
17.1.1 Features.......................................................................................................................................................... 375
17.1.2 Block diagram................................................................................................................................................375
17.1.3 Modes of operation........................................................................................................................................ 376
17.2 Memory map and register descriptions.........................................................................................................................376
17.2.1 CRC Data register (CRC_DATA)................................................................................................................. 377
17.2.2 CRC Polynomial register (CRC_GPOLY).................................................................................................... 378
17.2.3 CRC Control register (CRC_CTRL)..............................................................................................................378
17.3 Functional description...................................................................................................................................................379
17.3.1 CRC initialization/reinitialization..................................................................................................................379
17.3.2 CRC calculations............................................................................................................................................380
17.3.3 Transpose feature........................................................................................................................................... 381
17.3.4 CRC result complement.................................................................................................................................383
Chapter 18
12-bit Digital-to-Analog Converter (DAC)
18.1 Introduction...................................................................................................................................................................385
18.2 Features.........................................................................................................................................................................385
18.3 Block diagram...............................................................................................................................................................385
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18.4 Memory map/register definition................................................................................................................................... 386
18.4.1
DAC Data Low Register (DACx_DATnL)................................................................................................... 388
18.4.2
DAC Data High Register (DACx_DATnH).................................................................................................. 388
18.4.3
DAC Status Register (DACx_SR)................................................................................................................. 388
18.4.4
DAC Control Register (DACx_C0)............................................................................................................... 389
18.4.5
DAC Control Register 1 (DACx_C1)............................................................................................................ 391
18.4.6
DAC Control Register 2 (DACx_C2)............................................................................................................ 392
18.5 Functional description...................................................................................................................................................392
18.5.1 DAC data buffer operation.............................................................................................................................392
18.5.2 DMA operation.............................................................................................................................................. 393
18.5.3 Resets............................................................................................................................................................. 393
18.5.4 Low-Power mode operation...........................................................................................................................394
Chapter 19
Direct Memory Access Multiplexer (DMAMUX)
19.1 Introduction...................................................................................................................................................................395
19.1.1 Overview........................................................................................................................................................395
19.1.2 Features.......................................................................................................................................................... 396
19.1.3 Modes of operation........................................................................................................................................ 396
19.2 External signal description............................................................................................................................................397
19.3 Memory map/register definition................................................................................................................................... 397
19.3.1
Channel Configuration register (DMAMUXx_CHCFGn)............................................................................ 398
19.4 Functional description...................................................................................................................................................398
19.4.1 DMA channels with periodic triggering capability........................................................................................399
19.4.2 DMA channels with no triggering capability.................................................................................................401
19.4.3 Always-enabled DMA sources...................................................................................................................... 401
19.5 Initialization/application information........................................................................................................................... 403
19.5.1 Reset...............................................................................................................................................................403
19.5.2 Enabling and configuring sources..................................................................................................................403
Chapter 20
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Enhanced Direct Memory Access (eDMA)
20.1 Introduction...................................................................................................................................................................407
20.1.1 eDMA system block diagram........................................................................................................................ 407
20.1.2 Block parts..................................................................................................................................................... 408
20.1.3 Features.......................................................................................................................................................... 409
20.2 Modes of operation....................................................................................................................................................... 410
20.3 Memory map/register definition................................................................................................................................... 411
20.3.1 TCD memory................................................................................................................................................. 411
20.3.2 TCD initialization.......................................................................................................................................... 411
20.3.3 TCD structure.................................................................................................................................................411
20.3.4 Reserved memory and bit fields.....................................................................................................................412
20.3.5
Control Register (DMAx_CR).......................................................................................................................418
20.3.6
Error Status Register (DMAx_ES).................................................................................................................421
20.3.7
Enable Request Register (DMAx_ERQ)........................................................................................................423
20.3.8
Enable Error Interrupt Register (DMAx_EEI)...............................................................................................425
20.3.9
Clear Enable Error Interrupt Register (DMAx_CEEI).................................................................................. 426
20.3.10
Set Enable Error Interrupt Register (DMAx_SEEI)...................................................................................... 427
20.3.11
Clear Enable Request Register (DMAx_CERQ)........................................................................................... 428
20.3.12
Set Enable Request Register (DMAx_SERQ)............................................................................................... 429
20.3.13
Clear DONE Status Bit Register (DMAx_CDNE)........................................................................................ 430
20.3.14
Set START Bit Register (DMAx_SSRT)...................................................................................................... 431
20.3.15
Clear Error Register (DMAx_CERR)............................................................................................................432
20.3.16
Clear Interrupt Request Register (DMAx_CINT)..........................................................................................433
20.3.17
Interrupt Request Register (DMAx_INT)......................................................................................................434
20.3.18
Error Register (DMAx_ERR)........................................................................................................................ 435
20.3.19
Hardware Request Status Register (DMAx_HRS)........................................................................................ 437
20.3.20
Enable Asynchronous Request in Stop Register (DMAx_EARS).................................................................439
20.3.21
Channel n Priority Register (DMAx_DCHPRIn).......................................................................................... 440
20.3.22
TCD Source Address (DMAx_TCDn_SADDR)........................................................................................... 441
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20.3.23
TCD Signed Source Address Offset (DMAx_TCDn_SOFF)........................................................................441
20.3.24
TCD Transfer Attributes (DMAx_TCDn_ATTR).........................................................................................442
20.3.25
TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMAx_TCDn_NBYTES_MLNO)................. 443
20.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMAx_TCDn_NBYTES_MLOFFNO)....................................................................................................... 443
20.3.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMAx_TCDn_NBYTES_MLOFFYES)..................................................................................................... 445
20.3.28
TCD Last Source Address Adjustment (DMAx_TCDn_SLAST).................................................................446
20.3.29
TCD Destination Address (DMAx_TCDn_DADDR)................................................................................... 446
20.3.30
TCD Signed Destination Address Offset (DMAx_TCDn_DOFF)................................................................447
20.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMAx_TCDn_CITER_ELINKYES)...........................................................................................................447
20.3.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMAx_TCDn_CITER_ELINKNO).............................................................................................................449
20.3.33
TCD Last Destination Address Adjustment/Scatter Gather Address (DMAx_TCDn_DLASTSGA)...........450
20.3.34
TCD Control and Status (DMAx_TCDn_CSR).............................................................................................450
20.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMAx_TCDn_BITER_ELINKYES)...........................................................................................................453
20.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMAx_TCDn_BITER_ELINKNO).............................................................................................................454
20.4 Functional description...................................................................................................................................................455
20.4.1 eDMA basic data flow................................................................................................................................... 455
20.4.2 Fault reporting and handling..........................................................................................................................458
20.4.3 Channel preemption....................................................................................................................................... 461
20.4.4 Performance................................................................................................................................................... 461
20.5 Initialization/application information........................................................................................................................... 465
20.5.1 eDMA initialization....................................................................................................................................... 465
20.5.2 Programming errors....................................................................................................................................... 467
20.5.3 Arbitration mode considerations....................................................................................................................468
20.5.4 Performing DMA transfers............................................................................................................................ 468
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20.5.5 Monitoring transfer descriptor status............................................................................................................. 472
20.5.6 Channel Linking.............................................................................................................................................474
20.5.7 Dynamic programming.................................................................................................................................. 475
20.5.8 Suspend/resume a DMA channel with active hardware service requests......................................................479
Chapter 21
Smart Card Interface Module (EMV SIM)
21.1 Introduction...................................................................................................................................................................481
21.1.1 Features.......................................................................................................................................................... 481
21.2 Block Diagram..............................................................................................................................................................482
21.3 Design Overview.......................................................................................................................................................... 482
21.4 Signal Description.........................................................................................................................................................484
21.5 Memory Map and Registers..........................................................................................................................................485
21.5.1
Version ID Register (EMVSIMx_VER_ID)..................................................................................................486
21.5.2
Parameter Register (EMVSIMx_PARAM)................................................................................................... 486
21.5.3
Clock Configuration Register (EMVSIMx_CLKCFG)................................................................................. 487
21.5.4
Baud Rate Divisor Register (EMVSIMx_DIVISOR)....................................................................................488
21.5.5
Control Register (EMVSIMx_CTRL)........................................................................................................... 489
21.5.6
Interrupt Mask Register (EMVSIMx_INT_MASK)......................................................................................493
21.5.7
Receiver Threshold Register (EMVSIMx_RX_THD)...................................................................................496
21.5.8
Transmitter Threshold Register (EMVSIMx_TX_THD).............................................................................. 496
21.5.9
Receive Status Register (EMVSIMx_RX_STATUS)....................................................................................498
21.5.10
Transmitter Status Register (EMVSIMx_TX_STATUS)..............................................................................501
21.5.11
Port Control and Status Register (EMVSIMx_PCSR)...................................................................................504
21.5.12
Receive Data Read Buffer (EMVSIMx_RX_BUF).......................................................................................506
21.5.13
Transmit Data Buffer (EMVSIMx_TX_BUF)...............................................................................................507
21.5.14
Transmitter Guard ETU Value Register (EMVSIMx_TX_GETU)...............................................................507
21.5.15
Character Wait Time Value Register (EMVSIMx_CWT_VAL)...................................................................508
21.5.16
Block Wait Time Value Register (EMVSIMx_BWT_VAL)........................................................................ 508
21.5.17
Block Guard Time Value Register (EMVSIMx_BGT_VAL)....................................................................... 509
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NXP Semiconductors 17
Section number Title Page
21.5.18
General Purpose Counter 0 Timeout Value Register (EMVSIMx_GPCNT0_VAL)....................................509
21.5.19
General Purpose Counter 1 Timeout Value (EMVSIMx_GPCNT1_VAL).................................................. 510
21.6 Functional Description..................................................................................................................................................510
21.6.1 Initialization................................................................................................................................................... 510
21.6.2 Smart Card Interface and Control.................................................................................................................. 512
21.6.3 EMV SIM Receiver....................................................................................................................................... 515
21.6.4 EMV SIM Transmitter...................................................................................................................................519
21.6.5 LRC and CRC................................................................................................................................................ 521
21.6.6 Message Handling..........................................................................................................................................523
21.6.7 Protocol Timers..............................................................................................................................................525
21.6.8 Answer To Reset (ATR) Detection................................................................................................................528
Chapter 22
Flexible I/O (FlexIO)
22.1 Introduction...................................................................................................................................................................533
22.1.1 Overview........................................................................................................................................................533
22.1.2 Features.......................................................................................................................................................... 533
22.1.3 Block Diagram............................................................................................................................................... 534
22.1.4 Modes of operation........................................................................................................................................ 535
22.1.5 FlexIO Signal Descriptions............................................................................................................................535
22.2 Memory Map and Registers..........................................................................................................................................535
22.2.1 FLEXIO Register Descriptions......................................................................................................................535
22.3 Functional description...................................................................................................................................................565
22.3.1 Shifter operation.............................................................................................................................................565
22.3.2 Timer operation..............................................................................................................................................571
22.3.3 Pin operation.................................................................................................................................................. 573
22.4 Application Information................................................................................................................................................575
22.4.1 UART Transmit............................................................................................................................................. 575
22.4.2 UART Receive...............................................................................................................................................576
22.4.3 SPI Master......................................................................................................................................................578
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18 NXP Semiconductors
Section number Title Page
22.4.4 SPI Slave........................................................................................................................................................580
22.4.5 I2C Master......................................................................................................................................................581
22.4.6 I2S Master......................................................................................................................................................583
22.4.7 I2S Slave........................................................................................................................................................ 585
22.4.8 Camera Interface............................................................................................................................................586
22.4.9 Motorola 68K/Intel 8080 Bus Interface.........................................................................................................587
22.4.10 Low Power State Machine............................................................................................................................. 589
Chapter 23
Flash Memory Controller (FMC)
23.1 Introduction...................................................................................................................................................................593
23.1.1 Overview........................................................................................................................................................593
23.1.2 Features.......................................................................................................................................................... 594
23.2 Modes of operation....................................................................................................................................................... 594
23.3 External signal description............................................................................................................................................594
23.4 Memory map and register descriptions.........................................................................................................................594
23.5 Flash Access Control (FAC) Function..........................................................................................................................595
23.5.1 Memory map and register definitions............................................................................................................ 595
23.5.2 FAC functional description............................................................................................................................595
23.6 Initialization and application information.....................................................................................................................601
Chapter 24
Flash Memory Module (FTFA)
24.1 Introduction...................................................................................................................................................................603
24.1.1 Features.......................................................................................................................................................... 604
24.1.2 Block Diagram............................................................................................................................................... 604
24.1.3 Glossary......................................................................................................................................................... 605
24.2 External Signal Description.......................................................................................................................................... 606
24.3 Memory Map and Registers..........................................................................................................................................607
24.3.1 Flash Configuration Field Description...........................................................................................................607
24.3.2 Program Flash IFR Map.................................................................................................................................607
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NXP Semiconductors 19
Section number Title Page
24.3.3 Program Flash Erasable IFR Map..................................................................................................................608
24.3.4 Register Descriptions..................................................................................................................................... 609
24.4 Functional Description..................................................................................................................................................622
24.4.1 Flash Protection..............................................................................................................................................622
24.4.2 Flash Access Protection................................................................................................................................. 623
24.4.3 Interrupts........................................................................................................................................................ 625
24.4.4 Flash Operation in Low-Power Modes.......................................................................................................... 625
24.4.5 Functional Modes of Operation..................................................................................................................... 626
24.4.6 Flash Reads and Ignored Writes.................................................................................................................... 626
24.4.7 Read While Write (RWW).............................................................................................................................626
24.4.8 Flash Program and Erase................................................................................................................................626
24.4.9 Flash Command Operations...........................................................................................................................627
24.4.10 Margin Read Commands............................................................................................................................... 632
24.4.11 Flash Command Description..........................................................................................................................633
24.4.12 Security.......................................................................................................................................................... 652
24.4.13 Reset Sequence.............................................................................................................................................. 655
Chapter 25
Interrupt Multiplexer (INTMUX)
25.1 About this module.........................................................................................................................................................657
25.1.1 Introduction....................................................................................................................................................657
25.1.2 Features.......................................................................................................................................................... 657
25.1.3 Block diagram................................................................................................................................................657
25.2 Memory Map and register definition............................................................................................................................ 658
25.2.1
Channel n Control Status Register (INTMUXx_CHn_CSR)........................................................................ 659
25.2.2
Channel n Vector Number Register (INTMUXx_CHn_VEC)......................................................................660
25.2.3
Channel n Interrupt Enable Register (INTMUXx_CHn_IER_31_0)............................................................ 661
25.2.4
Channel n Interrupt Pending Register (INTMUXx_CHn_IPR_31_0)...........................................................661
25.3 Functional Description..................................................................................................................................................662
25.3.1 Configuring Output Channels........................................................................................................................ 662
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20 NXP Semiconductors
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