NXP MWCT1x23 Reference guide

MWCT1x23 Reference Manual

Supports MWCT1023IFVLL and MWCT1123FVLL

Document Number: MWCT1123FVLLRM

Rev. 0, 12/2019

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Contents

Section number Title Page

Chapter 1

About This Document

1.1 Overview.......................................................................................................................................................................57

1.1.1 Purpose...........................................................................................................................................................57

1.1.2 Audience........................................................................................................................................................ 57

1.2 Conventions.................................................................................................................................................................. 57

1.2.1 Numbering systems........................................................................................................................................57

1.2.2 Typographic notation..................................................................................................................................... 58

1.2.3 Special terms..................................................................................................................................................58

Chapter 2

Introduction

2.1 Overview.......................................................................................................................................................................59

2.2 Module Functional Categories......................................................................................................................................59

2.2.1 Arm® Cortex®-M4 Core Modules................................................................................................................60

2.2.2 System Modules.............................................................................................................................................61

2.2.3 Memories and Memory Interfaces................................................................................................................. 62

2.2.4 Clocks.............................................................................................................................................................62

2.2.5 Security and Integrity modules...................................................................................................................... 62

2.2.6 Analog modules............................................................................................................................................. 63

2.2.7 Timer modules............................................................................................................................................... 63

2.2.8 Communication interfaces............................................................................................................................. 64

2.2.9 Human-machine interfaces............................................................................................................................ 65

2.3 Orderable part numbers and features............................................................................................................................ 65

Chapter 3

Core overview

3.1 Arm Cortex-M4 Core Configuration............................................................................................................................ 67

3.1.1 Buses, interconnects, and interfaces.............................................................................................................. 68

3.1.2 System Tick Timer.........................................................................................................................................68

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3.1.3 Debug facilities.............................................................................................................................................. 68

3.1.4 Core privilege levels...................................................................................................................................... 69

3.2 Nested Vectored Interrupt Controller (NVIC) Configuration...................................................................................... 69

3.2.1 Interrupt priority levels.................................................................................................................................. 69

3.2.2 Non-maskable interrupt..................................................................................................................................69

3.2.3 Interrupt vector assignments ......................................................................................................................... 70

3.3 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration..........................................................................73

3.3.1 Wake-up sources............................................................................................................................................74

3.4 FPU Configuration........................................................................................................................................................74

3.5 JTAG Controller Configuration....................................................................................................................................75

Chapter 4

Memories and Memory Interfaces

4.1 Flash memory types......................................................................................................................................................77

4.2 Flash Memory Sizes......................................................................................................................................................77

4.3 Flash Security............................................................................................................................................................... 77

4.3.1 Flash Access Control Introduction.................................................................................................................78

4.4 Flash Modes..................................................................................................................................................................78

4.5 Erase All Flash Contents...............................................................................................................................................79

4.6 FTFA_FOPT Register...................................................................................................................................................79

4.7 SRAM sizes.................................................................................................................................................................. 79

4.8 SRAM Arrays............................................................................................................................................................... 79

4.9 SRAM retention in low power modes.......................................................................................................................... 80

4.10 System Register file......................................................................................................................................................80

Chapter 5

Memory Map

5.1 Introduction...................................................................................................................................................................81

5.2 System Memory Map....................................................................................................................................................81

5.3 Peripheral Memory Map...............................................................................................................................................82

5.3.1 Read-after-write sequence and required serialization of memory operations................................................82

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5.3.2 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map.......................................................................................... 83

Chapter 6

Clock Distribution

6.1 Introduction...................................................................................................................................................................87

6.2 High-level device clocking diagram............................................................................................................................. 87

6.2.1 Clock definitions............................................................................................................................................88

6.3 Internal clocking requirements..................................................................................................................................... 89

6.3.1 Clock divider values after reset......................................................................................................................90

6.3.2 VLPR mode clocking.....................................................................................................................................91

6.4 Clock Gating.................................................................................................................................................................91

6.5 Module clocks...............................................................................................................................................................91

6.5.1 NanoEdge clocking........................................................................................................................................93

6.5.2 WDOG clocking............................................................................................................................................ 93

6.5.3 PMC 1-kHz LPO clock..................................................................................................................................94

6.5.4 PORT digital filter clocking...........................................................................................................................94

6.5.5 LPTMR clocking............................................................................................................................................94

6.5.6 FlexCAN clocking......................................................................................................................................... 95

6.5.7 UART clocking..............................................................................................................................................95

6.6 External clocks .............................................................................................................................................................96

Chapter 7

Power Management

7.1 Introduction...................................................................................................................................................................97

7.2 Clocking Modes............................................................................................................................................................97

7.2.1 Partial Stop.....................................................................................................................................................97

7.2.2 DMA Wakeup................................................................................................................................................98

7.2.3 Compute Operation........................................................................................................................................99

7.2.4 Peripheral Doze..............................................................................................................................................100

7.3 Power modes.................................................................................................................................................................101

7.4 Module Operation in Low Power Modes......................................................................................................................102

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7.5 Power modes shutdown sequencing............................................................................................................................. 105

7.6 Clock Gating.................................................................................................................................................................105

7.7 Flash Program Restrictions...........................................................................................................................................106

Chapter 8

Security

8.1 Introduction...................................................................................................................................................................107

8.2 Flash Security............................................................................................................................................................... 107

8.3 Security Interactions with other Modules.....................................................................................................................108

8.3.1 Security Interactions with Debug...................................................................................................................108

Chapter 9

Debug

9.1 Introduction...................................................................................................................................................................109

9.1.1 References......................................................................................................................................................111

9.2 The Debug Port.............................................................................................................................................................111

9.2.1 JTAG-to-SWD change sequence................................................................................................................... 111

9.3 Debug Port Pin Descriptions.........................................................................................................................................112

9.4 JTAG status and control registers.................................................................................................................................112

9.4.1 MDM-AP Control Register............................................................................................................................113

9.4.2 MDM-AP Status Register.............................................................................................................................. 115

9.5 Debug Resets................................................................................................................................................................ 116

9.6 AHB-AP........................................................................................................................................................................116

9.7 ITM............................................................................................................................................................................... 117

9.8 TPIU..............................................................................................................................................................................117

9.9 DWT............................................................................................................................................................................. 118

9.10 Debug in Low Power Modes........................................................................................................................................ 118

9.10.1 Debug Module State in Low Power Modes...................................................................................................119

9.11 Debug & Security......................................................................................................................................................... 119

Chapter 10

Reset and Boot

10.1 Introduction...................................................................................................................................................................121

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10.2 Reset..............................................................................................................................................................................121

10.2.1 Power-on reset (POR).................................................................................................................................... 122

10.2.2 System resets..................................................................................................................................................122

10.2.2.1 External pin reset (PIN)............................................................................................................. 122

10.2.2.2 Low-voltage detect (LVD) reset................................................................................................ 123

10.2.2.3 Computer operating properly (COP) watchdog reset................................................................ 124

10.2.2.4 Low leakage wakeup (LLWU) reset..........................................................................................124

10.2.2.5 Multipurpose clock generator loss-of-clock (LOC) reset.......................................................... 124

10.2.2.6 Software reset (SW)...................................................................................................................125

10.2.2.7 Lockup reset (LOCKUP)........................................................................................................... 125

10.2.2.8 MDM-AP system reset request..................................................................................................125

10.2.3 Debug resets...................................................................................................................................................125

10.2.3.1 JTAG reset................................................................................................................................. 125

10.2.3.2 nTRST reset............................................................................................................................... 126

10.2.3.3 Resetting the Debug subsystem................................................................................................. 126

10.3 Boot...............................................................................................................................................................................127

10.3.1 Boot sources...................................................................................................................................................127

10.3.2 FOPT boot options.........................................................................................................................................127

10.3.3 Boot sequence................................................................................................................................................ 128

Chapter 11

Signal Multiplexing

11.1 Introduction...................................................................................................................................................................131

11.2 Port control and interrupt module features................................................................................................................... 131

11.3 Clock gating..................................................................................................................................................................132

11.4 Signal multiplexing constraints.................................................................................................................................... 133

11.5 MWCT1x23 Signal Multiplexing and Pin Assignments.............................................................................................. 133

11.6 Pinout diagrams............................................................................................................................................................ 136

Chapter 12

Port control and interrupts (PORT)

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12.1 Introduction...................................................................................................................................................................139

12.1.1 Overview........................................................................................................................................................139

12.1.2 Features.......................................................................................................................................................... 139

12.1.3 Modes of operation........................................................................................................................................ 140

12.1.3.1 Run mode................................................................................................................................... 140

12.1.3.2 Wait mode..................................................................................................................................140

12.1.3.3 Stop mode.................................................................................................................................. 140

12.1.3.4 Debug mode............................................................................................................................... 140

12.2 External signal description............................................................................................................................................141

12.3 Detailed signal description............................................................................................................................................141

12.4 Memory map and register definition.............................................................................................................................141

12.4.1

Pin Control Register n (PORTx_PCRn).........................................................................................................148

12.4.2

Global Pin Control Low Register (PORTx_GPCLR)....................................................................................151

12.4.3

Global Pin Control High Register (PORTx_GPCHR)...................................................................................151

12.4.4

Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 152

12.4.5

Digital Filter Enable Register (PORTx_DFER).............................................................................................152

12.4.6

Digital Filter Clock Register (PORTx_DFCR)..............................................................................................153

12.4.7

Digital Filter Width Register (PORTx_DFWR)............................................................................................ 153

12.5 Functional description...................................................................................................................................................154

12.5.1 Pin control......................................................................................................................................................154

12.5.2 Global pin control.......................................................................................................................................... 155

12.5.3 External interrupts..........................................................................................................................................155

12.5.4 Digital filter....................................................................................................................................................156

Chapter 13

System Integration Module (SIM)

13.1 Introduction...................................................................................................................................................................159

13.1.1 Features.......................................................................................................................................................... 159

13.2 Memory map and register definition.............................................................................................................................160

13.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 161

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13.2.2 System Options Register 2 (SIM_SOPT2).................................................................................................... 163

13.2.3 System Options Register 4 (SIM_SOPT4).................................................................................................... 164

13.2.4 System Options Register 5 (SIM_SOPT5).................................................................................................... 167

13.2.5 System Options Register 7 (SIM_SOPT7).................................................................................................... 168

13.2.6 System Options Register 8 (SIM_SOPT8).................................................................................................... 170

13.2.7 System Options Register 9 (SIM_SOPT9).................................................................................................... 173

13.2.8 System Device Identification Register (SIM_SDID).....................................................................................174

13.2.9 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................176

13.2.10 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................178

13.2.11 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................180

13.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)..............................................................................182

13.2.13 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................183

13.2.14 System Clock Divider Register 2 (SIM_CLKDIV2).....................................................................................185

13.2.14 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 185

13.2.15 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 187

13.2.16 Unique Identification Register High (SIM_UIDH)....................................................................................... 187

13.2.17 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................188

13.2.18 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 188

13.2.19 Unique Identification Register Low (SIM_UIDL)........................................................................................ 189

13.2.20 System Clock Divider Register 4 (SIM_CLKDIV4).....................................................................................189

13.2.21 Miscellaneous Control Register 0 (SIM_MISCTRL0)..................................................................................190

13.2.22 Miscellaneous Control Register 1 (SIM_MISCTRL1)..................................................................................192

13.2.23 WDOG Control Register (SIM_WDOGC)....................................................................................................194

13.2.24 Power Control Register (SIM_PWRC)..........................................................................................................196

13.2.25 ADC Channel 6/7 Mux Control Register (SIM_ADCOPT)..........................................................................198

13.3 Functional description...................................................................................................................................................200

Chapter 14

Reset Control Module (RCM)

14.1 Introduction...................................................................................................................................................................201

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14.2 Reset memory map and register descriptions............................................................................................................... 201

14.2.1 System Reset Status Register 0 (RCM_SRS0).............................................................................................. 202

14.2.2 System Reset Status Register 1 (RCM_SRS1).............................................................................................. 203

14.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................ 205

14.2.4 Reset Pin Filter Width register (RCM_RPFW)............................................................................................. 206

14.2.5 Sticky System Reset Status Register 0 (RCM_SSRS0).................................................................................207

14.2.6 Sticky System Reset Status Register 1 (RCM_SSRS1).................................................................................208

Chapter 15

System Mode Controller (SMC)

15.1 Introduction...................................................................................................................................................................211

15.2 Modes of operation....................................................................................................................................................... 211

15.3 Memory map and register descriptions.........................................................................................................................213

15.3.1 Power Mode Protection register (SMC_PMPROT).......................................................................................214

15.3.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................215

15.3.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................217

15.3.4 Power Mode Status register (SMC_PMSTAT)............................................................................................. 218

15.4 Functional description...................................................................................................................................................219

15.4.1 Power mode transitions..................................................................................................................................219

15.4.2 Power mode entry/exit sequencing................................................................................................................ 222

15.4.2.1 Stop mode entry sequence..........................................................................................................222

15.4.2.2 Stop mode exit sequence............................................................................................................222

15.4.2.3 Aborted stop mode entry............................................................................................................222

15.4.2.4 Transition to wait modes............................................................................................................223

15.4.2.5 Transition from stop modes to Debug mode..............................................................................223

15.4.3 Run modes......................................................................................................................................................223

15.4.3.1 RUN mode................................................................................................................................. 223

15.4.3.2 Very-Low Power Run (VLPR) mode........................................................................................ 224

15.4.3.3 High Speed Run (HSRUN) mode.............................................................................................. 224

15.4.4 Wait modes.................................................................................................................................................... 225

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15.4.4.1 WAIT mode............................................................................................................................... 225

15.4.4.2 Very-Low-Power Wait (VLPW) mode......................................................................................225

15.4.5 Stop modes.....................................................................................................................................................226

15.4.5.1 STOP mode................................................................................................................................226

15.4.5.2 Very-Low-Power Stop (VLPS) mode........................................................................................227

15.4.5.3 Very-Low-Leakage Stop (VLLSx) modes.................................................................................227

15.4.6 Debug in low power modes........................................................................................................................... 228

Chapter 16

Miscellaneous Control Module (MCM)

16.1 Introduction...................................................................................................................................................................231

16.1.1 Features.......................................................................................................................................................... 231

16.2 Memory map/register descriptions............................................................................................................................... 231

16.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................232

16.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 232

16.2.3 Control Register (MCM_CR)........................................................................................................................ 233

16.2.4 Interrupt Status and Control Register (MCM_ISCR).................................................................................... 235

16.2.5 Compute Operation Control Register (MCM_CPO)..................................................................................... 237

16.3 Functional description...................................................................................................................................................238

16.3.1 Interrupts........................................................................................................................................................ 238

16.3.1.1 Non-maskable interrupt..............................................................................................................238

16.3.1.2 Normal interrupt.........................................................................................................................238

16.4 Functional description...................................................................................................................................................239

16.4.1 Interrupts........................................................................................................................................................ 239

16.4.1.1 Determining source of the interrupt...........................................................................................239

Chapter 17

Power Management Controller (PMC)

17.1 Introduction...................................................................................................................................................................241

17.2 Features.........................................................................................................................................................................241

17.3 Low-voltage detect (LVD) system................................................................................................................................241

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17.3.1 LVD reset operation.......................................................................................................................................242

17.3.2 LVD interrupt operation.................................................................................................................................242

17.3.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 242

17.4 I/O retention..................................................................................................................................................................243

17.5 Memory map and register descriptions.........................................................................................................................243

17.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1).......................................................... 244

17.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2).......................................................... 245

17.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................246

Chapter 18

Low-Leakage Wakeup Unit (LLWU)

18.1 Chip-specific LLWU information.................................................................................................................................249

18.2 Introduction...................................................................................................................................................................250

18.2.1 Features.......................................................................................................................................................... 250

18.2.2 Modes of operation........................................................................................................................................ 250

18.2.2.1 VLLS modes.............................................................................................................................. 251

18.2.2.2 Non-low leakage modes.............................................................................................................251

18.2.2.3 Debug mode............................................................................................................................... 251

18.2.3 Block diagram................................................................................................................................................251

18.3 LLWU signal descriptions............................................................................................................................................ 252

18.4 Memory map/register definition................................................................................................................................... 253

18.4.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................254

18.4.2 LLWU Pin Enable 2 register (LLWU_PE2)..................................................................................................255

18.4.3 LLWU Pin Enable 3 register (LLWU_PE3)..................................................................................................256

18.4.4 LLWU Pin Enable 4 register (LLWU_PE4)..................................................................................................257

18.4.5 LLWU Pin Enable 5 register (LLWU_PE5)..................................................................................................259

18.4.6 LLWU Pin Enable 6 register (LLWU_PE6)..................................................................................................260

18.4.7 LLWU Pin Enable 7 register (LLWU_PE7)..................................................................................................261

18.4.8 LLWU Pin Enable 8 register (LLWU_PE8)..................................................................................................262

18.4.9 LLWU Module Enable register (LLWU_ME).............................................................................................. 263

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18.4.10 LLWU Pin Flag 1 register (LLWU_PF1)......................................................................................................265

18.4.11 LLWU Pin Flag 2 register (LLWU_PF2)......................................................................................................266

18.4.12 LLWU Pin Flag 3 register (LLWU_PF3)......................................................................................................268

18.4.13 LLWU Pin Flag 4 register (LLWU_PF4)......................................................................................................270

18.4.14 LLWU Module Flag 5 register (LLWU_MF5)..............................................................................................272

18.4.15 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................ 273

18.4.16 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................ 274

18.5 Functional description...................................................................................................................................................275

18.5.1 VLLS modes.................................................................................................................................................. 276

18.5.2 Initialization................................................................................................................................................... 276

Chapter 19

Crossbar Switch Lite (AXBS-Lite)

19.1 Crossbar-Light Switch Configuration...........................................................................................................................279

19.1.1 Crossbar Switch Master Assignments............................................................................................................279

19.1.2 Crossbar Switch Slave Assignments..............................................................................................................280

19.2 Introduction...................................................................................................................................................................280

19.2.1 Features.......................................................................................................................................................... 280

19.3 Memory Map / Register Definition...............................................................................................................................281

19.4 Functional Description..................................................................................................................................................281

19.4.1 General operation...........................................................................................................................................281

19.4.2 Arbitration......................................................................................................................................................282

19.4.2.1 Arbitration during undefined length bursts................................................................................282

19.4.2.2 Fixed-priority operation............................................................................................................. 282

19.4.2.3 Round-robin priority operation.................................................................................................. 283

19.5 Initialization/application information........................................................................................................................... 283

Chapter 20

Peripheral Bridge (AIPS-Lite)

20.1 Number of peripheral bridges....................................................................................................................................... 285

20.2 Memory map.................................................................................................................................................................285

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20.3 PACR registers..............................................................................................................................................................285

20.4 AIPS_Lite PACRE-P register reset values................................................................................................................... 285

20.5 Introduction...................................................................................................................................................................286

20.5.1 Features.......................................................................................................................................................... 286

20.5.2 General operation...........................................................................................................................................286

20.6 Memory map/register definition................................................................................................................................... 286

20.6.1 Master Privilege Register A (AIPS_MPRA)................................................................................................. 287

20.6.2

Peripheral Access Control Register (AIPS_PACRn).....................................................................................290

20.6.3

Peripheral Access Control Register (AIPS_PACRn).....................................................................................295

20.7 Functional description...................................................................................................................................................299

20.7.1 Access support............................................................................................................................................... 300

Chapter 21

Direct memory access multiplexer (DMAMUX)

21.1 Chip-specific DMAMUX information......................................................................................................................... 301

21.1.1 DMA MUX request sources.......................................................................................................................... 301

21.1.2 DMA transfers via PIT trigger.......................................................................................................................303

21.2 Introduction...................................................................................................................................................................303

21.2.1 Overview........................................................................................................................................................303

21.2.2 Features.......................................................................................................................................................... 304

21.2.3 Modes of operation........................................................................................................................................ 304

21.3 External signal description............................................................................................................................................305

21.4 Memory map/register definition................................................................................................................................... 305

21.4.1

Channel Configuration register (DMAMUX_CHCFGn).............................................................................. 306

21.5 Functional description...................................................................................................................................................307

21.5.1 DMA channels with periodic triggering capability........................................................................................307

21.5.2 DMA channels with no triggering capability.................................................................................................309

21.5.3 Always-enabled DMA sources...................................................................................................................... 310

21.6 Initialization/application information........................................................................................................................... 311

21.6.1 Reset...............................................................................................................................................................311

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21.6.2 Enabling and configuring sources..................................................................................................................311

Chapter 22

Direct Memory Access Controller (eDMA)

22.1 Introduction...................................................................................................................................................................315

22.1.1 eDMA system block diagram........................................................................................................................ 315

22.1.2 Block parts..................................................................................................................................................... 316

22.1.3 Features.......................................................................................................................................................... 317

22.2 Modes of operation....................................................................................................................................................... 318

22.3 Memory map/register definition................................................................................................................................... 319

22.3.1 TCD memory................................................................................................................................................. 319

22.3.2 TCD initialization.......................................................................................................................................... 319

22.3.3 TCD structure.................................................................................................................................................319

22.3.4 Reserved memory and bit fields.....................................................................................................................320

22.3.5 Control Register (DMA_CR).........................................................................................................................331

22.3.6 Error Status Register (DMA_ES).................................................................................................................. 334

22.3.7 Enable Request Register (DMA_ERQ)......................................................................................................... 336

22.3.8 Enable Error Interrupt Register (DMA_EEI).................................................................................................338

22.3.9 Clear Enable Error Interrupt Register (DMA_CEEI).................................................................................... 341

22.3.10 Set Enable Error Interrupt Register (DMA_SEEI)........................................................................................ 342

22.3.11 Clear Enable Request Register (DMA_CERQ).............................................................................................342

22.3.12 Set Enable Request Register (DMA_SERQ).................................................................................................343

22.3.13 Clear DONE Status Bit Register (DMA_CDNE)..........................................................................................344

22.3.14 Set START Bit Register (DMA_SSRT)........................................................................................................ 345

22.3.15 Clear Error Register (DMA_CERR)..............................................................................................................346

22.3.16 Clear Interrupt Request Register (DMA_CINT)........................................................................................... 347

22.3.17 Interrupt Request Register (DMA_INT)........................................................................................................348

22.3.18 Error Register (DMA_ERR).......................................................................................................................... 350

22.3.19 Hardware Request Status Register (DMA_HRS).......................................................................................... 353

22.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS)...................................................................356

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22.3.21

Channel n Priority Register (DMA_DCHPRIn)............................................................................................ 358

22.3.22

TCD Source Address (DMA_TCDn_SADDR).............................................................................................359

22.3.23

TCD Signed Source Address Offset (DMA_TCDn_SOFF)..........................................................................359

22.3.24

TCD Transfer Attributes (DMA_TCDn_ATTR)...........................................................................................360

22.3.25

TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMA_TCDn_NBYTES_MLNO)................... 361

22.3.26 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)

(DMA_TCDn_NBYTES_MLOFFNO).........................................................................................................362

22.3.27 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)

(DMA_TCDn_NBYTES_MLOFFYES)....................................................................................................... 363

22.3.28

TCD Last Source Address Adjustment (DMA_TCDn_SLAST)...................................................................364

22.3.29

TCD Destination Address (DMA_TCDn_DADDR).....................................................................................365

22.3.30

TCD Signed Destination Address Offset (DMA_TCDn_DOFF)..................................................................365

22.3.31 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_CITER_ELINKYES).............................................................................................................366

22.3.32 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_CITER_ELINKNO).............................................................................................................. 367

22.3.33

TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA)............ 368

22.3.34

TCD Control and Status (DMA_TCDn_CSR).............................................................................................. 369

22.3.35 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)

(DMA_TCDn_BITER_ELINKYES).............................................................................................................371

22.3.36 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)

(DMA_TCDn_BITER_ELINKNO).............................................................................................................. 372

22.4 Functional description...................................................................................................................................................373

22.4.1 eDMA basic data flow................................................................................................................................... 373

22.4.2 Fault reporting and handling..........................................................................................................................376

22.4.3 Channel preemption....................................................................................................................................... 379

22.4.4 Performance................................................................................................................................................... 379

22.4.4.1 Peak transfer rates...................................................................................................................... 379

22.4.4.2 Peak request rates.......................................................................................................................380

22.4.4.3 eDMA performance example.....................................................................................................382

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22.5 Initialization/application information........................................................................................................................... 383

22.5.1 eDMA initialization....................................................................................................................................... 383

22.5.2 Programming errors....................................................................................................................................... 385

22.5.3 Arbitration mode considerations....................................................................................................................386

22.5.3.1 Fixed channel arbitration........................................................................................................... 386

22.5.3.2 Round-robin channel arbitration................................................................................................ 386

22.5.4 Performing DMA transfers............................................................................................................................ 386

22.5.4.1 Single request.............................................................................................................................386

22.5.4.2 Multiple requests........................................................................................................................388

22.5.4.3 Using the modulo feature...........................................................................................................390

22.5.5 Monitoring transfer descriptor status............................................................................................................. 390

22.5.5.1 Testing for minor loop completion............................................................................................ 390

22.5.5.2 Reading the transfer descriptors of active channels...................................................................391

22.5.5.3 Checking channel preemption status..........................................................................................392

22.5.6 Channel Linking.............................................................................................................................................392

22.5.7 Dynamic programming.................................................................................................................................. 393

22.5.7.1 Dynamically changing the channel priority...............................................................................393

22.5.7.2 Dynamic channel linking........................................................................................................... 394

22.5.7.3 Dynamic scatter/gather.............................................................................................................. 394

22.5.8 Suspend/resume a DMA channel with active hardware service requests......................................................397

22.5.8.1 Suspend an active DMA channel...............................................................................................397

22.5.8.2 Resume a DMA channel............................................................................................................ 397

Chapter 23

External Watchdog Monitor (EWM)

23.1 Chip-specific EWM information.................................................................................................................................. 399

23.1.1 EWM clocks...................................................................................................................................................399

23.1.2 EWM low-power modes................................................................................................................................ 399

23.1.3 EWM_OUT pin state in low power modes....................................................................................................399

23.2 Introduction...................................................................................................................................................................400

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23.2.1 Features.......................................................................................................................................................... 400

23.2.2 Modes of Operation....................................................................................................................................... 401

23.2.2.1 Stop Mode..................................................................................................................................401

23.2.2.2 Debug Mode...............................................................................................................................401

23.2.3 Block Diagram............................................................................................................................................... 401

23.3 EWM Signal Descriptions............................................................................................................................................ 402

23.4 Memory Map/Register Definition.................................................................................................................................403

23.4.1 Control Register (EWM_CTRL)................................................................................................................... 403

23.4.2 Service Register (EWM_SERV)....................................................................................................................404

23.4.3 Compare Low Register (EWM_CMPL)........................................................................................................404

23.4.4 Compare High Register (EWM_CMPH).......................................................................................................405

23.5 Functional Description..................................................................................................................................................405

23.5.1 The EWM_out Signal.................................................................................................................................... 406

23.5.2 The EWM_in Signal...................................................................................................................................... 406

23.5.3 EWM Counter................................................................................................................................................407

23.5.4 EWM Compare Registers.............................................................................................................................. 407

23.5.5 EWM Refresh Mechanism.............................................................................................................................408

23.5.6 EWM Interrupt...............................................................................................................................................408

Chapter 24

Watchdog Timer (WDOG)

24.1 Chip-specific WDOG information................................................................................................................................409

24.1.1 WDOG clocks................................................................................................................................................409

24.1.2 WDOG low-power modes............................................................................................................................. 409

24.2 Introduction...................................................................................................................................................................410

24.3 Features.........................................................................................................................................................................410

24.4 Functional overview......................................................................................................................................................411

24.4.1 Unlocking and updating the watchdog...........................................................................................................413

24.4.2 Watchdog configuration time (WCT)............................................................................................................414

24.4.3 Refreshing the watchdog................................................................................................................................415

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24.4.4 Windowed mode of operation........................................................................................................................415

24.4.5 Watchdog disabled mode of operation...........................................................................................................415

24.4.6 Low-power modes of operation..................................................................................................................... 416

24.4.7 Debug modes of operation............................................................................................................................. 416

24.5 Testing the watchdog.................................................................................................................................................... 417

24.5.1 Quick test....................................................................................................................................................... 417

24.5.2 Byte test..........................................................................................................................................................418

24.6 Backup reset generator..................................................................................................................................................419

24.7 Generated resets and interrupts.....................................................................................................................................419

24.8 Memory map and register definition.............................................................................................................................420

24.8.1 Watchdog Status and Control Register High (WDOG_STCTRLH)............................................................. 421

24.8.2 Watchdog Status and Control Register Low (WDOG_STCTRLL).............................................................. 422

24.8.3 Watchdog Time-out Value Register High (WDOG_TOVALH)...................................................................423

24.8.4 Watchdog Time-out Value Register Low (WDOG_TOVALL)....................................................................423

24.8.5 Watchdog Window Register High (WDOG_WINH).................................................................................... 424

24.8.6 Watchdog Window Register Low (WDOG_WINL)..................................................................................... 424

24.8.7 Watchdog Refresh register (WDOG_REFRESH)......................................................................................... 425

24.8.8 Watchdog Unlock register (WDOG_UNLOCK)...........................................................................................425

24.8.9 Watchdog Timer Output Register High (WDOG_TMROUTH)................................................................... 425

24.8.10 Watchdog Timer Output Register Low (WDOG_TMROUTL).................................................................... 426

24.8.11 Watchdog Reset Count register (WDOG_RSTCNT).................................................................................... 426

24.8.12 Watchdog Prescaler register (WDOG_PRESC)............................................................................................ 426

24.9 Watchdog operation with 8-bit access.......................................................................................................................... 427

24.9.1 General guideline........................................................................................................................................... 427

24.9.2 Refresh and unlock operations with 8-bit access...........................................................................................427

24.10 Restrictions on watchdog operation..............................................................................................................................428

Chapter 25

Inter-Peripheral Crossbar Switch A (XBARA)

25.1 Chip-specific XBARA information.............................................................................................................................. 431

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25.1.1 XBARA input signal assignment...................................................................................................................431

25.1.2 XBARA signal output assignment.................................................................................................................432

25.2 Introduction...................................................................................................................................................................434

25.2.1 Overview........................................................................................................................................................434

25.2.2 Features.......................................................................................................................................................... 435

25.2.3 Modes of Operation....................................................................................................................................... 435

25.2.4 Block Diagram............................................................................................................................................... 435

25.3 Signal Descriptions.......................................................................................................................................................436

25.3.1 XBAR_OUT[0:NUM_OUT-1] - MUX Outputs........................................................................................... 437

25.3.2 XBAR_IN[0:NUM_IN-1] - MUX Inputs......................................................................................................437

25.3.3 DMA_REQ[n] - DMA Request Output(s).....................................................................................................437

25.3.4 DMA_ACK[n] - DMA Acknowledge Input(s)..............................................................................................437

25.3.5 INT_REQ[n] - Interrupt Request Output(s)...................................................................................................437

25.4 Memory Map and Register Descriptions...................................................................................................................... 437

25.4.1 Crossbar A Select Register 0 (XBARA_SEL0).............................................................................................439

25.4.2 Crossbar A Select Register 1 (XBARA_SEL1).............................................................................................439

25.4.3 Crossbar A Select Register 2 (XBARA_SEL2).............................................................................................440

25.4.4 Crossbar A Select Register 3 (XBARA_SEL3).............................................................................................440

25.4.5 Crossbar A Select Register 4 (XBARA_SEL4).............................................................................................441

25.4.6 Crossbar A Select Register 5 (XBARA_SEL5).............................................................................................441

25.4.7 Crossbar A Select Register 6 (XBARA_SEL6).............................................................................................442

25.4.8 Crossbar A Select Register 7 (XBARA_SEL7).............................................................................................442

25.4.9 Crossbar A Select Register 8 (XBARA_SEL8).............................................................................................443

25.4.10 Crossbar A Select Register 9 (XBARA_SEL9).............................................................................................443

25.4.11 Crossbar A Select Register 10 (XBARA_SEL10).........................................................................................444

25.4.12 Crossbar A Select Register 11 (XBARA_SEL11).........................................................................................444

25.4.13 Crossbar A Select Register 12 (XBARA_SEL12).........................................................................................445

25.4.14 Crossbar A Select Register 13 (XBARA_SEL13).........................................................................................445

25.4.15 Crossbar A Select Register 14 (XBARA_SEL14).........................................................................................446

MWCT1x23 Reference Manual, Rev. 0, 12/2019

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NXP MWCT1x23 Reference guide

NXP MWCT1x23 Reference guide

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