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NXP MWCT2xx3A Reference guide

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MWCT2xx3A Reference Manual
Supports MWCT2013A, MWCT20C3A and MWCT22C3A
Document Number: MWCT2XX3ARM
Rev. 0, 07/2020
MWCT2xx3A Reference Manual, Rev. 0, 07/2020
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................53
1.1.1 Purpose...........................................................................................................................................................53
1.1.2 Audience........................................................................................................................................................ 53
1.2 Conventions.................................................................................................................................................................. 53
1.2.1 Numbering systems........................................................................................................................................53
1.2.2 Typographic notation..................................................................................................................................... 54
1.2.3 Special terms..................................................................................................................................................54
Chapter 2
Introduction
2.1 Target Applications.......................................................................................................................................................55
2.2 System Block Diagram................................................................................................................................................. 55
2.3 Product Family..............................................................................................................................................................57
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................59
3.2 Digital Signal Controller (DSC) Core Configuration...................................................................................................59
3.3 System modules............................................................................................................................................................ 60
3.3.1 System Integration Module (SIM) Configuration..........................................................................................60
3.3.2 MCM Configuration...................................................................................................................................... 61
3.3.3 Inter-Peripheral Crossbar Switch (XBAR) Configuration.............................................................................62
3.3.3.1 Number of inputs and outputs....................................................................................................62
3.3.3.2 XBARA Inputs...........................................................................................................................62
3.3.3.3 XBARA Outputs........................................................................................................................64
3.3.4 Interrupt Controller (INTC) Configuration....................................................................................................66
3.3.4.1 Reset/Interrupt Vector Table......................................................................................................66
3.3.5 DMA Controller Configuration..................................................................................................................... 76
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3.3.5.1 eDMA and DMAMUX.............................................................................................................. 77
3.3.6 Power Management Controller (PMC) Configuration...................................................................................80
3.4 Clock Modules..............................................................................................................................................................81
3.4.1 On-Chip Clock Synthesis (OCCS) Configuration......................................................................................... 81
3.5 Memories and Memory Interfaces................................................................................................................................81
3.5.1 Flash Memory Controller (FMC) Configuration........................................................................................... 81
3.5.2 Flash Memory Configuration.........................................................................................................................82
3.5.2.1 Flash memory types and terminology........................................................................................83
3.5.2.2 FTFE_FOPT Register................................................................................................................ 83
3.6 Security and Integrity....................................................................................................................................................83
3.6.1 Computer Operating Properly (COP) Module Configuration........................................................................83
3.6.1.1 WCOP low power clocks...........................................................................................................84
3.6.2 External Watchdog Monitor (EWM) Configuration......................................................................................84
3.6.2.1 EWM low power clocks.............................................................................................................85
3.6.2.2 EWM_OUT pin state in Low Power Modes..............................................................................85
3.6.3 Cyclic Redundancy Check (CRC) Configuration..........................................................................................86
3.7 Analog...........................................................................................................................................................................86
3.7.1 Cyclic Analog-to-Digital Converter (ADC) Configuration...........................................................................86
3.7.1.1 Cyclic ADC Instantiation...........................................................................................................87
3.7.1.2 Cyclic ADC SYNC Signal Connections....................................................................................87
3.7.1.3 Cyclic ADC and PWM Connections......................................................................................... 87
3.7.2 Comparator (CMP) Configuration.................................................................................................................88
3.7.2.1 Comparator Channel Assignments.............................................................................................88
3.7.2.2 Comparator Voltage References................................................................................................ 89
3.7.3 12-bit Digital-to-Analog Converter (DAC) Configuration............................................................................89
3.8 Timers and PWM..........................................................................................................................................................90
3.8.1 PWM Configuration.......................................................................................................................................90
3.8.1.1 PWM auxiliary signals and analog inputs..................................................................................91
3.8.2 PIT Configuration.......................................................................................................................................... 91
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3.8.2.1 PIT low power clocks................................................................................................................ 92
3.8.2.2 PIT master/slave selection......................................................................................................... 92
3.8.3 TMR Configuration........................................................................................................................................93
3.9 Communication interfaces............................................................................................................................................ 93
3.9.1 CAN Configuration........................................................................................................................................93
3.9.1.1 FlexCAN glitch filter................................................................................................................. 94
3.9.1.2 FlexCAN3 Supervisor Mode..................................................................................................... 94
3.9.2 Serial Peripheral Interface (SPI) Configuration.............................................................................................95
3.9.3 Inter-Integrated Circuit (I2C) Configuration................................................................................................. 95
3.9.3.1 I2C module address matching to wake the device from stop mode...........................................96
3.9.4 SCI Configuration..........................................................................................................................................97
3.10 Human-machine interfaces (HMI)................................................................................................................................97
3.10.1 GPIO Configuration.......................................................................................................................................97
3.10.1.1 GPIO Port D[4:0] configuration................................................................................................ 98
3.10.1.2 GPIO unbonded pads................................................................................................................. 99
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................101
4.2 Program/Data Memory Maps....................................................................................................................................... 101
4.3 Core and System Peripheral Memory Map...................................................................................................................103
4.4 Slave Peripheral Memory Map..................................................................................................................................... 103
Chapter 5
Clock Distribution
5.1 Overview.......................................................................................................................................................................107
5.2 Clock Distribution.........................................................................................................................................................107
Chapter 6
ROM Bootloader
6.1 Chip-specific Information.............................................................................................................................................111
6.1.1 Bootloader Peripheral Pinmux.......................................................................................................................111
6.1.2 Bootloader Memory Access...........................................................................................................................112
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6.2 Introduction...................................................................................................................................................................112
6.3 Functional Description..................................................................................................................................................114
6.3.1 The Bootloader Configuration Area (BCA)...................................................................................................114
6.3.2 Start-up Process..............................................................................................................................................116
6.3.3 Bootloader Protocol....................................................................................................................................... 119
6.3.3.1 Command with no data phase.................................................................................................... 119
6.3.3.2 Command with incoming data phase.........................................................................................120
6.3.3.3 Command with outgoing data phase..........................................................................................121
6.3.4 Bootloader Packet Types............................................................................................................................... 123
6.3.4.1 Ping packet.................................................................................................................................123
6.3.4.2 Ping Response Packet................................................................................................................ 124
6.3.4.3 Framing Packet.......................................................................................................................... 124
6.3.4.4 Command packet........................................................................................................................126
6.3.4.5 Data packet.................................................................................................................................128
6.3.4.6 Response packet.........................................................................................................................128
6.3.5 Bootloader Command API.............................................................................................................................130
6.3.5.1 ReliableUpdate command..........................................................................................................131
6.3.5.2 Execute command......................................................................................................................132
6.3.5.3 Reset command..........................................................................................................................133
6.3.5.4 GetProperty command............................................................................................................... 134
6.3.5.5 FlashEraseAll command............................................................................................................ 136
6.3.5.6 FlashEraseRegion command......................................................................................................137
6.3.5.7 FlashEraseAllUnsecure command............................................................................................. 139
6.3.5.8 FlashProgramOnce command....................................................................................................140
6.3.5.9 FlashReadOnce command..........................................................................................................142
6.3.5.10 FlashReadResource command................................................................................................... 144
6.3.5.11 FlashSecurityDisable command.................................................................................................146
6.3.5.12 WriteMemory command............................................................................................................148
6.3.5.13 ReadMemory command.............................................................................................................150
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6.3.6 Bootloader Exit state......................................................................................................................................152
6.4 Peripherals Supported................................................................................................................................................... 152
6.4.1 I2C Peripheral................................................................................................................................................ 152
6.4.2 UART Peripheral........................................................................................................................................... 154
6.4.3 FlexCAN Peripheral.......................................................................................................................................157
6.5 Get/SetProperty Command Properties..........................................................................................................................159
6.5.1 Property Definitions.......................................................................................................................................159
6.5.1.1 CurrentVersion Property............................................................................................................160
6.5.1.2 AvailablePeripherals Property................................................................................................... 160
6.5.1.3 AvailableCommands Property................................................................................................... 160
6.6 Verifying the application in flash using CRC-32......................................................................................................... 161
6.7 Bootloader Status Error Codes......................................................................................................................................162
6.8 ROM flash driver API...................................................................................................................................................163
6.8.1 Introduction....................................................................................................................................................163
6.8.2 Struct of FlashDriverInterface....................................................................................................................... 163
6.8.3 Details of structs.............................................................................................................................................164
6.8.4 Flash Driver APIs...........................................................................................................................................166
6.8.5 Integrate flash driver API to user project.......................................................................................................167
Chapter 7
Power Management
7.1 Overview.......................................................................................................................................................................169
7.2 Architecture...................................................................................................................................................................169
7.3 External Supplies and Regulation.................................................................................................................................170
7.4 User Power Management Methods...............................................................................................................................170
Chapter 8
Signal Multiplexing and Signal Descriptions
8.1 Signal Multiplexing and Pin Assignments....................................................................................................................173
8.2 Pinout diagrams............................................................................................................................................................ 176
Chapter 9
Memory Resource Protection (MRP)
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9.1 Overview.......................................................................................................................................................................179
9.2 Features.........................................................................................................................................................................180
9.3 Operation.......................................................................................................................................................................180
9.4 Programming Model Overview.................................................................................................................................... 184
9.5 Memory Resource Protection Restrictions................................................................................................................... 184
9.6 Base Address Setup.......................................................................................................................................................184
9.7 Programming Example................................................................................................................................................. 186
Chapter 10
Miscellaneous Control Module (MCM)
10.1 Introduction...................................................................................................................................................................189
10.1.1 Features.......................................................................................................................................................... 189
10.2 Memory Map/Register Descriptions.............................................................................................................................190
10.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)....................................................................191
10.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)................................................................ 191
10.2.3 Core control register (MCM_CPCR).............................................................................................................192
10.2.4 Core fault address register (MCM_CFADR).................................................................................................194
10.2.5 Core fault attributes register (MCM_CFATR).............................................................................................. 195
10.2.6 Core fault location register (MCM_CFLOC)................................................................................................ 196
10.2.7 Core fault interrupt enable register (MCM_CFIER)......................................................................................196
10.2.8 MCM interrupt status register (MCM_CFISR)............................................................................................. 197
10.2.9 Core fault data register (MCM_CFDTR).......................................................................................................198
10.2.10 Resource Protection Control Register (MCM_RPCR).................................................................................. 198
10.2.11 User Flash Base Address Register (MCM_UFLASHBAR)..........................................................................199
10.2.12 User Program RAM Base Address Register (MCM_UPRAMBAR)............................................................ 200
10.2.13 User Boot ROM Base Address Register (MCM_UBROMBAR)..................................................................200
10.2.14 Resource Protection Other Stack Pointer (MCM_SRPOSP).........................................................................201
10.2.15 Memory Protection Illegal PC (MCM_SRPIPC)...........................................................................................201
10.2.16 Resource Protection Misaligned PC (MCM_SRPMPC)............................................................................... 203
10.3 Functional Description..................................................................................................................................................204
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10.3.1 Core Data Fault Recovery Registers..............................................................................................................204
Chapter 11
System Integration Module (SIM)
11.1 Introduction...................................................................................................................................................................205
11.1.1 Overview........................................................................................................................................................205
11.1.2 Features.......................................................................................................................................................... 205
11.1.3 Modes of Operation....................................................................................................................................... 206
11.2 Memory Map and Register Descriptions...................................................................................................................... 207
11.2.1 Control Register (SIM_CTRL)...................................................................................................................... 208
11.2.2 Reset Status Register (SIM_RSTAT)............................................................................................................ 211
11.2.3 Software Control Register (SIM_SCR0)....................................................................................................... 212
11.2.4 Software Control Register (SIM_SCR1)....................................................................................................... 212
11.2.5 Software Control Register (SIM_SCR2)....................................................................................................... 213
11.2.6 Software Control Register (SIM_SCR3)....................................................................................................... 213
11.2.7 Most Significant Half of JTAG ID (SIM_MSHID).......................................................................................214
11.2.8 Least Significant Half of JTAG ID (SIM_LSHID)....................................................................................... 215
11.2.9 Power Control Register (SIM_PWR)............................................................................................................ 216
11.2.10 Clock Output Select Register (SIM_CLKOUT)............................................................................................217
11.2.11 Peripheral Clock Rate Register (SIM_PCR)..................................................................................................219
11.2.12 Peripheral Clock Enable Register 0 (SIM_PCE0)......................................................................................... 220
11.2.13 Peripheral Clock Enable Register 1 (SIM_PCE1)......................................................................................... 222
11.2.14 Peripheral Clock Enable Register 2 (SIM_PCE2)......................................................................................... 224
11.2.15 Peripheral Clock Enable Register 3 (SIM_PCE3)......................................................................................... 226
11.2.16 Peripheral Clock STOP Disable Register 0 (SIM_SD0)............................................................................... 227
11.2.17 Peripheral Clock STOP Disable Register 1 (SIM_SD1)............................................................................... 230
11.2.18 Peripheral Clock STOP Disable Register 2 (SIM_SD2)............................................................................... 232
11.2.19 Peripheral Clock STOP Disable Register 3 (SIM_SD3)............................................................................... 234
11.2.20 I/O Short Address Location Register (SIM_IOSAHI)...................................................................................236
11.2.21 I/O Short Address Location Register (SIM_IOSALO)..................................................................................237
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11.2.22 Protection Register (SIM_PROT)..................................................................................................................238
11.2.23 GPIOA LSBs Peripheral Select Register (SIM_GPSAL)..............................................................................240
11.2.24 GPIOA MSBs Peripheral Select Register (SIM_GPSAH)............................................................................241
11.2.25 GPIOB LSBs Peripheral Select Register (SIM_GPSBL)..............................................................................242
11.2.26 GPIOB MSBs Peripheral Select Register (SIM_GPSBH)............................................................................ 242
11.2.27 GPIOC LSBs Peripheral Select Register (SIM_GPSCL)..............................................................................243
11.2.28 GPIOC MSBs Peripheral Select Register (SIM_GPSCH)............................................................................ 244
11.2.29 GPIOD LSBs Peripheral Select Register (SIM_GPSDL)..............................................................................245
11.2.30 GPIOE LSBs Peripheral Select Register (SIM_GPSEL).............................................................................. 246
11.2.31 GPIOE MSBs Peripheral Select Register (SIM_GPSEH).............................................................................247
11.2.32 GPIOF LSBs Peripheral Select Register (SIM_GPSFL)...............................................................................248
11.2.33 GPIOF MSBs Peripheral Select Register (SIM_GPSFH)............................................................................. 249
11.2.34 GPIOG LSBs Peripheral Select Register (SIM_GPSGL)..............................................................................251
11.2.35 GPIOG MSBs Peripheral Select Register (SIM_GPSGH)............................................................................252
11.2.36 Internal Peripheral Select Register 0 (SIM_IPS0)......................................................................................... 253
11.2.37 Miscellaneous Register 0 (SIM_MISC0).......................................................................................................256
11.2.38 Peripheral Software Reset Register 0 (SIM_PSWR0)...................................................................................257
11.2.39 Peripheral Software Reset Register 1 (SIM_PSWR1)...................................................................................258
11.2.40 Peripheral Software Reset Register 2 (SIM_PSWR2)...................................................................................260
11.2.41 Peripheral Software Reset Register 3 (SIM_PSWR3)...................................................................................261
11.2.42 Power Mode Register (SIM_PWRMODE)....................................................................................................262
11.2.43 Non-Volatile Memory Option Register 6 (Low) (SIM_NVMOPT6_LOW).................................................263
11.2.44 PWM Select Register (SIM_PWM_SEL)......................................................................................................264
11.2.45 ADC and TMR Select Register (SIM_ADC_TMR_SEL).............................................................................266
11.2.46 Boot Mode Override Register (SIM_BOOT_MODE_OVERRIDE)............................................................ 267
11.3 Functional Description..................................................................................................................................................268
11.3.1 Clock Generation Overview...........................................................................................................................268
11.3.2 Power-Down Modes Overview......................................................................................................................268
11.3.3 STOP and WAIT Mode Disable Function.....................................................................................................270
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11.4 Resets............................................................................................................................................................................271
11.5 Clocks........................................................................................................................................................................... 271
11.6 Interrupts.......................................................................................................................................................................271
Chapter 12
Interrupt Controller (INTC)
12.1 Introduction...................................................................................................................................................................273
12.1.1 References......................................................................................................................................................273
12.1.2 Features.......................................................................................................................................................... 273
12.1.3 Modes of Operation....................................................................................................................................... 273
12.1.4 Block Diagram............................................................................................................................................... 274
12.2 Memory Map and Registers..........................................................................................................................................275
12.2.1 Interrupt Priority Register 0 (INTC_IPR0)....................................................................................................276
12.2.2 Interrupt Priority Register 1 (INTC_IPR1)....................................................................................................277
12.2.3 Interrupt Priority Register 2 (INTC_IPR2)....................................................................................................279
12.2.4 Interrupt Priority Register 3 (INTC_IPR3)....................................................................................................280
12.2.5 Interrupt Priority Register 4 (INTC_IPR4)....................................................................................................282
12.2.6 Interrupt Priority Register 5 (INTC_IPR5)....................................................................................................284
12.2.7 Interrupt Priority Register 6 (INTC_IPR6)....................................................................................................285
12.2.8 Interrupt Priority Register 7 (INTC_IPR7)....................................................................................................287
12.2.9 Interrupt Priority Register 8 (INTC_IPR8)....................................................................................................288
12.2.10 Interrupt Priority Register 9 (INTC_IPR9)....................................................................................................290
12.2.11 Interrupt Priority Register 10 (INTC_IPR10)................................................................................................292
12.2.12 Interrupt Priority Register 11 (INTC_IPR11)................................................................................................293
12.2.13 Interrupt Priority Register 12 (INTC_IPR12)................................................................................................294
12.2.14 Vector Base Address Register (INTC_VBA)................................................................................................ 296
12.2.15 Fast Interrupt 0 Match Register (INTC_FIM0)............................................................................................. 296
12.2.16 Fast Interrupt 0 Vector Address Low Register (INTC_FIVAL0)..................................................................297
12.2.17 Fast Interrupt 0 Vector Address High Register (INTC_FIVAH0)................................................................ 297
12.2.18 Fast Interrupt 1 Match Register (INTC_FIM1)............................................................................................. 298
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12.2.19 Fast Interrupt 1 Vector Address Low Register (INTC_FIVAL1)..................................................................298
12.2.20 Fast Interrupt 1 Vector Address High Register (INTC_FIVAH1)................................................................ 299
12.2.21 IRQ Pending Register 0 (INTC_IRQP0)....................................................................................................... 299
12.2.22 IRQ Pending Register 1 (INTC_IRQP1)....................................................................................................... 300
12.2.23 IRQ Pending Register 2 (INTC_IRQP2)....................................................................................................... 300
12.2.24 IRQ Pending Register 3 (INTC_IRQP3)....................................................................................................... 301
12.2.25 IRQ Pending Register 4 (INTC_IRQP4)....................................................................................................... 301
12.2.26 IRQ Pending Register 5 (INTC_IRQP5)....................................................................................................... 302
12.2.27 IRQ Pending Register 6 (INTC_IRQP6)....................................................................................................... 302
12.2.28 Control Register (INTC_CTRL)....................................................................................................................303
12.3 Functional Description..................................................................................................................................................304
12.3.1 Normal Interrupt Handling.............................................................................................................................304
12.3.2 Interrupt Nesting............................................................................................................................................ 304
12.3.3 Fast Interrupt Handling.................................................................................................................................. 305
12.4 Interrupts.......................................................................................................................................................................305
Chapter 13
Enhanced Direct Memory Access (eDMA)
13.1 Introduction...................................................................................................................................................................307
13.1.1 eDMA system block diagram........................................................................................................................ 307
13.1.2 Block parts..................................................................................................................................................... 308
13.1.3 Features.......................................................................................................................................................... 309
13.2 Modes of operation....................................................................................................................................................... 310
13.3 Memory map/register definition................................................................................................................................... 311
13.3.1 TCD memory................................................................................................................................................. 311
13.3.2 TCD initialization.......................................................................................................................................... 311
13.3.3 TCD structure.................................................................................................................................................311
13.3.4 Reserved memory and bit fields.....................................................................................................................312
13.3.5 DMA register descriptions.............................................................................................................................312
13.3.5.1 DMA Memory map....................................................................................................................312
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13.3.5.2 Control Register (CR)................................................................................................................ 314
13.3.5.3 Error Status Register (ES)..........................................................................................................317
13.3.5.4 Enable Request Register (ERQ).................................................................................................319
13.3.5.5 Enable Error Interrupt Register (EEI)........................................................................................320
13.3.5.6 Clear Enable Error Interrupt Register (CEEI)............................................................................321
13.3.5.7 Set Enable Error Interrupt Register (SEEI)................................................................................323
13.3.5.8 Clear Enable Request Register (CERQ).................................................................................... 324
13.3.5.9 Set Enable Request Register (SERQ)........................................................................................ 325
13.3.5.10 Clear DONE Status Bit Register (CDNE)................................................................................. 326
13.3.5.11 Set START Bit Register (SSRT)............................................................................................... 327
13.3.5.12 Clear Error Register (CERR)..................................................................................................... 329
13.3.5.13 Clear Interrupt Request Register (CINT)...................................................................................330
13.3.5.14 Interrupt Request Register (INT)............................................................................................... 331
13.3.5.15 Error Register (ERR)................................................................................................................. 332
13.3.5.16 Hardware Request Status Register (HRS)................................................................................. 334
13.3.5.17 Enable Asynchronous Request in Stop Register (EARS)..........................................................335
13.3.5.18 Channel Priority Register (DCHPRI3 - DCHPRI0).................................................................. 337
13.3.5.19 TCD Source Address (TCD0_SADDR - TCD3_SADDR)....................................................... 338
13.3.5.20 TCD Signed Source Address Offset (TCD0_SOFF - TCD3_SOFF)........................................ 339
13.3.5.21 TCD Transfer Attributes (TCD0_ATTR - TCD3_ATTR)........................................................ 339
13.3.5.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(TCD0_NBYTES_MLOFFNO - TCD3_NBYTES_MLOFFNO)............................................ 340
13.3.5.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD0_NBY
TES_MLOFFYES - TCD3_NBYTES_MLOFFYES)...............................................................342
13.3.5.24 TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0_NBYTES_MLNO -
TCD3_NBYTES_MLNO).........................................................................................................343
13.3.5.25 TCD Last Source Address Adjustment (TCD0_SLAST - TCD3_SLAST).............................. 345
13.3.5.26 TCD Destination Address (TCD0_DADDR - TCD3_DADDR)...............................................346
13.3.5.27 TCD Signed Destination Address Offset (TCD0_DOFF - TCD3_DOFF)................................346
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13.3.5.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0_
CITER_ELINKNO - TCD3_CITER_ELINKNO).................................................................... 347
13.3.5.29 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0_CIT
ER_ELINKYES - TCD3_CITER_ELINKYES)....................................................................... 348
13.3.5.30 TCD Last Destination Address Adjustment/Scatter Gather Address (TCD0_DLASTSGA -
TCD3_DLASTSGA)................................................................................................................. 350
13.3.5.31 TCD Control and Status (TCD0_CSR - TCD3_CSR)...............................................................351
13.3.5.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0_
BITER_ELINKYES - TCD3_BITER_ELINKYES).................................................................353
13.3.5.33 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0_
BITER_ELINKNO - TCD3_BITER_ELINKNO).................................................................... 354
13.4 Functional description...................................................................................................................................................356
13.4.1 eDMA basic data flow................................................................................................................................... 356
13.4.2 Fault reporting and handling..........................................................................................................................359
13.4.3 Channel preemption....................................................................................................................................... 362
13.5 Initialization/application information........................................................................................................................... 362
13.5.1 eDMA initialization....................................................................................................................................... 362
13.5.2 Programming errors....................................................................................................................................... 364
13.5.3 Arbitration mode considerations....................................................................................................................365
13.5.3.1 Fixed channel arbitration........................................................................................................... 365
13.5.3.2 Round-robin channel arbitration................................................................................................ 365
13.5.4 Performing DMA transfers............................................................................................................................ 365
13.5.4.1 Single request.............................................................................................................................365
13.5.4.2 Multiple requests........................................................................................................................367
13.5.4.3 Using the modulo feature...........................................................................................................369
13.5.5 Monitoring transfer descriptor status............................................................................................................. 369
13.5.5.1 Testing for minor loop completion............................................................................................ 369
13.5.5.2 Reading the transfer descriptors of active channels...................................................................370
13.5.5.3 Checking channel preemption status..........................................................................................371
13.5.6 Channel Linking.............................................................................................................................................371
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13.5.7 Dynamic programming.................................................................................................................................. 372
13.5.7.1 Dynamically changing the channel priority...............................................................................372
13.5.7.2 Dynamic channel linking........................................................................................................... 373
13.5.7.3 Dynamic scatter/gather.............................................................................................................. 373
13.5.8 Suspend/resume a DMA channel with active hardware service requests......................................................376
13.5.8.1 Suspend an active DMA channel...............................................................................................376
13.5.8.2 Resume a DMA channel............................................................................................................ 376
Chapter 14
DMA Channel Multiplexer (DMAMUX)
14.1 Introduction...................................................................................................................................................................379
14.1.1 Overview........................................................................................................................................................379
14.1.2 Features.......................................................................................................................................................... 380
14.1.3 Modes of operation........................................................................................................................................ 380
14.2 Memory map/register definition................................................................................................................................... 380
14.2.1 DMAMUX register descriptions....................................................................................................................380
14.2.1.1 DMAMUX memory map...........................................................................................................380
14.2.1.2 Channel Configuration register (CHCFG0 - CHCFG3)............................................................ 381
14.3 Functional description...................................................................................................................................................382
14.3.1 Always-enabled DMA sources...................................................................................................................... 382
14.3.2 DMA sources with cancel_rewind capability................................................................................................ 384
14.4 Initialization/application information........................................................................................................................... 384
14.4.1 Reset...............................................................................................................................................................384
14.4.2 Enabling and configuring sources..................................................................................................................384
Chapter 15
Power Management Controller (PMC)
15.1 Introduction...................................................................................................................................................................387
15.1.1 Overview........................................................................................................................................................387
15.1.2 Features.......................................................................................................................................................... 387
15.1.3 Modes of Operation....................................................................................................................................... 388
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15.1.4 Block Diagram............................................................................................................................................... 389
15.2 Memory Map and Register Descriptions...................................................................................................................... 390
15.2.1 Control Register (PMC_CTRL).....................................................................................................................391
15.2.2 Status Register (PMC_STS)...........................................................................................................................392
15.3 Functional Description..................................................................................................................................................394
15.4 Resets............................................................................................................................................................................395
15.5 Clocks........................................................................................................................................................................... 395
15.6 Interrupts.......................................................................................................................................................................396
Chapter 16
Event Generator (EVTG)
16.1 About this module.........................................................................................................................................................397
16.1.1 Introduction....................................................................................................................................................397
16.1.2 Features.......................................................................................................................................................... 397
16.1.3 Block diagram................................................................................................................................................398
16.2 Signals...........................................................................................................................................................................398
16.3 Memory Map and register definition............................................................................................................................ 399
16.3.1 EVTG register descriptions............................................................................................................................399
16.3.1.1 EVTG memory map...................................................................................................................399
16.3.1.2 AOI0 Boolean Function Term 0 and 1 Configuration Register (EVTG0_AOI0_BFT01 -
EVTG3_AOI0_BFT01)............................................................................................................. 400
16.3.1.3 AOI0 Boolean Function Term 2 and 3 Configuration Register (EVTG0_AOI0_BFT23 -
EVTG3_AOI0_BFT23)............................................................................................................. 402
16.3.1.4 AOI1 Boolean Function Term 0 and 1 Configuration Register (EVTG0_AOI1_BFT01 -
EVTG3_AOI1_BFT01)............................................................................................................. 404
16.3.1.5 AOI1 Boolean Function Term 2 and 3 Configuration Register (EVTG0_AOI1_BFT23 -
EVTG3_AOI1_BFT23)............................................................................................................. 406
16.3.1.6 Control/Status Register (EVTG0_CTRL - EVTG3_CTRL)..................................................... 408
16.3.1.7 AOI0 Input Filter Register (EVTG0_AOI0_FILT - EVTG3_AOI0_FILT)..............................409
16.3.1.8 AOI1 Input Filter Register (EVTG0_AOI1_FILT - EVTG3_AOI1_FILT)..............................410
16.4 Functional description...................................................................................................................................................411
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16.4.1 Configuration Examples for AOI Combinational function............................................................................411
16.4.2 Input Sync and Filter Logic Description .......................................................................................................413
16.4.3 Flip-Flop mode configuration........................................................................................................................ 414
16.4.3.1 Bypass Mode..............................................................................................................................414
16.4.3.2 RS Trigger Mode....................................................................................................................... 415
16.4.3.3 T-FF Mode................................................................................................................................. 416
16.4.3.4 D-FF Mode.................................................................................................................................417
16.4.3.5 JK-FF Mode............................................................................................................................... 418
16.4.3.6 Latch Mode................................................................................................................................ 419
16.4.4 EVTG Timing Between Inputs and Outputs..................................................................................................420
Chapter 17
Inter-Peripheral Crossbar Switch (XBAR)
17.1 Introduction...................................................................................................................................................................423
17.1.1 Overview........................................................................................................................................................423
17.1.2 Features.......................................................................................................................................................... 423
17.1.3 Modes of Operation....................................................................................................................................... 424
17.1.4 Block Diagram............................................................................................................................................... 424
17.2 Signal Descriptions.......................................................................................................................................................425
17.2.1 XBAR_OUT[0:NUM_OUT-1] - MUX Outputs........................................................................................... 425
17.2.2 XBAR_IN[0:NUM_IN-1] - MUX Inputs......................................................................................................425
17.2.3 DMA_REQ[n] - DMA Request Output(s).....................................................................................................425
17.2.4 DMA_ACK[n] - DMA Acknowledge Input(s)..............................................................................................425
17.2.5 INT_REQ[n] - Interrupt Request Output(s)...................................................................................................426
17.3 Memory Map and Register Descriptions...................................................................................................................... 426
17.3.1 Crossbar A Select Register 0 (XBARA_SEL0).............................................................................................427
17.3.2 Crossbar A Select Register 1 (XBARA_SEL1).............................................................................................428
17.3.3 Crossbar A Select Register 2 (XBARA_SEL2).............................................................................................428
17.3.4 Crossbar A Select Register 3 (XBARA_SEL3).............................................................................................429
17.3.5 Crossbar A Select Register 4 (XBARA_SEL4).............................................................................................429
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17.3.6 Crossbar A Select Register 5 (XBARA_SEL5).............................................................................................430
17.3.7 Crossbar A Select Register 6 (XBARA_SEL6).............................................................................................430
17.3.8 Crossbar A Select Register 7 (XBARA_SEL7).............................................................................................431
17.3.9 Crossbar A Select Register 8 (XBARA_SEL8).............................................................................................431
17.3.10 Crossbar A Select Register 9 (XBARA_SEL9).............................................................................................432
17.3.11 Crossbar A Select Register 10 (XBARA_SEL10).........................................................................................432
17.3.12 Crossbar A Select Register 11 (XBARA_SEL11).........................................................................................433
17.3.13 Crossbar A Select Register 12 (XBARA_SEL12).........................................................................................433
17.3.14 Crossbar A Select Register 13 (XBARA_SEL13).........................................................................................434
17.3.15 Crossbar A Select Register 14 (XBARA_SEL14).........................................................................................434
17.3.16 Crossbar A Select Register 15 (XBARA_SEL15).........................................................................................435
17.3.17 Crossbar A Select Register 16 (XBARA_SEL16).........................................................................................435
17.3.18 Crossbar A Select Register 17 (XBARA_SEL17).........................................................................................436
17.3.19 Crossbar A Select Register 18 (XBARA_SEL18).........................................................................................436
17.3.20 Crossbar A Select Register 19 (XBARA_SEL19).........................................................................................437
17.3.21 Crossbar A Select Register 20 (XBARA_SEL20).........................................................................................437
17.3.22 Crossbar A Select Register 21 (XBARA_SEL21).........................................................................................438
17.3.23 Crossbar A Select Register 22 (XBARA_SEL22).........................................................................................438
17.3.24 Crossbar A Select Register 23 (XBARA_SEL23).........................................................................................439
17.3.25 Crossbar A Select Register 24 (XBARA_SEL24).........................................................................................439
17.3.26 Crossbar A Select Register 25 (XBARA_SEL25).........................................................................................440
17.3.27 Crossbar A Select Register 26 (XBARA_SEL26).........................................................................................440
17.3.28 Crossbar A Select Register 27 (XBARA_SEL27).........................................................................................441
17.3.29 Crossbar A Select Register 28 (XBARA_SEL28).........................................................................................441
17.3.30 Crossbar A Select Register 29 (XBARA_SEL29).........................................................................................442
17.3.31 Crossbar A Select Register 30 (XBARA_SEL30).........................................................................................442
17.3.32 Crossbar A Select Register 31 (XBARA_SEL31).........................................................................................443
17.3.33 Crossbar A Control Register 0 (XBARA_CTRL0)....................................................................................... 443
17.3.34 Crossbar A Control Register 1 (XBARA_CTRL1)....................................................................................... 445
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17.4 Functional Description..................................................................................................................................................447
17.4.1 General...........................................................................................................................................................447
17.4.2 Functional Mode............................................................................................................................................ 448
17.5 Resets............................................................................................................................................................................448
17.6 Clocks........................................................................................................................................................................... 448
17.7 Interrupts and DMA Requests...................................................................................................................................... 448
Chapter 18
On-Chip Clock Synthesis (OCCS)
18.1 Introduction...................................................................................................................................................................451
18.1.1 Overview........................................................................................................................................................451
18.1.2 Features.......................................................................................................................................................... 451
18.2 Modes of Operation...................................................................................................................................................... 452
18.2.1 Internal Clock Sources...................................................................................................................................453
18.2.2 Loop Controlled Pierce Crystal Oscillator.....................................................................................................454
18.2.2.1 External Clock Source - Crystal Oscillator Bypass Option....................................................... 454
18.2.3 External Clock Source - CLKIN....................................................................................................................455
18.3 Block Diagram..............................................................................................................................................................456
18.4 Pin Description..............................................................................................................................................................457
18.4.1 External Clock Reference.............................................................................................................................. 457
18.4.2 Oscillator IO (XTAL, EXTAL)..................................................................................................................... 457
18.4.3 CLKO - Output Pins...................................................................................................................................... 457
18.5 Memory Map and Register Descriptions...................................................................................................................... 457
18.5.1 OCCS register descriptions............................................................................................................................458
18.5.1.1 OCCS memory map...................................................................................................................458
18.5.1.2 PLL Control Register (CTRL)................................................................................................... 458
18.5.1.3 PLL Divide-By Register (DIVBY)............................................................................................460
18.5.1.4 OCCS Status Register (STAT).................................................................................................. 461
18.5.1.5 Oscillator Control Register 1 (OSCTL1)...................................................................................463
18.5.1.6 Oscillator Control Register 2 (OSCTL2)...................................................................................464
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18.5.1.7 External Clock Check Reference (CLKCHKR)........................................................................ 465
18.5.1.8 External Clock Check Target (CLKCHKT).............................................................................. 467
18.5.1.9 Protection Register (PROT).......................................................................................................468
18.6 Functional Description..................................................................................................................................................469
18.7 RC Oscillators...............................................................................................................................................................473
18.7.1 Trimming Frequency on the Internal 200 kHz RC Oscillator....................................................................... 473
18.8 External Reference........................................................................................................................................................473
18.9 Crystal Oscillator.......................................................................................................................................................... 473
18.9.1 Switching Clock Sources............................................................................................................................... 474
18.10 Phase Locked Loop.......................................................................................................................................................475
18.10.1 PLL Recommended Range of Operation.......................................................................................................475
18.10.2 PLL Lock Time Specification........................................................................................................................475
18.10.2.1 Lock Time Definition.................................................................................................................475
18.10.2.2 Parametric Influences on Reaction Time...................................................................................476
18.11 PLL Frequency Lock Detector Block...........................................................................................................................476
18.12 Loss of Reference Clock Detector................................................................................................................................ 477
18.13 Resets............................................................................................................................................................................477
18.14 Clocks........................................................................................................................................................................... 477
18.15 Interrupts.......................................................................................................................................................................478
Chapter 19
Flash Memory Controller (FMC)
19.1 Introduction...................................................................................................................................................................479
19.1.1 Overview........................................................................................................................................................479
19.1.2 Features.......................................................................................................................................................... 479
19.2 Modes of operation....................................................................................................................................................... 480
19.3 External signal description............................................................................................................................................480
19.4 Functional description...................................................................................................................................................480
19.4.1 Default configuration..................................................................................................................................... 480
19.4.2 Speculative reads............................................................................................................................................481
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