2. NXP
  3. MC56F83xxx

NXP MC56F83xxx Reference guide

  • Hello! I am an AI chatbot trained to assist you with the NXP MC56F83xxx Reference guide. I’ve already reviewed the document and can help you find the information you need or explain it in simple terms. Just ask your questions, and providing more details will help me assist you more effectively!
MC56F83xxx Reference Manual
Supports MC56F837xx and MC56F836xx
Document Number: MC56F83XXXRM
Rev. 1, 10/2019
MC56F83xxx Reference Manual, Rev. 1, 10/2019
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................63
1.1.1 Purpose...........................................................................................................................................................63
1.1.2 Audience........................................................................................................................................................ 63
1.2 Conventions.................................................................................................................................................................. 63
1.2.1 Numbering systems........................................................................................................................................63
1.2.2 Typographic notation..................................................................................................................................... 64
1.2.3 Special terms..................................................................................................................................................64
Chapter 2
Introduction
2.1 Target Applications.......................................................................................................................................................65
2.2 System Block Diagram................................................................................................................................................. 65
2.3 Product Family..............................................................................................................................................................68
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................69
3.2 Digital Signal Controller (DSC) Core Configuration...................................................................................................69
3.3 System modules............................................................................................................................................................ 70
3.3.1 System Integration Module (SIM) Configuration..........................................................................................70
3.3.2 MCM Configuration...................................................................................................................................... 71
3.3.3 Inter-Peripheral Crossbar Switch (XBAR) Configuration.............................................................................72
3.3.3.1 Number of inputs and outputs....................................................................................................72
3.3.3.2 XBARA Inputs...........................................................................................................................72
3.3.3.3 XBARA Outputs........................................................................................................................74
3.3.4 Interrupt Controller (INTC) Configuration....................................................................................................76
3.3.4.1 Reset/Interrupt Vector Table......................................................................................................76
3.3.5 DMA Controller Configuration..................................................................................................................... 86
MC56F83xxx Reference Manual, Rev. 1, 10/2019
NXP Semiconductors 3
Section number Title Page
3.3.5.1 eDMA and DMAMUX.............................................................................................................. 87
3.3.6 Power Management Controller (PMC) Configuration...................................................................................90
3.4 Clock Modules..............................................................................................................................................................91
3.4.1 On-Chip Clock Synthesis (OCCS) Configuration......................................................................................... 91
3.5 Memories and Memory Interfaces................................................................................................................................91
3.5.1 Flash Memory Controller (FMC) Configuration........................................................................................... 91
3.5.2 Flash Memory Configuration.........................................................................................................................92
3.5.2.1 Flash memory types and terminology........................................................................................93
3.5.2.2 FTFE_FOPT Register................................................................................................................ 93
3.6 Security and Integrity....................................................................................................................................................93
3.6.1 Computer Operating Properly (COP) Module Configuration........................................................................93
3.6.1.1 WCOP low power clocks...........................................................................................................94
3.6.2 External Watchdog Monitor (EWM) Configuration......................................................................................94
3.6.2.1 EWM low power clocks.............................................................................................................95
3.6.2.2 EWM_OUT pin state in Low Power Modes..............................................................................95
3.6.3 Cyclic Redundancy Check (CRC) Configuration..........................................................................................96
3.7 Analog...........................................................................................................................................................................96
3.7.1 Cyclic Analog-to-Digital Converter (ADC) Configuration...........................................................................96
3.7.1.1 Cyclic ADC Instantiation...........................................................................................................97
3.7.1.2 Cyclic ADC SYNC Signal Connections....................................................................................97
3.7.1.3 Cyclic ADC and PWM Connections......................................................................................... 97
3.7.2 Comparator (CMP) Configuration.................................................................................................................98
3.7.2.1 Comparator Channel Assignments.............................................................................................98
3.7.2.2 Comparator Voltage References................................................................................................ 99
3.7.3 12-bit Digital-to-Analog Converter (DAC) Configuration............................................................................99
3.8 Timers and PWM..........................................................................................................................................................100
3.8.1 PWM Configuration.......................................................................................................................................100
3.8.1.1 PWM auxiliary signals and analog inputs..................................................................................101
3.8.2 PIT Configuration.......................................................................................................................................... 101
MC56F83xxx Reference Manual, Rev. 1, 10/2019
4 NXP Semiconductors
Section number Title Page
3.8.2.1 PIT low power clocks................................................................................................................ 102
3.8.2.2 PIT master/slave selection......................................................................................................... 102
3.8.3 TMR Configuration........................................................................................................................................103
3.9 Communication interfaces............................................................................................................................................ 103
3.9.1 CAN Configuration........................................................................................................................................103
3.9.1.1 FlexCAN glitch filter................................................................................................................. 104
3.9.1.2 FlexCAN3 Supervisor Mode..................................................................................................... 104
3.9.2 Serial Peripheral Interface (SPI) Configuration.............................................................................................105
3.9.3 Inter-Integrated Circuit (I2C) Configuration................................................................................................. 105
3.9.3.1 I2C module address matching to wake the device from stop mode...........................................106
3.9.4 SCI Configuration..........................................................................................................................................107
3.10 Human-machine interfaces (HMI)................................................................................................................................107
3.10.1 GPIO Configuration.......................................................................................................................................107
3.10.1.1 GPIO Port D[4:0] configuration................................................................................................ 108
3.10.1.2 GPIO unbonded pads................................................................................................................. 109
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................111
4.2 Program/Data Memory Maps....................................................................................................................................... 111
4.3 Core and System Peripheral Memory Map...................................................................................................................113
4.4 Slave Peripheral Memory Map..................................................................................................................................... 113
Chapter 5
Clock Distribution
5.1 Overview.......................................................................................................................................................................117
5.2 Clock Distribution.........................................................................................................................................................117
Chapter 6
ROM Bootloader
6.1 Chip-specific Information.............................................................................................................................................121
6.1.1 Bootloader Peripheral Pinmux.......................................................................................................................121
6.1.2 Bootloader Memory Access...........................................................................................................................122
MC56F83xxx Reference Manual, Rev. 1, 10/2019
NXP Semiconductors 5
Section number Title Page
6.2 Introduction...................................................................................................................................................................122
6.3 Functional Description..................................................................................................................................................124
6.3.1 The Bootloader Configuration Area (BCA)...................................................................................................124
6.3.2 Start-up Process..............................................................................................................................................126
6.3.3 Bootloader Protocol....................................................................................................................................... 129
6.3.3.1 Command with no data phase.................................................................................................... 129
6.3.3.2 Command with incoming data phase.........................................................................................130
6.3.3.3 Command with outgoing data phase..........................................................................................131
6.3.4 Bootloader Packet Types............................................................................................................................... 133
6.3.4.1 Ping packet.................................................................................................................................133
6.3.4.2 Ping Response Packet................................................................................................................ 134
6.3.4.3 Framing Packet.......................................................................................................................... 134
6.3.4.4 Command packet........................................................................................................................136
6.3.4.5 Data packet.................................................................................................................................138
6.3.4.6 Response packet.........................................................................................................................138
6.3.5 Bootloader Command API.............................................................................................................................140
6.3.5.1 ReliableUpdate command..........................................................................................................141
6.3.5.2 Execute command......................................................................................................................142
6.3.5.3 Reset command..........................................................................................................................143
6.3.5.4 GetProperty command............................................................................................................... 144
6.3.5.5 FlashEraseAll command............................................................................................................ 146
6.3.5.6 FlashEraseRegion command......................................................................................................147
6.3.5.7 FlashEraseAllUnsecure command............................................................................................. 149
6.3.5.8 FlashProgramOnce command....................................................................................................150
6.3.5.9 FlashReadOnce command..........................................................................................................152
6.3.5.10 FlashReadResource command................................................................................................... 154
6.3.5.11 FlashSecurityDisable command.................................................................................................156
6.3.5.12 WriteMemory command............................................................................................................158
6.3.5.13 ReadMemory command.............................................................................................................160
MC56F83xxx Reference Manual, Rev. 1, 10/2019
6 NXP Semiconductors
Section number Title Page
6.3.6 Bootloader Exit state......................................................................................................................................162
6.4 Peripherals Supported................................................................................................................................................... 162
6.4.1 I2C Peripheral................................................................................................................................................ 162
6.4.2 UART Peripheral........................................................................................................................................... 164
6.4.3 FlexCAN Peripheral.......................................................................................................................................167
6.5 Get/SetProperty Command Properties..........................................................................................................................169
6.5.1 Property Definitions.......................................................................................................................................169
6.5.1.1 CurrentVersion Property............................................................................................................170
6.5.1.2 AvailablePeripherals Property................................................................................................... 170
6.5.1.3 AvailableCommands Property................................................................................................... 170
6.6 Verifying the application in flash using CRC-32......................................................................................................... 171
6.7 Bootloader Status Error Codes......................................................................................................................................172
6.8 ROM flash driver API...................................................................................................................................................173
6.8.1 Introduction....................................................................................................................................................173
6.8.2 Struct of FlashDriverInterface....................................................................................................................... 173
6.8.3 Details of structs.............................................................................................................................................174
6.8.4 Flash Driver APIs...........................................................................................................................................176
6.8.5 Integrate flash driver API to user project.......................................................................................................177
Chapter 7
Power Management
7.1 Overview.......................................................................................................................................................................179
7.2 Architecture...................................................................................................................................................................179
7.3 External Supplies and Regulation.................................................................................................................................180
7.4 User Power Management Methods...............................................................................................................................180
Chapter 8
Signal Multiplexing and Signal Descriptions
8.1 Signal Multiplexing and Pin Assignments....................................................................................................................183
8.2 Pinout diagrams............................................................................................................................................................ 186
Chapter 9
Memory Resource Protection (MRP)
MC56F83xxx Reference Manual, Rev. 1, 10/2019
NXP Semiconductors 7
Section number Title Page
9.1 Overview.......................................................................................................................................................................191
9.2 Features.........................................................................................................................................................................192
9.3 Operation.......................................................................................................................................................................192
9.4 Programming Model Overview.................................................................................................................................... 196
9.5 Memory Resource Protection Restrictions................................................................................................................... 196
9.6 Base Address Setup.......................................................................................................................................................196
9.7 Programming Example................................................................................................................................................. 198
Chapter 10
Miscellaneous Control Module (MCM)
10.1 Introduction...................................................................................................................................................................201
10.1.1 Features.......................................................................................................................................................... 201
10.2 Memory Map/Register Descriptions.............................................................................................................................202
10.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)....................................................................203
10.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)................................................................ 203
10.2.3 Core control register (MCM_CPCR).............................................................................................................204
10.2.4 Core fault address register (MCM_CFADR).................................................................................................206
10.2.5 Core fault attributes register (MCM_CFATR).............................................................................................. 207
10.2.6 Core fault location register (MCM_CFLOC)................................................................................................ 208
10.2.7 Core fault interrupt enable register (MCM_CFIER)......................................................................................208
10.2.8 MCM interrupt status register (MCM_CFISR)............................................................................................. 209
10.2.9 Core fault data register (MCM_CFDTR).......................................................................................................210
10.2.10 Resource Protection Control Register (MCM_RPCR).................................................................................. 210
10.2.11 User Flash Base Address Register (MCM_UFLASHBAR)..........................................................................211
10.2.12 User Program RAM Base Address Register (MCM_UPRAMBAR)............................................................ 212
10.2.13 User Boot ROM Base Address Register (MCM_UBROMBAR)..................................................................212
10.2.14 Resource Protection Other Stack Pointer (MCM_SRPOSP).........................................................................213
10.2.15 Memory Protection Illegal PC (MCM_SRPIPC)...........................................................................................213
10.2.16 Resource Protection Misaligned PC (MCM_SRPMPC)............................................................................... 215
10.3 Functional Description..................................................................................................................................................216
MC56F83xxx Reference Manual, Rev. 1, 10/2019
8 NXP Semiconductors
Section number Title Page
10.3.1 Core Data Fault Recovery Registers..............................................................................................................216
Chapter 11
System Integration Module (SIM)
11.1 Introduction...................................................................................................................................................................217
11.1.1 Overview........................................................................................................................................................217
11.1.2 Features.......................................................................................................................................................... 217
11.1.3 Modes of Operation....................................................................................................................................... 218
11.1.4 Block Diagram............................................................................................................................................... 219
11.2 Memory Map and Register Descriptions...................................................................................................................... 220
11.2.1 Control Register (SIM_CTRL)...................................................................................................................... 222
11.2.2 Reset Status Register (SIM_RSTAT)............................................................................................................ 224
11.2.3 Software Control Register (SIM_SCR0)....................................................................................................... 225
11.2.4 Software Control Register (SIM_SCR1)....................................................................................................... 226
11.2.5 Software Control Register (SIM_SCR2)....................................................................................................... 226
11.2.6 Software Control Register (SIM_SCR3)....................................................................................................... 226
11.2.7 Most Significant Half of JTAG ID (SIM_MSHID).......................................................................................227
11.2.8 Least Significant Half of JTAG ID (SIM_LSHID)....................................................................................... 228
11.2.9 Power Control Register (SIM_PWR)............................................................................................................ 229
11.2.10 Clock Output Select Register (SIM_CLKOUT)............................................................................................230
11.2.11 Peripheral Clock Rate Register (SIM_PCR)..................................................................................................232
11.2.12 Peripheral Clock Enable Register 0 (SIM_PCE0)......................................................................................... 233
11.2.13 Peripheral Clock Enable Register 1 (SIM_PCE1)......................................................................................... 235
11.2.14 Peripheral Clock Enable Register 2 (SIM_PCE2)......................................................................................... 237
11.2.15 Peripheral Clock Enable Register 3 (SIM_PCE3)......................................................................................... 239
11.2.16 Peripheral Clock STOP Disable Register 0 (SIM_SD0)............................................................................... 240
11.2.17 Peripheral Clock STOP Disable Register 1 (SIM_SD1)............................................................................... 243
11.2.18 Peripheral Clock STOP Disable Register 2 (SIM_SD2)............................................................................... 245
11.2.19 Peripheral Clock STOP Disable Register 3 (SIM_SD3)............................................................................... 247
11.2.20 I/O Short Address Location Register (SIM_IOSAHI)...................................................................................249
MC56F83xxx Reference Manual, Rev. 1, 10/2019
NXP Semiconductors 9
Section number Title Page
11.2.21 I/O Short Address Location Register (SIM_IOSALO)..................................................................................250
11.2.22 Protection Register (SIM_PROT)..................................................................................................................251
11.2.23 GPIOA LSBs Peripheral Select Register (SIM_GPSAL)..............................................................................253
11.2.24 GPIOA MSBs Peripheral Select Register (SIM_GPSAH)............................................................................254
11.2.25 GPIOB LSBs Peripheral Select Register (SIM_GPSBL)..............................................................................255
11.2.26 GPIOB MSBs Peripheral Select Register (SIM_GPSBH)............................................................................ 255
11.2.27 GPIOC LSBs Peripheral Select Register (SIM_GPSCL)..............................................................................256
11.2.28 GPIOC MSBs Peripheral Select Register (SIM_GPSCH)............................................................................ 257
11.2.29 GPIOD LSBs Peripheral Select Register (SIM_GPSDL)..............................................................................259
11.2.30 GPIOE LSBs Peripheral Select Register (SIM_GPSEL).............................................................................. 259
11.2.31 GPIOE MSBs Peripheral Select Register (SIM_GPSEH).............................................................................261
11.2.32 GPIOF LSBs Peripheral Select Register (SIM_GPSFL)...............................................................................261
11.2.33 GPIOF MSBs Peripheral Select Register (SIM_GPSFH)............................................................................. 263
11.2.34 GPIOG LSBs Peripheral Select Register (SIM_GPSGL)..............................................................................264
11.2.35 GPIOG MSBs Peripheral Select Register (SIM_GPSGH)............................................................................265
11.2.36 Internal Peripheral Select Register 0 (SIM_IPS0)......................................................................................... 266
11.2.37 Miscellaneous Register 0 (SIM_MISC0).......................................................................................................269
11.2.38 Peripheral Software Reset Register 0 (SIM_PSWR0)...................................................................................270
11.2.39 Peripheral Software Reset Register 1 (SIM_PSWR1)...................................................................................271
11.2.40 Peripheral Software Reset Register 2 (SIM_PSWR2)...................................................................................273
11.2.41 Peripheral Software Reset Register 3 (SIM_PSWR3)...................................................................................274
11.2.42 Power Mode Register (SIM_PWRMODE)....................................................................................................275
11.2.43 Non-Volatile Memory Option Register 6 (Low) (SIM_NVMOPT6_LOW).................................................276
11.2.44 PWM Select Register (SIM_PWM_SEL)......................................................................................................277
11.2.45 ADC and TMR Select Register (SIM_ADC_TMR_SEL).............................................................................279
11.2.46 Boot Mode Override Register (SIM_BOOT_MODE_OVERRIDE)............................................................ 280
11.3 Functional Description..................................................................................................................................................281
11.3.1 Clock Generation Overview...........................................................................................................................281
11.3.2 Power-Down Modes Overview......................................................................................................................281
MC56F83xxx Reference Manual, Rev. 1, 10/2019
10 NXP Semiconductors
Section number Title Page
11.3.3 STOP and WAIT Mode Disable Function.....................................................................................................283
11.4 Resets............................................................................................................................................................................284
11.5 Clocks........................................................................................................................................................................... 284
11.6 Interrupts.......................................................................................................................................................................284
Chapter 12
Interrupt Controller (INTC)
12.1 Introduction...................................................................................................................................................................285
12.1.1 References......................................................................................................................................................285
12.1.2 Features.......................................................................................................................................................... 285
12.1.3 Modes of Operation....................................................................................................................................... 285
12.1.4 Block Diagram............................................................................................................................................... 286
12.2 Memory Map and Registers..........................................................................................................................................287
12.2.1 Interrupt Priority Register 0 (INTC_IPR0)....................................................................................................288
12.2.2 Interrupt Priority Register 1 (INTC_IPR1)....................................................................................................289
12.2.3 Interrupt Priority Register 2 (INTC_IPR2)....................................................................................................291
12.2.4 Interrupt Priority Register 3 (INTC_IPR3)....................................................................................................292
12.2.5 Interrupt Priority Register 4 (INTC_IPR4)....................................................................................................294
12.2.6 Interrupt Priority Register 5 (INTC_IPR5)....................................................................................................296
12.2.7 Interrupt Priority Register 6 (INTC_IPR6)....................................................................................................297
12.2.8 Interrupt Priority Register 7 (INTC_IPR7)....................................................................................................299
12.2.9 Interrupt Priority Register 8 (INTC_IPR8)....................................................................................................300
12.2.10 Interrupt Priority Register 9 (INTC_IPR9)....................................................................................................302
12.2.11 Interrupt Priority Register 10 (INTC_IPR10)................................................................................................304
12.2.12 Interrupt Priority Register 11 (INTC_IPR11)................................................................................................305
12.2.13 Interrupt Priority Register 12 (INTC_IPR12)................................................................................................306
12.2.14 Vector Base Address Register (INTC_VBA)................................................................................................ 308
12.2.15 Fast Interrupt 0 Match Register (INTC_FIM0)............................................................................................. 308
12.2.16 Fast Interrupt 0 Vector Address Low Register (INTC_FIVAL0)..................................................................309
12.2.17 Fast Interrupt 0 Vector Address High Register (INTC_FIVAH0)................................................................ 309
MC56F83xxx Reference Manual, Rev. 1, 10/2019
NXP Semiconductors 11
Section number Title Page
12.2.18 Fast Interrupt 1 Match Register (INTC_FIM1)............................................................................................. 310
12.2.19 Fast Interrupt 1 Vector Address Low Register (INTC_FIVAL1)..................................................................310
12.2.20 Fast Interrupt 1 Vector Address High Register (INTC_FIVAH1)................................................................ 311
12.2.21 IRQ Pending Register 0 (INTC_IRQP0)....................................................................................................... 311
12.2.22 IRQ Pending Register 1 (INTC_IRQP1)....................................................................................................... 312
12.2.23 IRQ Pending Register 2 (INTC_IRQP2)....................................................................................................... 312
12.2.24 IRQ Pending Register 3 (INTC_IRQP3)....................................................................................................... 313
12.2.25 IRQ Pending Register 4 (INTC_IRQP4)....................................................................................................... 313
12.2.26 IRQ Pending Register 5 (INTC_IRQP5)....................................................................................................... 314
12.2.27 IRQ Pending Register 6 (INTC_IRQP6)....................................................................................................... 314
12.2.28 Control Register (INTC_CTRL)....................................................................................................................315
12.3 Functional Description..................................................................................................................................................316
12.3.1 Normal Interrupt Handling.............................................................................................................................316
12.3.2 Interrupt Nesting............................................................................................................................................ 316
12.3.3 Fast Interrupt Handling.................................................................................................................................. 317
12.4 Interrupts.......................................................................................................................................................................317
Chapter 13
Enhanced Direct Memory Access (eDMA)
13.1 Introduction...................................................................................................................................................................319
13.1.1 eDMA system block diagram........................................................................................................................ 319
13.1.2 Block parts..................................................................................................................................................... 320
13.1.3 Features.......................................................................................................................................................... 321
13.2 Modes of operation....................................................................................................................................................... 322
13.3 Memory map/register definition................................................................................................................................... 323
13.3.1 TCD memory................................................................................................................................................. 323
13.3.2 TCD initialization.......................................................................................................................................... 323
13.3.3 TCD structure.................................................................................................................................................323
13.3.4 Reserved memory and bit fields.....................................................................................................................324
13.3.5 DMA register descriptions.............................................................................................................................324
MC56F83xxx Reference Manual, Rev. 1, 10/2019
12 NXP Semiconductors
Section number Title Page
13.3.5.1 DMA Memory map....................................................................................................................324
13.3.5.2 Control Register (CR)................................................................................................................ 326
13.3.5.3 Error Status Register (ES)..........................................................................................................329
13.3.5.4 Enable Request Register (ERQ).................................................................................................331
13.3.5.5 Enable Error Interrupt Register (EEI)........................................................................................332
13.3.5.6 Clear Enable Error Interrupt Register (CEEI)............................................................................333
13.3.5.7 Set Enable Error Interrupt Register (SEEI)................................................................................335
13.3.5.8 Clear Enable Request Register (CERQ).................................................................................... 336
13.3.5.9 Set Enable Request Register (SERQ)........................................................................................ 337
13.3.5.10 Clear DONE Status Bit Register (CDNE)................................................................................. 338
13.3.5.11 Set START Bit Register (SSRT)............................................................................................... 339
13.3.5.12 Clear Error Register (CERR)..................................................................................................... 341
13.3.5.13 Clear Interrupt Request Register (CINT)...................................................................................342
13.3.5.14 Interrupt Request Register (INT)............................................................................................... 343
13.3.5.15 Error Register (ERR)................................................................................................................. 344
13.3.5.16 Hardware Request Status Register (HRS)................................................................................. 346
13.3.5.17 Enable Asynchronous Request in Stop Register (EARS)..........................................................347
13.3.5.18 Channel Priority Register (DCHPRI3 - DCHPRI0).................................................................. 349
13.3.5.19 TCD Source Address (TCD0_SADDR - TCD3_SADDR)....................................................... 350
13.3.5.20 TCD Signed Source Address Offset (TCD0_SOFF - TCD3_SOFF)........................................ 351
13.3.5.21 TCD Transfer Attributes (TCD0_ATTR - TCD3_ATTR)........................................................ 351
13.3.5.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(TCD0_NBYTES_MLOFFNO - TCD3_NBYTES_MLOFFNO)............................................ 352
13.3.5.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD0_NBY
TES_MLOFFYES - TCD3_NBYTES_MLOFFYES)...............................................................354
13.3.5.24 TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0_NBYTES_MLNO -
TCD3_NBYTES_MLNO).........................................................................................................355
13.3.5.25 TCD Last Source Address Adjustment (TCD0_SLAST - TCD3_SLAST).............................. 357
13.3.5.26 TCD Destination Address (TCD0_DADDR - TCD3_DADDR)...............................................358
13.3.5.27 TCD Signed Destination Address Offset (TCD0_DOFF - TCD3_DOFF)................................358
MC56F83xxx Reference Manual, Rev. 1, 10/2019
NXP Semiconductors 13
Section number Title Page
13.3.5.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0_
CITER_ELINKNO - TCD3_CITER_ELINKNO).................................................................... 359
13.3.5.29 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0_CIT
ER_ELINKYES - TCD3_CITER_ELINKYES)....................................................................... 360
13.3.5.30 TCD Last Destination Address Adjustment/Scatter Gather Address (TCD0_DLASTSGA -
TCD3_DLASTSGA)................................................................................................................. 362
13.3.5.31 TCD Control and Status (TCD0_CSR - TCD3_CSR)...............................................................363
13.3.5.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0_
BITER_ELINKYES - TCD3_BITER_ELINKYES).................................................................365
13.3.5.33 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0_
BITER_ELINKNO - TCD3_BITER_ELINKNO).................................................................... 366
13.4 Functional description...................................................................................................................................................368
13.4.1 eDMA basic data flow................................................................................................................................... 368
13.4.2 Fault reporting and handling..........................................................................................................................371
13.4.3 Channel preemption....................................................................................................................................... 374
13.5 Initialization/application information........................................................................................................................... 374
13.5.1 eDMA initialization....................................................................................................................................... 374
13.5.2 Programming errors....................................................................................................................................... 376
13.5.3 Arbitration mode considerations....................................................................................................................377
13.5.3.1 Fixed channel arbitration........................................................................................................... 377
13.5.3.2 Round-robin channel arbitration................................................................................................ 377
13.5.4 Performing DMA transfers............................................................................................................................ 377
13.5.4.1 Single request.............................................................................................................................377
13.5.4.2 Multiple requests........................................................................................................................379
13.5.4.3 Using the modulo feature...........................................................................................................381
13.5.5 Monitoring transfer descriptor status............................................................................................................. 381
13.5.5.1 Testing for minor loop completion............................................................................................ 381
13.5.5.2 Reading the transfer descriptors of active channels...................................................................382
13.5.5.3 Checking channel preemption status..........................................................................................383
13.5.6 Channel Linking.............................................................................................................................................383
MC56F83xxx Reference Manual, Rev. 1, 10/2019
14 NXP Semiconductors
Section number Title Page
13.5.7 Dynamic programming.................................................................................................................................. 384
13.5.7.1 Dynamically changing the channel priority...............................................................................384
13.5.7.2 Dynamic channel linking........................................................................................................... 385
13.5.7.3 Dynamic scatter/gather.............................................................................................................. 385
13.5.8 Suspend/resume a DMA channel with active hardware service requests......................................................388
13.5.8.1 Suspend an active DMA channel...............................................................................................388
13.5.8.2 Resume a DMA channel............................................................................................................ 388
Chapter 14
DMA Channel Multiplexer (DMAMUX)
14.1 Introduction...................................................................................................................................................................391
14.1.1 Overview........................................................................................................................................................391
14.1.2 Features.......................................................................................................................................................... 392
14.1.3 Modes of operation........................................................................................................................................ 392
14.2 Memory map/register definition................................................................................................................................... 392
14.2.1 DMAMUX register descriptions....................................................................................................................392
14.2.1.1 DMAMUX memory map...........................................................................................................392
14.2.1.2 Channel Configuration register (CHCFG0 - CHCFG3)............................................................ 393
14.3 Functional description...................................................................................................................................................394
14.3.1 Always-enabled DMA sources...................................................................................................................... 394
14.3.2 DMA sources with cancel_rewind capability................................................................................................ 396
14.4 Initialization/application information........................................................................................................................... 396
14.4.1 Reset...............................................................................................................................................................396
14.4.2 Enabling and configuring sources..................................................................................................................396
Chapter 15
Power Management Controller (PMC)
15.1 Introduction...................................................................................................................................................................399
15.1.1 Overview........................................................................................................................................................399
15.1.2 Features.......................................................................................................................................................... 399
15.1.3 Modes of Operation....................................................................................................................................... 400
MC56F83xxx Reference Manual, Rev. 1, 10/2019
NXP Semiconductors 15
Section number Title Page
15.1.4 Block Diagram............................................................................................................................................... 401
15.2 Memory Map and Register Descriptions...................................................................................................................... 402
15.2.1 Control Register (PMC_CTRL).....................................................................................................................403
15.2.2 Status Register (PMC_STS)...........................................................................................................................404
15.3 Functional Description..................................................................................................................................................406
15.4 Resets............................................................................................................................................................................407
15.5 Clocks........................................................................................................................................................................... 407
15.6 Interrupts.......................................................................................................................................................................408
Chapter 16
Event Generator (EVTG)
16.1 About this module.........................................................................................................................................................409
16.1.1 Introduction....................................................................................................................................................409
16.1.2 Features.......................................................................................................................................................... 409
16.1.3 Block diagram................................................................................................................................................410
16.2 Signals...........................................................................................................................................................................410
16.3 Memory Map and register definition............................................................................................................................ 411
16.3.1 EVTG register descriptions............................................................................................................................411
16.3.1.1 EVTG memory map...................................................................................................................411
16.3.1.2 AOI0 Boolean Function Term 0 and 1 Configuration Register (EVTG0_AOI0_BFT01 -
EVTG3_AOI0_BFT01)............................................................................................................. 412
16.3.1.3 AOI0 Boolean Function Term 2 and 3 Configuration Register (EVTG0_AOI0_BFT23 -
EVTG3_AOI0_BFT23)............................................................................................................. 414
16.3.1.4 AOI1 Boolean Function Term 0 and 1 Configuration Register (EVTG0_AOI1_BFT01 -
EVTG3_AOI1_BFT01)............................................................................................................. 416
16.3.1.5 AOI1 Boolean Function Term 2 and 3 Configuration Register (EVTG0_AOI1_BFT23 -
EVTG3_AOI1_BFT23)............................................................................................................. 418
16.3.1.6 Control/Status Register (EVTG0_CTRL - EVTG3_CTRL)..................................................... 420
16.3.1.7 AOI0 Input Filter Register (EVTG0_AOI0_FILT - EVTG3_AOI0_FILT)..............................421
16.3.1.8 AOI1 Input Filter Register (EVTG0_AOI1_FILT - EVTG3_AOI1_FILT)..............................422
16.4 Functional description...................................................................................................................................................423
MC56F83xxx Reference Manual, Rev. 1, 10/2019
16 NXP Semiconductors
Section number Title Page
16.4.1 Configuration Examples for AOI Combinational function............................................................................423
16.4.2 Input Sync and Filter Logic Description .......................................................................................................425
16.4.3 Flip-Flop mode configuration........................................................................................................................ 426
16.4.3.1 Bypass Mode..............................................................................................................................426
16.4.3.2 RS Trigger Mode....................................................................................................................... 427
16.4.3.3 T-FF Mode................................................................................................................................. 428
16.4.3.4 D-FF Mode.................................................................................................................................429
16.4.3.5 JK-FF Mode............................................................................................................................... 430
16.4.3.6 Latch Mode................................................................................................................................ 431
16.4.4 EVTG Timing Between Inputs and Outputs..................................................................................................432
Chapter 17
Inter-Peripheral Crossbar Switch (XBAR)
17.1 Introduction...................................................................................................................................................................435
17.1.1 Overview........................................................................................................................................................435
17.1.2 Features.......................................................................................................................................................... 435
17.1.3 Modes of Operation....................................................................................................................................... 436
17.1.4 Block Diagram............................................................................................................................................... 436
17.2 Signal Descriptions.......................................................................................................................................................437
17.2.1 XBAR_OUT[0:NUM_OUT-1] - MUX Outputs........................................................................................... 437
17.2.2 XBAR_IN[0:NUM_IN-1] - MUX Inputs......................................................................................................437
17.2.3 DMA_REQ[n] - DMA Request Output(s).....................................................................................................437
17.2.4 DMA_ACK[n] - DMA Acknowledge Input(s)..............................................................................................437
17.2.5 INT_REQ[n] - Interrupt Request Output(s)...................................................................................................438
17.3 Memory Map and Register Descriptions...................................................................................................................... 438
17.3.1 Crossbar A Select Register 0 (XBARA_SEL0).............................................................................................439
17.3.2 Crossbar A Select Register 1 (XBARA_SEL1).............................................................................................440
17.3.3 Crossbar A Select Register 2 (XBARA_SEL2).............................................................................................440
17.3.4 Crossbar A Select Register 3 (XBARA_SEL3).............................................................................................441
17.3.5 Crossbar A Select Register 4 (XBARA_SEL4).............................................................................................441
MC56F83xxx Reference Manual, Rev. 1, 10/2019
NXP Semiconductors 17
Section number Title Page
17.3.6 Crossbar A Select Register 5 (XBARA_SEL5).............................................................................................442
17.3.7 Crossbar A Select Register 6 (XBARA_SEL6).............................................................................................442
17.3.8 Crossbar A Select Register 7 (XBARA_SEL7).............................................................................................443
17.3.9 Crossbar A Select Register 8 (XBARA_SEL8).............................................................................................443
17.3.10 Crossbar A Select Register 9 (XBARA_SEL9).............................................................................................444
17.3.11 Crossbar A Select Register 10 (XBARA_SEL10).........................................................................................444
17.3.12 Crossbar A Select Register 11 (XBARA_SEL11).........................................................................................445
17.3.13 Crossbar A Select Register 12 (XBARA_SEL12).........................................................................................445
17.3.14 Crossbar A Select Register 13 (XBARA_SEL13).........................................................................................446
17.3.15 Crossbar A Select Register 14 (XBARA_SEL14).........................................................................................446
17.3.16 Crossbar A Select Register 15 (XBARA_SEL15).........................................................................................447
17.3.17 Crossbar A Select Register 16 (XBARA_SEL16).........................................................................................447
17.3.18 Crossbar A Select Register 17 (XBARA_SEL17).........................................................................................448
17.3.19 Crossbar A Select Register 18 (XBARA_SEL18).........................................................................................448
17.3.20 Crossbar A Select Register 19 (XBARA_SEL19).........................................................................................449
17.3.21 Crossbar A Select Register 20 (XBARA_SEL20).........................................................................................449
17.3.22 Crossbar A Select Register 21 (XBARA_SEL21).........................................................................................450
17.3.23 Crossbar A Select Register 22 (XBARA_SEL22).........................................................................................450
17.3.24 Crossbar A Select Register 23 (XBARA_SEL23).........................................................................................451
17.3.25 Crossbar A Select Register 24 (XBARA_SEL24).........................................................................................451
17.3.26 Crossbar A Select Register 25 (XBARA_SEL25).........................................................................................452
17.3.27 Crossbar A Select Register 26 (XBARA_SEL26).........................................................................................452
17.3.28 Crossbar A Select Register 27 (XBARA_SEL27).........................................................................................453
17.3.29 Crossbar A Select Register 28 (XBARA_SEL28).........................................................................................453
17.3.30 Crossbar A Select Register 29 (XBARA_SEL29).........................................................................................454
17.3.31 Crossbar A Select Register 30 (XBARA_SEL30).........................................................................................454
17.3.32 Crossbar A Select Register 31 (XBARA_SEL31).........................................................................................455
17.3.33 Crossbar A Control Register 0 (XBARA_CTRL0)....................................................................................... 455
17.3.34 Crossbar A Control Register 1 (XBARA_CTRL1)....................................................................................... 457
MC56F83xxx Reference Manual, Rev. 1, 10/2019
18 NXP Semiconductors
Section number Title Page
17.4 Functional Description..................................................................................................................................................459
17.4.1 General...........................................................................................................................................................459
17.4.2 Functional Mode............................................................................................................................................ 460
17.5 Resets............................................................................................................................................................................460
17.6 Clocks........................................................................................................................................................................... 460
17.7 Interrupts and DMA Requests...................................................................................................................................... 460
Chapter 18
On-Chip Clock Synthesis (OCCS)
18.1 Introduction...................................................................................................................................................................463
18.1.1 Overview........................................................................................................................................................463
18.1.2 Features.......................................................................................................................................................... 463
18.2 Modes of Operation...................................................................................................................................................... 464
18.2.1 Internal Clock Sources...................................................................................................................................465
18.2.2 Loop Controlled Pierce Crystal Oscillator.....................................................................................................466
18.2.2.1 External Clock Source - Crystal Oscillator Bypass Option....................................................... 466
18.2.3 External Clock Source - CLKIN....................................................................................................................467
18.3 Block Diagram..............................................................................................................................................................468
18.4 Pin Description..............................................................................................................................................................469
18.4.1 External Clock Reference.............................................................................................................................. 469
18.4.2 Oscillator IO (XTAL, EXTAL)..................................................................................................................... 469
18.4.3 CLKO - Output Pins...................................................................................................................................... 469
18.5 Memory Map and Register Descriptions...................................................................................................................... 469
18.5.1 OCCS register descriptions............................................................................................................................470
18.5.1.1 OCCS memory map...................................................................................................................470
18.5.1.2 PLL Control Register (CTRL)................................................................................................... 470
18.5.1.3 PLL Divide-By Register (DIVBY)............................................................................................472
18.5.1.4 OCCS Status Register (STAT).................................................................................................. 473
18.5.1.5 Oscillator Control Register 1 (OSCTL1)...................................................................................475
18.5.1.6 Oscillator Control Register 2 (OSCTL2)...................................................................................476
MC56F83xxx Reference Manual, Rev. 1, 10/2019
NXP Semiconductors 19
Section number Title Page
18.5.1.7 External Clock Check Reference (CLKCHKR)........................................................................ 477
18.5.1.8 External Clock Check Target (CLKCHKT).............................................................................. 479
18.5.1.9 Protection Register (PROT).......................................................................................................480
18.6 Functional Description..................................................................................................................................................481
18.7 RC Oscillators...............................................................................................................................................................485
18.7.1 Trimming Frequency on the Internal 200 kHz RC Oscillator....................................................................... 485
18.8 External Reference........................................................................................................................................................485
18.9 Crystal Oscillator.......................................................................................................................................................... 485
18.9.1 Switching Clock Sources............................................................................................................................... 486
18.10 Phase Locked Loop.......................................................................................................................................................487
18.10.1 PLL Recommended Range of Operation.......................................................................................................487
18.10.2 PLL Lock Time Specification........................................................................................................................487
18.10.2.1 Lock Time Definition.................................................................................................................487
18.10.2.2 Parametric Influences on Reaction Time...................................................................................488
18.11 PLL Frequency Lock Detector Block...........................................................................................................................488
18.12 Loss of Reference Clock Detector................................................................................................................................ 489
18.13 Resets............................................................................................................................................................................489
18.14 Clocks........................................................................................................................................................................... 489
18.15 Interrupts.......................................................................................................................................................................490
Chapter 19
Flash Memory Controller (FMC)
19.1 Introduction...................................................................................................................................................................491
19.1.1 Overview........................................................................................................................................................491
19.1.2 Features.......................................................................................................................................................... 491
19.2 Modes of operation....................................................................................................................................................... 492
19.3 External signal description............................................................................................................................................492
19.4 Functional description...................................................................................................................................................492
19.4.1 Default configuration..................................................................................................................................... 492
19.4.2 Speculative reads............................................................................................................................................493
MC56F83xxx Reference Manual, Rev. 1, 10/2019
20 NXP Semiconductors
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
/