AKM AK7736BVQ Evaluation Board Manual

Brand: AKM

Model: AK7736BVQ

Type: Evaluation Board Manual

[AKD7736B-A]

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GENERAL DESCRIPTION

The AKD7736B-A is an evaluation board for the AK7736B that is an audio processor with a 2ch SRC. This

board consists of a main board and a sub board. It is possible to control by a PC via USB port. This board

has digital interfaces enabling to interface with digital audio systems via optical connector, ADC-Port,

DAC-Port and EXT-Port.

■ Ordering guide

AKD7736B-A --- AK7736B Evaluation board

The AK77XX-HF-CONTROL-BOX, Control software and USB cable are

included in this package.

FUNCTION

 Read/Write access to PRAM, CRAM, OFFRAM and registers of the AK7736B

 Compatible with 2 types of digital audio interface

- Optical input (x1) / Optical output (x1)

- 10-pin header (x2) and 44-pin header (x1) for interface with external data source

 USB port for board control

FPGA

(XC95288XL)

ADC DAC

10 Pin Header

Regulator

GND+3.3V

1.8V

CONTROL

Opt In

Opt Out

AK4118A

EXT

44 Pin Header

10 Pin Header

AK7736B

Figure 1. AKD7736B-A Block Diagram

AK7736B Evaluation Board Rev.0

AKD7736B-A

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Evaluation Board Diagram

■ Board Diagram

Figure 2. AKD7736B-A Board Diagram

(1)

(2)

(3) (5) (6)

(4)

(7)

(8)

(9)

(13)

(12)

(14)

(10)

(11)

(15)

(16)

(17)

(18)

(19)

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■ Description

No. Name Function

(1) AKD7736B-A-SUB Connector for the AKD7736B-A-SUB board.

(2) Interface select

(3-pin header x 13)

Interface selector of the AK7736B.

EXT: EXT port;

Xilinx: ADCport, DACport

No Name AK7736B

JP15 DI4 SDIN4

JP18 DI3 SDIN3

JP11 DI2C SDIN2C

JP10 DI2B SDIN2B

JP9 DI2A SDIN2A

JP8 DI1 SDIN1

JP20 LR3 LRCLKI3

JP19 BTI3 BITCLKI3

JP17 LR2 LRCLKI2/JX2

JP16 BTI2 BITCLKI2/JX1

JP14 LR1 LRCLK1

JP13 BT1 BITCLK1

JP12 XT1 XTI

(3) EXT port

J1 (44-pin header)

44-pin header for external interface

When using this connector, jumper pins of (2) must be shorted to Xilinx.

(4) XC95288XL

U6(xilinx)

FPGA for data path controlling

Various operations are available by setting the control software.

(5) DAC port

JP3 (10-pin header)

10-pin header for external interface

Interfacing to external digital audio devices.

Pin I/O Function Pin I/O Function

1 O MCLK 2 P GND

3 O BITCLK 4 P GND

5 O LRCLK 6 O SDTI1

7 - Open 8 O SDTI2

9 O SDTI4 10 O SDTI3

(6) ADC port

JP2 (10-pin header)

10-pin header for external interface

Interfacing to external digital audio devices.

Pin I/O Function Pin I/O Function

1 I/O MCLK 2 P GND

3 I/O BITCLK 4 P GND

5 I/O LRCLK 6 - Open

7 I SDTO1 8 - Open

9 I SDTO2 10 - open

(7) JTAG port

JP21(10-pin header)

10-pin header for Xilinx access

Do not use.

(8) CONTROL port

JP1 (10-pin header)

10-pin header for AK7736B control

Normally, connect the AKD77XX-HF-CONTROL-BOX to interface to a PC

via USB port.

Pin I/O Function Pin I/O Function

1 P GND 2 P +3.3V

3 I HOST 4 I RQN

5 I SCK/SCL 6 I SI

7 I/O XCS/SDA 8 O SO

9 I CSN 10 - RESET

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(9) 5 DIP Switches

DIP switches for the AK7736B pin setting (L/H).

No Name AK7736B

1 TESTI3 TESTI3(6 pin)

2 TESTI1 TESTI1(1 pin)

3 TESTI2 TESTI2(46 pin)

4 JX0 JX0(43 pin)

5 I2C I2CSEL(19 pin)

(10) VDD Jumper

JP6 (2-pin header)

Jumper pin for VDD power supply of the AK7736B.

Open: Supply from the VDD test pin

Short: +3.3V

(11) P-TVDD Jumper

JP5 (3-pin header)

Jumper pin for S2 and level shifter power supply

3.3VShort: +3.3V

1.8VShort: +1.8V

(12) Optical Connector

PORT1, PORT2

SPDIF-IN (Input): Optical digital signal (Fs: 8~48kHz) is input to the AK4118A.

SPDIF-OUT (Output): Optical digital signal (Fs: 8~48kHz) is output from the

AK4118A.

(13) AK4118A

AK4118A (Digital Audio Transceiver)

(14) 7 DIP Switches

DIP Switch for pin settings (L/H) of the AK4118A.

Refer to the “AK4118A Setting” for details

No Name AK4118A

1 CM0 CM0(32 pin)

2 CM1 CM1(33 pin)

3 OCKS0 OCKS0(35 pin)

4 OCKS1 OCKS1(34 pin)

5 DIF0 DIF0(3 pin)

6 DIF1 DIF1(5 pin)

7 DIF2 DIF2(7 pin)

(15) Toggle Switch

SW1

Toggle Switch for selecting clock source to the AK4118A-XTI.

XTL: Crystal Clock

TX-CLK: External Clock

(16) P-DVDD Jumper

JP7 (2-pin header)

Jumper Pin for selecting power supply to IC’s except the AK7736B.

Open: Supply from the P-DVDD test pin

Short: +3.3V

(17) +3.3V power supply

TM1

Power Supply Connector

Supply +3.3V.

(18) GND

TM2

Connect to GND

(19) TVDD Jumper

JP4 (2-pin header)

Jumper pin for selecting power supply to the TVDD pin of the AK7736B

Open: Supply from the TVDD test pin

Short: P-TVDD

Table 1. Main Board Functions (Bold: Default Setting)

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Evaluation Board Manual

■ Operation Sequence

(1) Set up the power supply lines.

[The jumper pins should be set as following]

JP4

TVDD

(Short)

JP6

VDD

(

Short

)

JP7

P-DVDD

(

Short

)

JP5

PIC-VDD-SEL

V3.3V

Set up the power supply lines.

ame Colo

Volta

e Commen

Attention

+3.3V Red +3.3V Regulator,

Input/Output buffe

Should always be connected.

GND Blac

0V Ground Should alwa

s be connected.

Table 2. Set Up of Power Supply Lines

Each supply line should be distributed separately from the power supply unit. The regulator on the board that

converts 3.3V to 1.8V can also supply TVDD of the AK7736B.

(2) Set up the evaluation mode, jumper pins and connectors. (according to the following section)

(3) Connect the board to a PC with a USB cable via the AKD77XX-HF-CONTROL-BOX (called

“CONTROL-BOX” hereafter) which is included in this package. It is required to push down the reset button

(yellow) of the CONTROL-BOX to initialize the USB control chip.

(4) Power On

(5) Start the control software and set up registers by PC. (according to the following section)

■ Evaluation Mode

In case of evaluating theAK7736B by using the AK4118A, it is necessary that audio interface format of both

devices are matched. Refer to the datasheet for audio interface format of the AK7736B, and refer to

“Jumper Pin and Switch Setting” for audio interface format of the AK4118A.

Applicable Evaluation Mode

(1) Digital-to-Digital Evaluation using ADC-Port and DAC-Port:

CKM Master Mode = 0/1

(2) Digital-to-Digital Evaluation using ADC-Port and DAC-Port:

CKM Slave Mode = 2/3/4/5

Refer to the “Control Software” section of this manual and the datasheet of the AK7736B for FPGA, the AK4118A

and control register setting of the AK7736B.

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(1) Digital-to-Digital Evaluation using ADC Port and DAC Port: CKM Master Mode = 0/1

ADC-Port and DAC-Port are used on this evaluation. Set the clock mode of the AK7736B to CKM Master Mode

0 (12.288MHz) or CKM Master Mode 1 (18.432MHz). The AK7736B outputs BICK and LRCK to the ADC-Port

and DAC-Port by setting the FPGA. The ADC-Port inputs data to the SDIN1, SDIN2A, SDIN2B, SDIN2C,

SDIN3 or SDIN4 pin. The DAC-Port output data from the SDOUT1, SDOUT2A, SDOUT2B, SDOUT3 or

SDOUT4 pin.

[Jumper Pins Setting]

JP1

XTI-SEL

CRY EXT

For digital output, optical connector PORT2 (SPDIF-OUT) is also available. The following setting must be made

and the FPGA setting should be changed when using the SPDIF-OUT instead of the DAC-Port. Refer to

“AK4118A Setting” for detail setting of the AK4118A.

Main Board

Jumper / Switch Setting (Default)

SW1 (AK4118A

Clock)

“TX-CLK”

S1(AK4118A Setting) 1->7=LHLLLHH

Table 3. Configuration of the AK4118A switch in Master Mode

(2) Digital-to-Digital Evaluation using ADC Port and DAC Port: CKM Slave Mode = 2/3/4/5

ADC-Port and DAC-Port are used on this evaluation. Set the clock mode of AK7736B to CKM Slave Mode

2/3/4/5. ADC-Port supplies MCLK, BICK, LRCK and digital data to the AK7736B. (MCLK is needed in CKM

Slave Mode 2 only)

[Jumper Pins Setting]

JP10

XTI-SEL

CRY EXT

(MCLK is needed in CKM Slave Mode 2 only)

For digital input and output, optical connector PORT1 (SPDIF-IN) and PORT2 (SPDIF-OUT) are available,

respectively. The following setting must be made and the FPGA setting should be changed when using these

connectors. Refer to “AK4118A Setting” for detail setting of the AK4118A.

Main Board

Jumper / Switch Setting (Default)

SW1 (AK4118A

Clock)

“XTL”

S1(AK4118A Setting) 1->7=LHLLLLH

Table 4. Configure the AK4118A switch at the Slave Mode

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■ Board control

The AKD7736B-A can be controlled by a PC via USB port. Connect the CONTROL-BOX included in this package to

the AKD7736B-A with a 10-pin flat cable, and connect the CONTROL-BOX to a PC with a USB cable. The 10-pin flat

cable should be connected in the direction that the side with a bump meets a marking, that says “CONTROL”, on the

main board of the AKD7736B-A.

Figure 1. Direction of the 10-pin Flat Cable

The interface setting is made by jumper pins of the CONTROL-BOX and the I2CSEL pin of the AK7736B.

SPI(Serial) Setting I2C Setting

Figure 2. Configuration of the CONTROL-BOX

Control software is different depending on the interface setting.

The software operation sequence is shown in this manual.

■ Indication for LED

[LED] D1: The status of AK7736B’s PDN pin is shown. “H” → Light off; “L” → Light on.

CONTROL

Open

Short

Open

Short

Open

Short

Open

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■ Jumper Pin and Switch Setting

Jumper / Switch Setting (Default) Note

SW1 (AK4118A

Clock)

“TX-CLK”

AK4118A Clock Source

“XTL”: Crystal Clock

“TX-CLK”: External Clock

S1(AK4118A Setting) 1->7=LHLLLHH Refer to “AK4118A Setting”

S2(AK7736B Setting) 1->5=LLLLL Refer to (9) in Table 1

JP4 (TVDD) Short AK7736B TVDD

JP5 (P-TVDD) “3.3V” Refer to (11) in Table 1

JP6 (VDD) Short AK7736B VDD

JP7 (P-DVDD) Short Peripheral DVDD

JP8 (DI1)

“Xilinx”

Refer to (2) in Table 1

JP9 (DI2A)

“Xilinx”

JP10 (DI2B)

“Xilinx”

JP11 (DI2C)

“Xilinx”

JP12 (XTI)

“Xilinx”

JP13 (BTI1)

“Xilinx”

JP14 (LR1)

“Xilinx”

JP15 (DI4)

“Xilinx”

JP16 (BTI2)

“Xilinx”

JP17 (LR2)

“Xilinx”

JP18 (DI3)

“Xilinx”

JP19 (BTI3)

“Xilinx”

JP20 (LR3)

“Xilinx”

Table 5. Setting of Jumper Pins on Main Board

Jumper/ Switch Setting (Default) Note

JP1 (XTI-SEL) “CRY”

AK7736B Clock Source

“

CRY”: Crystal Clock

“

EXT”: External Clock

Table 6. Setting of Jumper Pins on Sub Board

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OCKS1 OCKS0 MCKO1 MCKO2 X’tal Fs(max)

0 0 256fs L 256fs 96kHz default

0 1 256fs L 256fs 96kHz

1 0 512fs L 512fs 48kHz

1 1 128fs L 128fs 192kHz

Table 7. AK4118A-OCKS[1:0]

CM1 CM0

Clock

source

MCKO1 MCKO2 SDTO

0 0 PLL PLL L RX

0 1 X’tal X’tal X’tal DAUX

1 0 PLL PLL L RX default

1 1 X’tal X’tal X’tal DAUX

Table 8. AK4118A-CM[1:0]

DIF2 DIF1 DIF0 DAUX SDTO LRCK BICK

0 0 0 24bit,Left justified 16bit,Right justified H/L

64fs

0 0 1 24bit,Left justified 18bit,Right justified H/L

64fs

0 1 0 24bit,Left justified 20bit,Right justified H/L

64fs

0 1 1 24bit,Left justified 24bit,Right justified H/L

64fs

1 0 0 24bit,Left justified 24bit,Left justified L/H

64fs

1 0 1 24bit,I2S 24bit,I2S H/L

64fs

1 1 0 24bit,Left justified 24bit,Left justified L/H

64fs

default

1 1 1 24bit,I2S 24bit,I2S H/L

64fs

Table 9. AK4118A-DIF[2:0]

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■ Digital Input Circuit (External DIR: PORT1)

Figure 3. Digital Input Circuit

For digital input SPDIF-IN, optical connector PORT1 is available.

■ Digital Output Circuit (External DIT: PORT2)

Figure 4. Digital Output Circuit

For digital output SPDIF-OUT, optical connector PORT2 is available.

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Control Software Manual

■ Evaluation Board and Control Software Settings

(1) Set up the AKD7736B-A as needed, according to the previous terms.

(2) Connect the AKD7736B-A to a PC via the CONTROL BOX with a 10-pin flat cable on the evaluation board side

and a USB cable on the PC side. After power on the evaluation board, press the reset button (yellow) of the

CONTROL BOX to initialize the USB chip.

(3) Insert the CD-ROM labeled “AKD7736B-A Evaluation Kit” into the CD-ROM drive.

(4) Access the CD-ROM drive and double-click the icon of “AK7736B.exe” according to the interface setting to set

up the program. (AK7736B.exe: Control software of the AKD7736B-A)

(5) Begin evaluation by following the procedure below.

■ Operation Flow

Evaluation flow is shown below.

1. Start up the control program following the above procedure.

2. Open dialogues to set necessary settings for evaluation and evaluate the AK7736B.

(The control software must run again when disconnecting a USB control box from the PC.)

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■ Operation Screen

(1) Main Window

Figure 5. Startup Screen

Program download, register setting, FPGA setting and script processing are executed by this control software. These

controls may be selected by the upper tabs. Frequently used buttons, such as register initializing and control buttons are

located outside of the switching tab window. Supported control interface format is shown in the Control I/F box as

“Serial” (SPI) or “I2C”.

[JX]: JX Code Setting.

[Board Init]: Reset the evaluation board, and the register values set by the control software are written again.

[PDN Pin]: Power Down. The AK7736B is initialized.

[SRESET]: System Reset.

[DSP]: DSP Reset.

[CK]: Clock Reset.

Clock reset is required when changing the clock mode or the frequency of input clock without

power downing the AKD7736B. Register values are not initialized by this reset.

[DLRDY]: Down loads DSP programs. It is required when down loading a DSP program without system clocks.

[READ]: Reads out register values and shows them on the register column.

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(2) Download

Figure 6. [Download] Dialogue

Click each [refer] button next to the Source, Program, CRAM or OFREG column to select a file, or drag and drop a file to

the each column.

CRAM file or OFREG file can be selected and be written to CRAM or OFREG by clicking the [refer] button of CRAM

write@operation column or OFREG write@operation column when the system is running. The data will be written to

specific address of CRAM or OFREG when the [write] button at right side is clicked.

[Assemble]: Compiles a source file, and the output file will be selected as a download file automatically.

[Write]: Downloads the program to the AK7736B.

[Assemble Write]: Compiles a source file and then downloads the file to the AK7736B.

[PRAM read]: Reads out the PRAM data to a temporary file.

[CRAM read]: Reads out the CRAM data to a temporary file.

[OFREG read]: Reads out the OFREG data M to a temporary file.

[CRAM SAVE]: Reads out the CRAM data, and save them to a file.

[OFREG SAVE]: Reads out the OFREG data, and save them to a file.

[MICR1~4]: Reads out the register data of MICR1~4 during run, and shows them into the box next to each button.

[CRC-Check]: By checking this checkbox, simple error detection by CRC (cyclic redundancy check) is executed

when down loading a file.

[Auto RUN]: By checking this checkbox, the downloaded file will be run automatically when finish downloading.

If not checked, the AK7736B will be in system reset state when finish downloading.

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(3) Register Set up

Figure 7. [REG1] Dialogue

Tab dialogues of REG1/REG2/REG3/REG4 are used to set registers. (TEST and Reserved items are prohibited to

change.) As the checkbox is clicked, the data is written to the register. Release the reset state after setting CKM mode

since SRESET and CKRST are on by CKM mode setting.

Refer to the AK7736B’s datasheet for details of the register setting.

[AKD7736B-A]

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(4) FPGA Set up

Figure 8. [FPGA1] Dialogue

The FPGA1/FPGA2 dialogues are used to control the data path of the AK7736B.

FPGA Setting Table: (The default setting is shown in bold.)

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Bit Function Description

D[47:36] Reserved

D[35:34]

SEL20

EXT-XTI Input data source to the XTI pin of the AK7736B in Slave mode.

00: AK4118A-RX-CLK

01: ADC-MCLK

10: Low

11: Low

D[33]

SEL19

BICK1/LRCK1

In/Out

In/Out setting of the BITCLK1/LRCLK1 pin of the AK7736B.

0: output

1: input

D[32:31]

SEL18

BICK1/LRCK1 Input clock select to the BITCLK1/LRCLK1 pin of the

AK7736B.

00: AK4118A-BICK/LRCK

01: ADC-BICK/LRCK

10: Low

11: Low

D[30:29]

SEL17

BICK2/JX1 Input data source to the BITCLKI2/JX1 pin of the AK7736B.

00: AK4118A-BICK

01: ADC-BICK

10: Low

11: High

D[28:27]

SEL16

LRCK2/JX2 Input data source to the LRCLKI2/JX2 pin of the AK7736B.

00: AK4118A-LRCK

01: ADC-LRCK

10: Low

11: High

D[26:25]

SEL15

BICK3/LRCK3 Input clock to the BITCLKI3/LRCLKI3 pin of the AK7736B.

00: AK4118A-BICK/LRCK

01: ADC-BICK/LRCK

10: Low

11: Low

D[24:23]

SEL14

SDIN1 Input data source to the SDIN1 pin of the AK7736B.

00: AK4118A

01: ADC-SDTO1

10: ADC-SDTO2

11: Low

D[22:21]

SEL13

SDIN2A Input data source to the SDIN2A pin of the AK7736B.

00: AK4118A

01: ADC-SDTO1

10: ADC-SDTO2

11: Low

D[20:19]

SEL12

SDIN2B Input data source to the SDIN2B pin of the AK7736B.

00: AK4118A

01: ADC-SDTO1

10: ADC-SDTO2

11: Low

D[18:17]

SEL11

SDIN2C Input data source to the SDIN2C pin of the AK7736B.

00: AK4118A

01: ADC-SDTO1

10: ADC-SDTO2

11: Low

D[16:15]

SEL10

SDIN3 Input data source to the SDIN3 pin of the AK7736B.

00: AK4118A

01: ADC-SDTO1

10: ADC-SDTO2

11: Low

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D[14:13]

SEL9

SDIN4 Input data source to the SDIN4 pin of the AK7736B.

00: AK4118A

01: ADC-SDTO1

10: ADC-SDTO2

11: Low

D[12:11]

SEL8

CAD[1:0] The CAD pin setting of the AK7736B.

00: Low,Low

01: Low,High

10: High,Low

11: High,High

D[10]

SEL7

TRX-PDN The PDN pin setting of the AK4118A

0: Low

1: High

D[9]

SEL6

TX-CLK Input clock select to the XTI pin of the AK4118A.

0: AK7736B-CLKO

1: Low

D[8]

SEL5

TRX-BICK/LRCK

In/Out

In/Out setting of the BICK/LRCK pin of the AK4118A

0: output

1: AK7736B-BITCLKO/LRCLKO input

D[7:5]

SEL4

TX-DAT Input data source to the DAUX pin of the AK4118A

000: AK7736B-SDOUT1

001: AK7736B-SDOUT2A

010: AK7736B-SDOUT2B

011: AK7736B-SDOUT3

100: AK7736B-SDOUT4

101: Low

110: Low

111: Low

D[4]

SEL3

ADC-MCLK In/Out In/Out setting of the MCLK pin of the ADC-Port

0: MCLK output

1: AK7736B-CLKO input

D[3]

SEL2

ADC-BICK/LRCK

In/Out

In/Out setting of the BICK/LRCK pin of the ADC-Port

0: output

1: input

D[2:1]

SEL1

ADC-BICK/LRCK Input clock select to the BICK/LRCK pin of the ADC-Port

00: AK7736B-BITCLKO/LRCLKO

01: AK7736B-BITCLK1/LRCLK1

10: Low

11: Low

D[0]

SEL0

DAC-SDTI2 Input data source to the SDTI pin of the DAC-Port.

0: AK7736B-SDOUT2A

1: AK7736B-SDOUT2B

Table 10. FPGA

[AKD7736B-A]

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(5) Script

Figure 9. [SCRIPT] Dialogue

As a script file is selected, the program is executed automatically. By clicking the [Repeat] button, the selected script file

will be executed once again.

The script commands are listed below.

Command Description

[SCRIPT]

Header of script file. A data error will be detected without this header.

;Comment

The line following a semicolon is ignored as a comment.

W,< command>,<data>

W,0xC0,0x00

WL,<command>,<address>,<data>,…

WL,0x82,0x0022,0x4000,0x4000,0x4000

Continuous Data Write. This command can be used during CRAM run.

Command is byte assigned, the data is word assigned.

WS,<command>,<address>,<data>,…

WS,0x81,0x00,0x22,0x40,0x00,0x40,0x00

Continuous Data Write. This command can be used during CRAM run.

Command, address and data are byte assigned.

RI: H, RI: L RS: H, RS: L

RD: H, RD: L RC: H, RC: L

PDN control SRESET control

DSP-RESET control CKRESET control

X,<address>,<data>

FPGA register write command.

P,<message>

Displays a message and poses the script.

T,<wait>

T,50mS

Wait some micro seconds.

In an actual operation, it is possible to wait longer than this period.

LP:<filename>

Program file download to PRAM of the DSP.

LC:<filename>

Coefficient file download to CRAM of the DSP.

LO:<filename>

Off-set file download to OFREG of the DSP.

Table 11. Script Command

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REVISION HISTORY

Date

(yy/mm/dd)

Manual

Revision

Board

Revision

Reason Page Contents

12/07/27 KM110501 0 First edition

12/12/10 KM113102 0 Renamed AK7736 -> AK7736A

13/08/21 KM115102 0 Renamed AK7736A -> AK7736B

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IMPORTANT NOTICE

0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information

contained in this document without notice. When you consider any use or application of AKM product

stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized

distributors as to current status of the Products.

1. All information included in this document are provided only to illustrate the operation and application

examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy

or completeness of the information contained in this document nor grants any license to any intellectual

property rights or any other rights of AKM or any third party with respect to the information in this

document. You are fully responsible for use of such information contained in this document in your product

design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR

THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT

DESIGN OR APPLICATIONS.

2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily

high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human

life, bodily injury, serious property damage or serious public impact, including but not limited to,

equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment,

equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment,

equipment used to control combustions or explosions, safety devices, elevators and escalators, devices

related to electric power, and equipment used in finance-related fields. Do not use Product for the above use

unless specifically agreed by AKM in writing.

3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for

complying with safety standards and for providing adequate designs and safeguards for your hardware,

software and systems which minimize risk and avoid situations in which a malfunction or failure of the

Product could cause loss of human life, bodily injury or damage to property, including data loss or

corruption.

4. Do not use or otherwise make available the Product or related technology or any information contained in

this document for any military purposes, including without limitation, for the design, development, use,

stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology products

(mass destruction weapons). When exporting the Products or related technology or any information

contained in this document, you should comply with the applicable export control laws and regulations and

follow the procedures required by such laws and regulations. The Products and related technology may not

be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited

under any applicable domestic or foreign laws or regulations.

5. Please contact AKM sales representative for details as to environmental matters such as the RoHS

compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations

that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS

Directive. AKM assumes no liability for damages or losses occurring as a result of noncompliance with

applicable laws and regulations.

6. Resale of the Product with provisions different from the statement and/or technical features set forth in this

document shall immediately void any warranty granted by AKM for the Product and shall not create or

extend in any manner whatsoever, any liability of AKM.

7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written

consent of AKM.

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AKM AK7736BVQ Evaluation Board Manual

AKM AK7736BVQ Evaluation Board Manual

AKM AK7736BVQ Evaluation Board Manual

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