AKM AK5720VT Evaluation Board Manual

AKM
Brand
AKM
Model
AK5720VT
Type
Evaluation Board Manual
ASAHI KASEI [AKD5720-A]
KM113601 2013/10
GENERAL DESCRIPTION
AKD5720-A is an evaluation board for AK5720 which is low voltage 24bit analog-digital converter
developed for digital audio system. It supports Jacks for analog signal input.
This board also has a digital interface and can achieve the interface with a digital audio system through an
optical connector.
Ordering guide
AKD5720-A --- Evaluation board for AK5720
FUNCTION
AK5720
PORT2
DOUT(OPT)
VA
DIT
(AK4118A)
SDTO
VD
VSS
PORT1
DOUT(DSP)
X’tal
DGNDREG AK4118a 3.3V
MCLK
BICK
LRCK
512fs
256fs
BICK
LRCK
DAUX
LIN
RIN
LIN
RIN
VSS
VA
VD
T1
(LDO 5V)
T
5
(LDO 3.3V)
T
2
(LDO 3V)
T
3
(LDO 5V)
T
4
(LDO 3V)
Figure 1. AKD5720-A Block Diagram
AK5720 Evaluation Board Rev.1
- 1-
ASAHI KASEI [AKD5720-A]
KM113601 2013/10
Board Outline Chart
Outline Chart
JP11
JP10
JP9
J2 J1J4
J6
J5 J3 J7 J8
JP6
JP14
JP12
JP1
JP2
JP7
JP8
JP13
Port1
Port2
SW1
SW3
SW2
U3
U4
U1
JP5
JP3
JP4
T1
T2
T3
T4
Figure 2. Outline Chart
Description
(1) J1,J2（Analog data ）
RCA jack, Used for Analog audio input.
(2) J3,J4, J5, J6, J7,J8(Power supply)
The Ak5720 can be powered by external power supply or by Regulator (T1, T2, T3, T4) on the evaluation board.
(3) PORT1（10pin header）
10pin header (MCLK, BICK, LRCK, SDTO, TDMI)
(4) PORT2（Digital Data）
SPDIF output (Optical output connector.)
(5) U1(AK5720)
Low voltage 24bit analog-digital converter.
(6) U2（AK4118A）
AK4118A is DIT, which transmits digital data of AK5720.
(7) SW1(Toggle switch)
Power down of AK5720
“H” ：PDN of AK5720 is Hi.
“L” ：PDN of AK5720 is Lo.
(8) SW2(Toggle switch)
Power down of AK4118A
“H” ：PDN of AK4118A is Hi.
“L” ：PDN of AK4118A is Lo.
(9) SW3(Dip switch)
Setting of AK5720 and AK4118A
See Table4.
- 2-
ASAHI KASEI [AKD5720-A]
KM113601 2013/10
(10) JP1, JP2, JP3, JP4
Setting of audio interface format of AK5720
(11) JP5
Setting of digital filter of Ak5720
(12) JP6
Setting of input gain of AK5720
(13) JP7
Setting of AK4118a
(14) JP8
Setting of AK4118a
(15) JP9, JP10, JP11, JP12, JP13, JP14
Setting of power supply of AK5720 and AK4118a
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ASAHI KASEI [AKD5720-A]
KM113601 2013/10
Evaluation Board Manual
Operation Sequence
1) Set up the Power Supply Lines.
2) Setup the Audio I/F Evaluation Mode.
(1) Evaluation of A/D using DIT of AK4118A.
(1-1) Slave Mode (Default)
(1-2) Master Mode
(1-3) PLL Slave Mode
(2) Evaluation of A/D using external clock.
(2-1) Slave Mode
(2-2) Master Mode
(2-3) PLL Slave Mode
3) Jumper pins and SW Setting.
(1) Setting of other jumper pins
(2) Setting of SW
4) Power on
- 4-
ASAHI KASEI [AKD5720-A]
KM113601 2013/10
1) Set up the power Supplies
JP9 (SEL_VA): When VA is supplied from the regulator.
・JP9 5V : VA is supplied 5V. <Default>
3V : VA is supplied 3V.
JP10 (SEL_VD): When VD is supplied from the regulator.
・JP10 5V : VD is supplied 5V. <Default>
3V : VD is supplied 3V.
JP11 (VD): VD line and VA line are set common or separation.
・JP11 VA : VD line and VA line are set common.
VD : VD line and VA line are set separation.
OPEN : VD is not supplied from the regulator. <Default>
JP12 (VA): VA is supplied from the regulator.
・JP12 OPEN : VA is not supplied from the regulator. <Default>
SHORT : VA is supplied from the regulator.
JP13 (4118a_3.3V): When power supply of AK4118A is supplied from the regulator.
・JP13 OPEN : Power supply of AK4118A is not supplied from the regulator. <Default>
SHORT : Power supply of AK4118A is supplied from the regulator.
JP14 : VSS and DGND are set common or separation.
・JP14 OPEN : VSS and DGND are set common.
SHORT : VSS and DGND are set separation. <Default>
(1) When VA, VD and 4118a_3.3V are supplied from the regulator. <Default>
Set up the power supply lines
Name Color Setting Comments
VA Red Open Not used. Supplied through regulator
VD Red Open Not used. Supplied through regulator
VSS Black 0V Ground for AK5720
4118a_3.3V Red Open Not used. Supplied through regulator
DGND Black 0V Ground for AK4118a
REG Yellow +7V Power supply for the regulator.
Table 1 Setup of power supply (Used regulator)
Jumper Setting
Table 2 Setting of VA=VD=5V Table 3 Setting of VA=VD=3V
(2) When VA, VD and 4118a_3.3V are supplied from the power supply connectors.
Name Setting
JP9 Short on 5V side
JP10 Short on 5V side
JP11
VA : VD line and VA line are set common.
VD : VD line and VA line are set separation .
JP12 Short
JP13 Short
Name Setting
JP9 Short on 3V side
JP10 Short on 3V side
JP11
VA : VD line and VA line are set common.
VD : VD line and VA line are set separation .
JP12 Short
JP13 Short
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ASAHI KASEI [AKD5720-A]
KM113601 2013/10
Set up the power supply lines
Name Color Setting Comments
VA Red +2.7～+5.5V Power supply for VA of AK5720.
VD Red +2.7～VA V Power supply for VD of AK5720.
VSS Black 0V Ground for AK5720.
4118a_3.3V Red +3.3V Power supply for AK4118a.
DGND Black 0V Ground for AK4118a.
REG Yellow Open Not used.
Table 4 Setup of power supply (Not used regulator)
Jumper Setting
Table 5 Setting of VA=VD Table 6 Setting of VA≠VD
Name Setting
JP9 Open
JP10 Open
JP11 Short on VA side
JP12 Short
JP13 Open
Name Setting
JP9 Open
JP10 Open
JP11 Short on VD side
JP12 Open
JP13 Open
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ASAHI KASEI [AKD5720-A]
KM113601 2013/10
2) Setup the Audio I/F Evaluation Mode
In case of using the AK4118A when evaluating the AK5720, the audio interface format of the AK5720 and
AK4118A must be matched.
Refer to audio interface format of AK5720 (Table 7, Table 8), and audio interface format of AK4118A (Table 10).
The AK4118A operates at sampling frequency of 32 kHz or more. If the sampling frequency is lower than 32 kHz,
please use other mode.
Refer to the datasheet for register setting of the AK5720.
(1) Evaluation of A/D using DIT of AK4118A
(1-1) Slave Mode. (Default).
PORT2 (TOTX) is used
・PORT1: Open
・AK5720: Slave mode
・Setting of JP1, JP2, JP3, JP4 : See Table 7.
・AK4118A: Master mode
・SW3(4118-DIF1) : “Lo”
Mode
JP1
(VA/
GND)
JP2 (CKS)
JP4
(DIF/
TDMI)
JP3
(DIF)
SDTO
Master/
Slave
MCLK BICK
DIF
L MSB
GND
Short on 1 side
（Short to GND）
DIF
H I
2
S
Slave
256/384fs (8kfs96k)
512/768fs (8kfs48k)
48fs or
32fs
DIF
L MSB
VA
Short on 1 side
（Short to VA）
DIF
H I
2
S
Master
256fs (8kfs96k)
64fs
DIF
L MSB
GND
Short on 2 side
（4.7kΩ±10% to GND）
DIF
H I
2
S
Master
384fs (8kfs96k)
64fs
DIF
L MSB
Norma
l
VA
Short on 2 side
（4.7kΩ±10% to VA）
DIF
H I
2
S
Master
512fs (8kfs48k)
64fs
GND
Short on 3 side
（18kΩ±10% to GND）
TDMI MSB Master
256fs (8kfs96k)
256fs
VA
Short on 3 side
（18kΩ±10% to VA）
TDMI MSB Slave
256fs (8kfs96k)
256fs
GND
Short on 4 side
（82kΩ±10% to GND）
TDMI I
2
S Master
256fs (8kfs96k)
256fs
TDM
VA
Short on 4 side
（82kΩ±10% to VA）
TDMI I
2
S Slave
256fs (8kfs96k)
256fs
Table 7 Slave Mode (Setting of JP1,JP2, JP3, JP4)
MCLK, BICK and LRCK are supplied from AK4118A to AK5720. PORT2 outputs optical data of AK5720
through AK4118A. MCLK can be selected between 512fs and 256fs by JP7.
H
L
4118
-DIF1
SW 3
AK4118a
Master/Slave Select
JP7
EXT
256fs
512fs
EXT
256fs
512fs
OR
MCLK Select
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ASAHI KASEI [AKD5720-A]
KM113601 2013/10
(1-2) Master Mode
PORT2 (TOTX) is used
・PORT1: Open
・AK5720: Master mode
・Setting of JP1, JP2, JP3, JP4 : See Table 8.
・AK4118A: Slave mode
・SW3(4118-DIF1) : “Hi”
Mode
JP1
(VA/
GND)
JP2 (CKS)
JP4
(DIF/
TDMI)
JP3
(DIF)
SDTO
Master/
Slave
MCLK BICK
DIF
L MSB
GND
Short on 1 side
（Short to GND）
DIF
H I
2
S
Slave
256/384fs (8kfs96k)
512/768fs (8kfs48k)
48fs or
32fs
DIF
L MSB
VA
Short on 1 side
（Short to VA）
DIF
H I
2
S
Master
256fs (8kfs96k)
64fs
DIF
L MSB
GND
Short on 2 side
（4.7kΩ±10% to GND）
DIF
H I
2
S
Master
384fs (8kfs96k)
64fs
DIF
L MSB
Norma
l
VA
Short on 2 side
（4.7kΩ±10% to VA）
DIF
H I
2
S
Master
512fs (8kfs48k)
64fs
GND
Short on 3 side
（18kΩ±10% to GND）
TDMI MSB Master
256fs (8kfs96k)
256fs
VA
Short on 3 side
（18kΩ±10% to VA）
TDMI MSB Slave
256fs (8kfs96k)
256fs
GND
Short on 4 side
（82kΩ±10% to GND）
TDMI I
2
S Master
256fs (8kfs96k)
256fs
TDM
VA
Short on 4 side
（82kΩ±10% to VA）
TDMI I
2
S Slave
256fs (8kfs96k)
256fs
Table 8 Master Mode (Setting of JP1,JP2, JP3, JP4)
MCLK is supplied from AK4118A or external input to AK5720. LRCK, BICK, SDTO of AK5720 are outputs to
AK4118A. PORT2 outputs optical data of AK5720 through AK4118A. MCLK can be selected between 512fs
and 256fs by JP10.
H
L
-DIF1
SW3
AK4118a
Master/Slave Select
JP7
OR
MCLK Select
OR
GND
External clock input
- 8-
ASAHI KASEI [AKD5720-A]
KM113601 2013/10
(2) Evaluation of A/D using external clock.
(2-1) Slave Mode
PORT1 (DSP) is used.
・SW2: “Lo” (AK4118A is not used)
・AK5720: Slave mode
・Setting of JP1, JP2, JP3, JP4 : See Table 7
・SW3(4118-DIF1) : “Lo”
MCLK, BICK and LRCK are supplied from PORT1 to AK5720. SDTO of AK5720 is output to PORT1
H
L
4118
-DIF1
SW3
Master/SlaveSelect
H
L
4118
-PDN
SW2
PDN of AK4118A
MCLK
PORT1
BICK
LRCK
SDTO
TDM
2
9
10
GND
GND
GND
GND
PORT1
(2-2) Master Mode
PORT1 (DSP) is used.
・SW2: “Lo” (AK4118A is not used)
・AK5720: Master mode
・Setting of JP1, JP2, JP3, JP4 : See Table 8
・SW3(4118-DIF1) : “Lo”
MCLK is supplied from PORT1. LRCK, BICK , SDTO of AK5720 is output to PORT1.
H
L
4118
-DIF1
SW3
Master/SlaveSelect
H
L
4118
-PDN
SW2
PDN of AK4118A
MCLK
PORT1
BICK
LRCK
SDTO
TDM
2
9
10
GND
GND
GND
GND
PORT1
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ASAHI KASEI [AKD5720-A]
KM113601 2013/10
3) Jumper pins and SW Setting
(1) Setting of other jumper pins.
JP5 (FSEL): Setting of digital-filter of AK5720.
・JP5 L : Sharp Roll-Off. < Default >
H : Short Delay Sharp Roll-Off.
JP6 (GSEL): Setting of input gain of AK5720.
・JP6 L : 0dB. < Default >
H : +6dB.
JP8 : The selection of OPEN or SHORT of SDTO line, BICK line, LRCK line for AK4118A.
・JP8 SDTO : SHORT < Default >
BICK : SHORT < Default >
LRCK : SHORT < Default >
(2) Setting of SW
[SW3] (SW DIP-4): Mode setting for AK4118A.
No. Name ON (“H”) OFF (“L”) Default
1 4118-DIF1 OFF
2 4118-DIF0
See Table 10
ON
3 4118-OCKS0 OFF
4 4118-OCKS1
See Table 11
ON
Table 9 Mode setting for AK4118A
LRCK BICK
4118-
DIF1
4118-
DIF0
Mode DAUX SDTO
I/O I/O
L L
Master Mode 24bit, Left justified 24bit, Left justified H/L O
64ｆｓ
O
L H
Master Mode 24bit, I
2
S 24bit, I
2
S L/H O
64ｆｓ
O
H L
Slave Mode 24bit, Left justified 24bit, Left justified H/L I
64-128ｆｓ
I
H H
Slave Mode 24bit, I
2
S 24bit, I
2
S L/H I
64-128ｆｓ
I
Table 10 Audio I/F Format Setting for AK4118A
No. OCKS1 OCKS0
MCKO1 MCKO2 X’tal fs (max)
0 0 0 256fs 256fs 256fs 96 kHz
1 0 1 256fs 128fs 256fs 96 kHz
2 1 0 512fs 256fs 512fs 48 kHz (Default)
3 1 1 128fs 64fs 128fs 192 kHz
Table 11 Master Clock setting for AK4118A
- 10-
ASAHI KASEI [AKD5720-A]
KM113601 2013/10
4) Power on
[SW1] (5720-PDN) : The AK5720 should be reset once bringing “L” upon power-up.
Keep “H” during normal operation.
[SW2] (4118a-PDN) : The AK4118A should be reset once bringing “L” upon power-up.
Keep “H” during normal operation.
- 11-
ASAHI KASEI [AKD5720-A]
KM113601 2013/10
Revision History
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the accuracy
or completeness of the information contained in this document nor grants any license to any intellectual
property rights or any other rights of AKM or any third party with respect to the information in this
document. You are fully responsible for use of such information contained in this document in your product
design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES INCURRED BY YOU OR
THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION IN YOUR PRODUCT
DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require extraordinarily
high levels of quality and/or reliability and/or a malfunction or failure of which may cause loss of human
life, bodily injury, serious property damage or serious public impact, including but not limited to,
equipment used in nuclear facilities, equipment used in the aerospace industry, medical equipment,
equipment used for automobiles, trains, ships and other transportation, traffic signaling equipment,
equipment used to control combustions or explosions, safety devices, elevators and escalators, devices
related to electric power, and equipment used in finance-related fields. Do not use Product for the above use
unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or
corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained in
this document for any military purposes, including without limitation, for the design, development, use,
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(mass destruction weapons). When exporting the Products or related technology or any information
contained in this document, you should comply with the applicable export control laws and regulations and
follow the procedures required by such laws and regulations. The Products and related technology may not
be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under
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5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and regulations
that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS
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6. Resale of the Product with provisions different from the statement and/or technical features set forth in this
document shall immediately void any warranty granted by AKM for the Product and shall not create or
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7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
consent of AKM.
Date
(yy/mm/dd)
Manual
Revision
Board
Revision
Reason Page Contents
13/10/09 KM113600 0 First Edition
13/10/15 KM113601 1
Specifications
change
7,8 CKS Setting Changed
- 12-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AGND AGND
AGND
AGND
AGND
AGND
5720-FSEL
5720-DIF / TDMI
5720-PDN
BICK
MCLK
LRCK
VD
VA
5720-GSEL
5720-CKS
SDTO
VA
Title
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Date: Sheet of
ak5720
1
AKD5720-a
A4
1 4Tuesday, October 15, 2013
Title
Size Document Number Rev
Date: Sheet of
ak5720
1
AKD5720-a
A4
1 4Tuesday, October 15, 2013
Title
Size Document Number Rev
Date: Sheet of
ak5720
1
AKD5720-a
A4
1 4Tuesday, October 15, 2013
TP7 GSEL C7
0.1u
TP8 REGO
TP17
AGND
+
C6
10u
R1 51
TP3 LIN
R4 51
TP4 VSS
R7
OPEN
TP1 VCOM
+
C2 10u
TP16 CKS
+
C1
0.47u
TP13 DIF_TDMI
CN2
16pin_R
9
10
11
12
13
14
15
16
TP6 VD
R6
OPEN
TP15 FSEL
TP9 SDTO
+
C8
1u
TP11 MCLK
AK5720
U1
VCOM
1
RIN
2
LIN
3
VSS
4
VA
5
VD
6
GSEL
7
REGO
8
SDTO
9
LRCK
10
MCLK
11
BICK
12
PDN
13
DIF / TDMI
14
FSEL
15
CKS
16
R3 51
TP10 LRCK
TP5 VA
J1
RIN
12
3
4
5
TP14 DIF_TDMI
+
C4
10u
C5
0.1u
+
C3 10u
TP12 BICK
R2 51
J2
LIN
12
3
4
5
TP18
AGND
R5 51
TP2 RIN
CN1
16pin_L
1
2
3
4
5
6
7
8
- 13-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
L
H
HL
VA
GND
H
H
L
L TDMI
DIF
AGND
AGND
AGND
AGND
AGND
AGND
5720-GSEL
VD
5720-PDN
VD
VD
VA
5720-CKS
VD
5720-DIF / TDMI
VD
5720-FSEL
5720-TDMI
Title
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Logic 1
AKD5720-a
A4
2 4Tuesday, October 15, 2013
Title
Size Document Number Rev
Date: Sheet of
Logic 1
AKD5720-a
A4
2 4Tuesday, October 15, 2013
Title
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Date: Sheet of
Logic 1
AKD5720-a
A4
2 4Tuesday, October 15, 2013
R9
4.7k
SW1
5730-PDN
2
1
3
JP5
R11
82k
JP6
JP4
C10
0.1u
C9
0.1u
R13 0
JP1 JP2
JUMPER_4
D1
HSU119
KA
JP3
R8
0
U2
SN74LVC2G14
1A
1
GND
2
2Y
4
VCC
5
2A
3
1Y
6
R10
18k
R12
10k
- 14-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XTL512fs
XTL256fs
EXT
SDTO
BICK
LRCK
H
L
SDTO
LRCK
BICK
TDMI
MCLK
L H
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
DGND
BICK
LRCK
MCLK
SDTO
4118-OCKS0
4118_3.3V4118-DIF1
4118-DIF0
4118_3.3V
4118_3.3V
4118-OCKS1
4118_3.3V
4118-PDN
5720-TDMI
4118-OCKS1
4118-DIF0
4118-DIF1
4118-OCKS0
4118_3.3V
4118_3.3V
4118-PDN
4118_3.3V
Title
Size Document Number Rev
Date: Sheet of
DIT 1
AKD5720-a
A3
3 4Tuesday, October 15, 2013
Title
Size Document Number Rev
Date: Sheet of
DIT 1
AKD5720-a
A3
3 4Tuesday, October 15, 2013
Title
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Date: Sheet of
DIT 1
AKD5720-a
A3
3 4Tuesday, October 15, 2013
C21
0.1u
JP7
JMP2x3
C15
10p
+
C18
10u
R14
10k
PORT1
10PIN-PORT
1
3
5
7
9 10
8
6
4
2
PORT2
TX
GND
1
VCC
2
IN
3
SW3
SW DIP-4
1
2
3
4
8
7
6
5
RP1
R-PACK4R
4
3
2
1
U3
IPS0/RX4
1
NC
2
DIF0/RX5
3
TEST2
4
DIF1/RX6
5
VSS1
6
DIF2/RX7
7
IPS1/IIC
8
P/SN
9
XTL0
10
XTL1
11
TVDD
13
NC/GP1
14
TX0/GP2
15
TX1/GP3
16
BOUT/GP4
17
COUT/GP5
18
UOUT/GP6
19
VOUT/GP7
20
DVDD
21
VSS2
22
MCKO1
23
BICK
26
MCKO2
27
DAUX
28
XTO
29
XTI
30
PDN
31
CM0/CDTO/CAD1
32
CM1/CDTI/SDA
33
OCKS1/CCLK/SCL
34
OCKS0/CSN/CAD0
35
INT0
36
AVDD
38
R
39
VCOM
40
VSS3
41
RX0
42
NC
43
RX1
44
TEST1
45
RX2
46
VSS4
47
RX3
48
VIN/GP0
12
LRCK
24
SDTO
25
INT1
37
C22
0.1u
U5
SN74LVC2G14
1A
1
GND
2
2Y
4
VCC
5
2A
3
1Y
6
C17
0.1u
C12
0.1u
D2
HSU119
KA
+
C19
10u
JP8
JMP2x3
SW2
4118-PDN
2
1
3
+
C11 10u
C14
10p
C13
0.47u
R15
10k
C20
0.1u
X1
24.576MHz
12
C16
0.1u
- 15-
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DGNDVSS
5V
3V
5V
3V
VD VA
VD=VA
AK4118_3.3V
AGND
+7V
+7V
DVDD
AVDD
AVDD
AGND
AGND
AGND
AGND
DVDD
AK4118_3.3V
AGND
DGND
DGND
AGND
AGND
AGND
DGND
DGND
AGND
AGND
VA
VD
4118_3.3V
Title
Size Document Number Rev
Date: Sheet of
Power Supply 1
AKD5720-a
A4
4 4Tuesday, October 15, 2013
Title
Size Document Number Rev
Date: Sheet of
Power Supply 1
AKD5720-a
A4
4 4Tuesday, October 15, 2013
Title
Size Document Number Rev
Date: Sheet of
Power Supply 1
AKD5720-a
A4
4 4Tuesday, October 15, 2013
+
C38
10u
J5
VD
1
R17
160
+
C24
10u
C26
0.1u
+
C29
10u
+
C45
10u
C43
0.1u
J6
VSS
1
+
C34
10u
J7
AK4118a_3.3V
1
JP12
VA
R18
120
J4
VA
1
J8
DGND
1
+
C27
10u
T4
LM1117IDTX-ADJ
OUT
2
GND
1
IN
3
JP10
VD 5 / 3 V
C36
0.1u
T2
LM1117IDTX-ADJ
OUT
2
GND
1
IN
3
+
C42
10u
J3
REG
1
R19
160
JP11
VD
+
C23
47u
C39
0.1u
T1
LM1117IDTX-5.0
OUT
2
GND
1
IN
3
+
C33
47u
12
R20 8.2
C30
0.1u
+
C37
10u
+
C46
47u
12
C40
0.1u
R16
120
JP9
VA 5 / 3 V
JP14
GND
C44
0.1u
C31
0.1u
JP13
4118_3.3V
T3
LM1117IDTX-5.0
OUT
2
GND
1
IN
3
C25
0.1u
+
C41
10u
R21 8.2
+
C28
47u
12
+
C32
10u
T5
LM1117IDTX-3.3
OUT
2
GND
1
IN
3
C35
0.1u
- 16-
AKD5720-A Rev.1 Pattern View Silk View of Component Side
（Perspective View of Component Side）
U4, C47, C48： No mount
- 17-
AKD5720-A Rev.1 Pattern View Silk View of Solder Side
（Perspective View of Component Side ）
- 18-
AKD5720-A Rev.1 Pattern View Pattern View of Component Side
（Perspective View of Component Side）
- 19-
AKD5720-A Rev.1 Pattern View Pattern View of Solder Side
（Perspective View of Component Side ）
Jumper Line
- 20-
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  • Page 16 16
  • Page 17 17
  • Page 18 18
  • Page 19 19
  • Page 20 20

AKM AK5720VT Evaluation Board Manual

AKM
Brand
AKM
Model
AK5720VT
Type
Evaluation Board Manual
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