AKM AK7736AVQ Evaluation Board Manual

Brand: AKM

Model: AK7736AVQ

Type: Evaluation Board Manual

[AKD7736A-A]

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GENERAL DESCRIPTION

The AKD7736A-A is an evaluation board for the AK7736A that is an audio processor with a 2ch SRC. This

board consists of a main board and a sub board. It is possible to control by a PC via USB port. This board

has digital interfaces enabling to interface with digital audio systems via optical connector, ADC-Port,

DAC-Port and EXT-Port.

■ Ordering guide

AKD7736A-A --- AK7736A Evaluation board

The AK77XX-HF-CONTROL-BOX, Control software and USB cable are

included in this package.

FUNCTION

 Read/Write access to PRAM, CRAM, OFFRAM and registers of the AK7736A

 Compatible with 2 types of digital audio interface

- Optical input (x1) / Optical output (x1)

- 10-pin header (x2) and 44-pin header (x1) for interface with external data source

 USB port for board control

FPGA

(XC95288XL)

ADC DAC

10 Pin Header

Regulator

GND+3.3V

1.8V

CONTROL

Opt In

Opt Out

AK4118A

EXT

44 Pin Header

10 Pin Header

AK7736A

Figure 1. AKD7736A-A Block Diagram

AK7736A Evaluation Board Rev.0

AKD7736A-A

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Evaluation Board Diagram

■ Board Diagram

Figure 2. AKD7736A-A Board Diagram

(1)

(2)

(3) (5) (6)

(4)

(7)

(8)

(9)

(13)

(12)

(14)

(10)

(11)

(15)

(16)

(17)

(18)

(19)

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■ Description

No. Name Function

(1) AKD7736A-A-SUB Connector for the AKD7736A-A-SUB board.

(2) Interface select

(3-pin header x 13)

Interface selector of the AK7736A.

EXT: EXT port;

Xilinx: ADCport, DACport

No Name AK7736A

JP15 DI4 SDIN4

JP18 DI3 SDIN3

JP11 DI2C SDIN2C

JP10 DI2B SDIN2B

JP9 DI2A SDIN2A

JP8 DI1 SDIN1

JP20 LR3 LRCLKI3

JP19 BTI3 BITCLKI3

JP17 LR2 LRCLKI2/JX2

JP16 BTI2 BITCLKI2/JX1

JP14 LR1 LRCLK1

JP13 BT1 BITCLK1

JP12 XT1 XTI

(3) EXT port

J1 (44-pin header)

44-pin header for external interface

When using this connector, jumper pins of (2) must be shorted to Xilinx.

(4) XC95288XL

U6(xilinx)

FPGA for data path controlling

Various operations are available by setting the control software.

(5) DAC port

JP3 (10-pin header)

10-pin header for external interface

Interfacing to external digital audio devices.

Pin I/O Function Pin I/O Function

1 O MCLK 2 P GND

3 O BITCLK 4 P GND

5 O LRCLK 6 O SDTI1

7 - Open 8 O SDTI2

9 O SDTI4 10 O SDTI3

(6) ADC port

JP2 (10-pin header)

10-pin header for external interface

Interfacing to external digital audio devices.

Pin I/O Function Pin I/O Function

1 I/O MCLK 2 P GND

3 I/O BITCLK 4 P GND

5 I/O LRCLK 6 - Open

7 I SDTO1 8 - Open

9 I SDTO2 10 - open

(7) JTAG port

JP21(10-pin header)

10-pin header for Xilinx access

Do not use.

(8) CONTROL port

JP1 (10-pin header)

10-pin header for AK7736A control

Normally, connect the AKD77XX-HF-CONTROL-BOX to interface to a PC

via USB port.

Pin I/O Function Pin I/O Function

1 P GND 2 P +3.3V

3 I HOST 4 I RQN

5 I SCK/SCL 6 I SI

7 I/O XCS/SDA 8 O SO

9 I CSN 10 - RESET

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(9) 5 DIP Switches

DIP switches for the AK7736A pin setting (L/H).

No Name AK7736A

1 TESTI3 TESTI3(6 pin)

2 TESTI1 TESTI1(1 pin)

3 TESTI2 TESTI2(46 pin)

4 JX0 JX0(43 pin)

5 I2C I2CSEL(19 pin)

(10) VDD Jumper

JP6 (2-pin header)

Jumper pin for VDD power supply of the AK7736A.

Open: Supply from the VDD test pin

Short: +3.3V

(11) P-TVDD Jumper

JP5 (3-pin header)

Jumper pin for S2 and level shifter power supply

3.3VShort: +3.3V

1.8VShort: +1.8V

(12) Optical Connector

PORT1, PORT2

SPDIF-IN (Input): Optical digital signal (Fs: 8~48kHz) is input to the AK4118A.

SPDIF-OUT (Output): Optical digital signal (Fs: 8~48kHz) is output from the

AK4118A.

(13) AK4118A

AK4118A (Digital Audio Transceiver)

(14) 7 DIP Switches

DIP Switch for pin settings (L/H) of the AK4118A.

Refer to the “AK4118A Setting” for details

No Name AK4118A

1 CM0 CM0(32 pin)

2 CM1 CM1(33 pin)

3 OCKS0 OCKS0(35 pin)

4 OCKS1 OCKS1(34 pin)

5 DIF0 DIF0(3 pin)

6 DIF1 DIF1(5 pin)

7 DIF2 DIF2(7 pin)

(15) Toggle Switch

SW1

Toggle Switch for selecting clock source to the AK4118A-XTI.

XTL: Crystal Clock

TX-CLK: External Clock

(16) P-DVDD Jumper

JP7 (2-pin header)

Jumper Pin for selecting power supply to IC’s except the AK7736A.

Open: Supply from the P-DVDD test pin

Short: +3.3V

(17) +3.3V power supply

TM1

Power Supply Connector

Supply +3.3V.

(18) GND

TM2

Connect to GND

(19) TVDD Jumper

JP4 (2-pin header)

Jumper pin for selecting power supply to the TVDD pin of the AK7736A

Open: Supply from the TVDD test pin

Short: P-TVDD

Table 1. Main Board Functions (Bold: Default Setting)

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Evaluation Board Manual

■ Operation Sequence

(1) Set up the power supply lines.

[The jumper pins should be set as following]

JP4

TVDD

(Short)

JP6

VDD

(

Short

)

JP7

P-DVDD

(

Short

)

JP5

PIC-VDD-SEL

V3.3V

Set up the power supply lines.

ame Colo

Volta

e Commen

Attention

+3.3V Red +3.3V Regulator,

Input/Output buffe

Should always be connected.

GND Blac

0V Ground Should alwa

s be connected.

Table 2. Set Up of Power Supply Lines

Each supply line should be distributed separately from the power supply unit. The regulator on the board that

converts 3.3V to 1.8V can also supply TVDD of the AK7736A.

(2) Set up the evaluation mode, jumper pins and connectors. (according to the following section)

(3) Connect the board to a PC with a USB cable via the AKD77XX-HF-CONTROL-BOX (called

“CONTROL-BOX” hereafter) which is included in this package. It is required to push down the reset button

(yellow) of the CONTROL-BOX to initialize the USB control chip.

(4) Power On

(5) Start the control software and set up registers by PC. (according to the following section)

■ Evaluation Mode

In case of evaluating theAK7736A by using the AK4118A, it is necessary that audio interface format of both

devices are matched. Refer to the datasheet for audio interface format of the AK7736A, and refer to

“Jumper Pin and Switch Setting” for audio interface format of the AK4118A.

Applicable Evaluation Mode

(1) Digital-to-Digital Evaluation using ADC-Port and DAC-Port:

CKM Master Mode = 0/1

(2) Digital-to-Digital Evaluation using ADC-Port and DAC-Port:

CKM Slave Mode = 2/3/4/5

Refer to the “Control Software” section of this manual and the datasheet of the AK7736A for FPGA, the AK4118A

and control register setting of the AK7736A.

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(1) Digital-to-Digital Evaluation using ADC Port and DAC Port: CKM Master Mode = 0/1

ADC-Port and DAC-Port are used on this evaluation. Set the clock mode of the AK7736A to CKM Master Mode

0 (12.288MHz) or CKM Master Mode 1 (18.432MHz). The AK7736A outputs BICK and LRCK to the ADC-Port

and DAC-Port by setting the FPGA. The ADC-Port inputs data to the SDIN1, SDIN2A, SDIN2B, SDIN2C,

SDIN3 or SDIN4 pin. The DAC-Port output data from the SDOUT1, SDOUT2A, SDOUT2B, SDOUT3 or

SDOUT4 pin.

[Jumper Pins Setting]

JP1

XTI-SEL

CRY EXT

For digital output, optical connector PORT2 (SPDIF-OUT) is also available. The following setting must be made

and the FPGA setting should be changed when using the SPDIF-OUT instead of the DAC-Port. Refer to

“AK4118A Setting” for detail setting of the AK4118A.

Main Board

Jumper / Switch Setting (Default)

SW1 (AK4118A

Clock)

“TX-CLK”

S1(AK4118A Setting) 1->7=LHLLLHH

Table 3. Configuration of the AK4118A switch in Master Mode

(2) Digital-to-Digital Evaluation using ADC Port and DAC Port: CKM Slave Mode = 2/3/4/5

ADC-Port and DAC-Port are used on this evaluation. Set the clock mode of AK7736A to CKM Slave Mode

2/3/4/5. ADC-Port supplies MCLK, BICK, LRCK and digital data to the AK7736A. (MCLK is needed in CKM

Slave Mode 2 only)

[Jumper Pins Setting]

JP10

XTI-SEL

CRY EXT

(MCLK is needed in CKM Slave Mode 2 only)

For digital input and output, optical connector PORT1 (SPDIF-IN) and PORT2 (SPDIF-OUT) are available,

respectively. The following setting must be made and the FPGA setting should be changed when using these

connectors. Refer to “AK4118A Setting” for detail setting of the AK4118A.

Main Board

Jumper / Switch Setting (Default)

SW1 (AK4118A

Clock)

“XTL”

S1(AK4118A Setting) 1->7=LHLLLLH

Table 4. Configure the AK4118A switch at the Slave Mode

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■ Board control

The AKD7736A-A can be controlled by a PC via USB port. Connect the CONTROL-BOX included in this package to

the AKD7736A-A with a 10-pin flat cable, and connect the CONTROL-BOX to a PC with a USB cable. The 10-pin

flat cable should be connected in the direction that the side with a bump meets a marking, that says “CONTROL”, on

the main board of the AKD7736A-A.

Figure 1. Direction of the 10-pin Flat Cable

The interface setting is made by jumper pins of the CONTROL-BOX and the I2CSEL pin of the AK7736A.

SPI(Serial) Setting I2C Setting

Figure 2. Configuration of the CONTROL-BOX

Control software is different depending on the interface setting.

The software operation sequence is shown in this manual.

■ Indication for LED

[LED] D1: The status of AK7736A’s PDN pin is shown. “H” → Light off; “L” → Light on.

CONTROL

Open

Short

Open

Short

Open

Short

Open

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■ Jumper Pin and Switch Setting

Jumper / Switch Setting (Default) Note

SW1 (AK4118A

Clock)

“TX-CLK”

AK4118A Clock Source

“XTL”: Crystal Clock

“TX-CLK”: External Clock

S1(AK4118A Setting) 1->7=LHLLLHH Refer to “AK4118A Setting”

S2(AK7736A Setting) 1->5=LLLLL Refer to (9) in Table 1

JP4 (TVDD) Short AK7736A TVDD

JP5 (P-TVDD) “3.3V” Refer to (11) in Table 1

JP6 (VDD) Short AK7736A VDD

JP7 (P-DVDD) Short Peripheral DVDD

JP8 (DI1)

“Xilinx”

Refer to (2) in Table 1

JP9 (DI2A)

“Xilinx”

JP10 (DI2B)

“Xilinx”

JP11 (DI2C)

“Xilinx”

JP12 (XTI)

“Xilinx”

JP13 (BTI1)

“Xilinx”

JP14 (LR1)

“Xilinx”

JP15 (DI4)

“Xilinx”

JP16 (BTI2)

“Xilinx”

JP17 (LR2)

“Xilinx”

JP18 (DI3)

“Xilinx”

JP19 (BTI3)

“Xilinx”

JP20 (LR3)

“Xilinx”

Table 5. Setting of Jumper Pins on Main Board

Jumper/ Switch Setting (Default) Note

JP1 (XTI-SEL) “CRY”

AK7736A Clock Source

“

CRY”: Crystal Clock

“

EXT”: External Clock

Table 6. Setting of Jumper Pins on Sub Board

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OCKS1 OCKS0 MCKO1 MCKO2 X’tal Fs(max)

0 0 256fs L 256fs 96kHz default

0 1 256fs L 256fs 96kHz

1 0 512fs L 512fs 48kHz

1 1 128fs L 128fs 192kHz

Table 7. AK4118A-OCKS[1:0]

CM1 CM0

Clock

source

MCKO1 MCKO2 SDTO

0 0 PLL PLL L RX

0 1 X’tal X’tal X’tal DAUX

1 0 PLL PLL L RX default

1 1 X’tal X’tal X’tal DAUX

Table 8. AK4118A-CM[1:0]

DIF2 DIF1 DIF0 DAUX SDTO LRCK BICK

0 0 0 24bit,Left justified 16bit,Right justified H/L

64fs

0 0 1 24bit,Left justified 18bit,Right justified H/L

64fs

0 1 0 24bit,Left justified 20bit,Right justified H/L

64fs

0 1 1 24bit,Left justified 24bit,Right justified H/L

64fs

1 0 0 24bit,Left justified 24bit,Left justified L/H

64fs

1 0 1 24bit,I2S 24bit,I2S H/L

64fs

1 1 0 24bit,Left justified 24bit,Left justified L/H

64fs

default

1 1 1 24bit,I2S 24bit,I2S H/L

64fs

Table 9. AK4118A-DIF[2:0]

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■ Digital Input Circuit (External DIR: PORT1)

Figure 3. Digital Input Circuit

For digital input SPDIF-IN, optical connector PORT1 is available.

■ Digital Output Circuit (External DIT: PORT2)

Figure 4. Digital Output Circuit

For digital output SPDIF-OUT, optical connector PORT2 is available.

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Control Software Manual

■ Evaluation Board and Control Software Settings

(1) Set up the AKD7736A-A as needed, according to the previous terms.

(2) Connect the AKD7736A-A to a PC via the CONTROL BOX with a 10-pin flat cable on the evaluation board side

and a USB cable on the PC side. After power on the evaluation board, press the reset button (yellow) of the

CONTROL BOX to initialize the USB chip.

(3) Insert the CD-ROM labeled “AKD7736A-A Evaluation Kit” into the CD-ROM drive.

(4) Access the CD-ROM drive and double-click the icon of “AK7736A.exe” according to the interface setting to set

up the program. (AK7736A.exe: Control software of the AKD3376-A)

(5) Begin evaluation by following the procedure below.

■ Operation Flow

Evaluation flow is shown below.

1. Start up the control program following the above procedure.

2. Open dialogues to set necessary settings for evaluation and evaluate the AK7736A.

(The control software must run again when disconnecting a USB control box from the PC.)

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■ Operation Screen

(1) Main Window

Figure 5. Startup Screen

Program download, register setting, FPGA setting and script processing are executed by this control software. These

controls may be selected by the upper tabs. Frequently used buttons, such as register initializing and control buttons are

located outside of the switching tab window. Supported control interface format is shown in the Control I/F box as

“Serial” (SPI) or “I2C”.

[JX]: JX Code Setting.

[Board Init]: Reset the evaluation board, and the register values set by the control software are written again.

[PDN Pin]: Power Down. The AK7736A is initialized.

[SRESET]: System Reset.

[DSP]: DSP Reset.

[CK]: Clock Reset.

Clock reset is required when changing the clock mode or the frequency of input clock without

power downing the AKD7736A. Register values are not initialized by this reset.

[DLRDY]: Down loads DSP programs. It is required when down loading a DSP program without system clocks.

[READ]: Reads out register values and shows them on the register column.

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(2) Download

Figure 6. [Download] Dialogue

Click each [refer] button next to the Source, Program, CRAM or OFREG column to select a file, or drag and drop a file to

the each column.

CRAM file or OFREG file can be selected and be written to CRAM or OFREG by clicking the [refer] button of CRAM

write@operation column or OFREG write@operation column when the system is running. The data will be written to

specific address of CRAM or OFREG when the [write] button at right side is clicked.

[Assemble]: Compiles a source file, and the output file will be selected as a download file automatically.

[Write]: Downloads the program to the AK7736A.

[Assemble Write]: Compiles a source file and then downloads the file to the AK7736A.

[PRAM read]: Reads out the PRAM data to a temporary file.

[CRAM read]: Reads out the CRAM data to a temporary file.

[OFREG read]: Reads out the OFREG data M to a temporary file.

[CRAM SAVE]: Reads out the CRAM data, and save them to a file.

[OFREG SAVE]: Reads out the OFREG data, and save them to a file.

[MICR1~4]: Reads out the register data of MICR1~4 during run, and shows them into the box next to each button.

[CRC-Check]: By checking this checkbox, simple error detection by CRC (cyclic redundancy check) is executed

when down loading a file.

[Auto RUN]: By checking this checkbox, the downloaded file will be run automatically when finish downloading.

If not checked, the AK7736A will be in system reset state when finish downloading.

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(3) Register Set up

Figure 7. [REG1] Dialogue

Tab dialogues of REG1/REG2/REG3/REG4 are used to set registers. (TEST and Reserved items are prohibited to

change.) As the checkbox is clicked, the data is written to the register. Release the reset state after setting CKM mode

since SRESET and CKRST are on by CKM mode setting.

Refer to the AK7736A’s datasheet for details of the register setting.

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(4) FPGA Set up

Figure 8. [FPGA1] Dialogue

The FPGA1/FPGA2 dialogues are used to control the data path of the AK7736A.

FPGA Setting Table: (The default setting is shown in bold.)

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Bit Function Description

D[47:36] Reserved

D[35:34]

SEL20

EXT-XTI Input data source to the XTI pin of the AK7736A in Slave mode.

00: AK4118A-RX-CLK

01: ADC-MCLK

10: Low

11: Low

D[33]

SEL19

BICK1/LRCK1

In/Out

In/Out setting of the BITCLK1/LRCLK1 pin of the AK7736A.

0: output

1: input

D[32:31]

SEL18

BICK1/LRCK1 Input clock select to the BITCLK1/LRCLK1 pin of the

AK7736A.

00: AK4118A-BICK/LRCK

01: ADC-BICK/LRCK

10: Low

11: Low

D[30:29]

SEL17

BICK2/JX1 Input data source to the BITCLKI2/JX1 pin of the AK7736A.

00: AK4118A-BICK

01: ADC-BICK

10: Low

11: High

D[28:27]

SEL16

LRCK2/JX2 Input data source to the LRCLKI2/JX2 pin of the AK7736A.

00: AK4118A-LRCK

01: ADC-LRCK

10: Low

11: High

D[26:25]

SEL15

BICK3/LRCK3 Input clock to the BITCLKI3/LRCLKI3 pin of the AK7736A.

00: AK4118A-BICK/LRCK

01: ADC-BICK/LRCK

10: Low

11: Low

D[24:23]

SEL14

SDIN1 Input data source to the SDIN1 pin of the AK7736A.

00: AK4118A

01: ADC-SDTO1

10: ADC-SDTO2

11: Low

D[22:21]

SEL13

SDIN2A Input data source to the SDIN2A pin of the AK7736A.

00: AK4118A

01: ADC-SDTO1

10: ADC-SDTO2

11: Low

D[20:19]

SEL12

SDIN2B Input data source to the SDIN2B pin of the AK7736A.

00: AK4118A

01: ADC-SDTO1

10: ADC-SDTO2

11: Low

D[18:17]

SEL11

SDIN2C Input data source to the SDIN2C pin of the AK7736A.

00: AK4118A

01: ADC-SDTO1

10: ADC-SDTO2

11: Low

D[16:15]

SEL10

SDIN3 Input data source to the SDIN3 pin of the AK7736A.

00: AK4118A

01: ADC-SDTO1

10: ADC-SDTO2

11: Low

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D[14:13]

SEL9

SDIN4 Input data source to the SDIN4 pin of the AK7736A.

00: AK4118A

01: ADC-SDTO1

10: ADC-SDTO2

11: Low

D[12:11]

SEL8

CAD[1:0] The CAD pin setting of the AK7736A.

00: Low,Low

01: Low,High

10: High,Low

11: High,High

D[10]

SEL7

TRX-PDN The PDN pin setting of the AK4118A

0: Low

1: High

D[9]

SEL6

TX-CLK Input clock select to the XTI pin of the AK4118A.

0: AK7736A-CLKO

1: Low

D[8]

SEL5

TRX-BICK/LRCK

In/Out

In/Out setting of the BICK/LRCK pin of the AK4118A

0: output

1: AK7736A-BITCLKO/LRCLKO input

D[7:5]

SEL4

TX-DAT Input data source to the DAUX pin of the AK4118A

000: AK7736A-SDOUT1

001: AK7736A-SDOUT2A

010: AK7736A-SDOUT2B

011: AK7736A-SDOUT3

100: AK7736A-SDOUT4

101: Low

110: Low

111: Low

D[4]

SEL3

ADC-MCLK In/Out In/Out setting of the MCLK pin of the ADC-Port

0: MCLK output

1: AK7736A-CLKO input

D[3]

SEL2

ADC-BICK/LRCK

In/Out

In/Out setting of the BICK/LRCK pin of the ADC-Port

0: output

1: input

D[2:1]

SEL1

ADC-BICK/LRCK Input clock select to the BICK/LRCK pin of the ADC-Port

00: AK7736A-BITCLKO/LRCLKO

01: AK7736A-BITCLK1/LRCLK1

10: Low

11: Low

D[0]

SEL0

DAC-SDTI2 Input data source to the SDTI pin of the DAC-Port.

0: AK7736A-SDOUT2A

1: AK7736A-SDOUT2B

Table 10. FPGA

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(5) Script

Figure 9. [SCRIPT] Dialogue

As a script file is selected, the program is executed automatically. By clicking the [Repeat] button, the selected script file

will be executed once again.

The script commands are listed below.

Command Description

[SCRIPT]

Header of script file. A data error will be detected without this header.

;Comment

The line following a semicolon is ignored as a comment.

W,< command>,<data>

W,0xC0,0x00

WL,<command>,<address>,<data>,…

WL,0x82,0x0022,0x4000,0x4000,0x4000

Continuous Data Write. This command can be used during CRAM run.

Command is byte assigned, the data is word assigned.

WS,<command>,<address>,<data>,…

WS,0x81,0x00,0x22,0x40,0x00,0x40,0x00

Continuous Data Write. This command can be used during CRAM run.

Command, address and data are byte assigned.

RI: H, RI: L RS: H, RS: L

RD: H, RD: L RC: H, RC: L

PDN control SRESET control

DSP-RESET control CKRESET control

X,<address>,<data>

FPGA register write command.

P,<message>

Displays a message and poses the script.

T,<wait>

T,50mS

Wait some micro seconds.

In an actual operation, it is possible to wait longer than this period.

LP:<filename>

Program file download to PRAM of the DSP.

LC:<filename>

Coefficient file download to CRAM of the DSP.

LO:<filename>

Off-set file download to OFREG of the DSP.

Table 11. Script Command

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REVISION HISTORY

IMPORTANT NOTICE

z These products and their specifications are subject to change without notice.

When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei

Microdevices Corporation (AKM) or authorized distributors as to current status of the products.

z Descriptions of external circuits, application circuits, software and other related information contained in this

document are provided only to illustrate the operation and application examples of the semiconductor products. You

are fully responsible for the incorporation of these external circuits, application circuits, software and other related

information in the design of your equipments. AKM assumes no responsibility for any losses incurred by you or third

parties arising from the use of these information herein. AKM assumes no liability for infringement of any patent,

intellectual property, or other rights in the application or use of such information contained herein.

z Any export of these products, or devices or systems containing them, may require an export license or other official

approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,

or strategic materials.

z AKM products are neither intended nor authorized for use as critical components

Note1)

in any safety, life support, or

other hazard related device or system

Note2)

, and AKM assumes no responsibility for such use, except for the use

approved with the express written consent by Representative Director of AKM. As used here:

Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,

whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and

which must therefore meet very high standards of performance and reliability.

Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety

or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or

perform may reasonably be expected to result in loss of life or in significant injury or damage to person or

property.

z It is the responsibility of the buyer or distributor of AKM products, who distributes, disposes of, or otherwise places

the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer

or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all

claims arising from the use of said product in the absence of such notification.

Date

(yy/mm/dd)

Manual

Revision

Board

Revision

Reason Page Contents

12/07/27 KM110501 0 First edition

12/12/10 KM113102 0 Renamed AK7736 -> AK7736A

D D

C C

B B

A A

Title

Size Document Number Rev

Date: Sheet of

TOP

AKD7736A-A-MAIN

19Friday, December 07, 2012

Title

Size Document Number Rev

Date: Sheet of

TOP

AKD7736A-A-MAIN

19Friday, December 07, 2012

Title

Size Document Number Rev

Date: Sheet of

TOP

AKD7736A-A-MAIN

19Friday, December 07, 2012

CONTROL

CTRL-RESET

CTRL-RQN

CTRL-CSN

CTRL-SCK/SCL

CTRL-SI

CTRL-SO

CTRL-HOST

CTRL-XCS/SDA

DIP-TESTI1

DIP-TESTI2

DIP-TESTI3

DIP-JX0

DIP-I2C

SELECTOR

SEL-SDIN1

SEL-EXT-SDIN1

SEL-LRCLKI2/JX2

SEL-EXT-BITCLKI2/JX1

SEL-EXT-SDIN2A

SEL-EXT-LRCLK1

SEL-EXT-SDIN2B

SEL-BITCLK1

SEL-EXT-LRCLKI2/JX2

SEL-EXT-XTI

SEL-EXT-SDIN2C

SEL-X-BITCLKI2/JX1

SEL-X-XTI

SEL-EXT-LRCLKI3

SEL-EXT-BITCLKI3

SEL-X-LRCLKI2/JX2

SEL-BITCLKI3

SEL-X-SDIN3

SEL-X-SDIN4

SEL-X-BITCLKI3

SEL-SDIN2A

SEL-EXT-SDIN3

SEL-LRCLK1

SEL-SDIN2B

SEL-EXT-SDIN4

SEL-XTI

SEL-SDIN2C

SEL-X-SDIN2A

SEL-LRCLKI3

SEL-EXT-BITCLK1

SEL-X-LRCLKI3

SEL-X-SDIN2C

SEL-BITCLKI2/JX1

SEL-SDIN3

SEL-SDIN4

SEL-LS-SDIN2B

SEL-LS-LRCLK1

SEL-LS-BITCLK1

SEL-LS-SDIN1

XILINX

X-SDIN1

X-SDIN2B

X-LRCLKI2/JX2

X-BITCLKI2/JX1

X-SDA

X-BITCLK1

X-SDIN4

X-SCLK/SCL

X-LRCLK1

X-SI/CAD0

X-SDOUT2A

X-STO

X-SDOUT2B

X-EXPDN

X-CLKO

X-SO

X-BITCLKO

X-LRCLKO

X-RDY

X-SDOUT1

X-SDOUT3

X-SDOUT4

X-XTI

X-LRCLKI3

X-SDIN3

X-BITCLKI3

X-SDIN2A

X-SDIN2C

X-PDN

X-I2CSEL

X-CTRL-SCLK/SCL

X-CTRL-SO

X-CTRL-HOST

X-CTRL-RESET

X-CTRL-SI

X-CTRL-RQN

X-CTRL-CSN

X-ADC-LRCK

X-ADC-BICK

X-DAC-SDTI2

X-ADC-MCLK

X-ADC-SDTO1

X-ADC-SDTO2

X-CTRL-XCS/SDA

X-TX-DAT

X-RX-CLK2

X-RX-DAT

X-TRX-LRCK

X-TRX-BICK

X-TRX-PDN

X-TX-CLK

X-RX-CLK

X-RQN/CAD1

X-EXTCLK

X-CONFIG-BITLRIO

EXT

DAC-SDTI2

ADC-MCLK

ADC-SDTO1

EXT-SDOUT2A

EXT-LRCLKI3

ADC-SDTO2

EXT-SDOUT2B

EXT-LRCLKO

EXT-BITCLKI2/JX1

EXT-XTI

ADC-LRCK

EXT-BITCLKO

EXT-SDIN2A

ADC-BICK

EXT-SDIN2B

EXT-SDOUT1

EXT-BITCLKI3

EXT-SDIN2C

EXT-BITLK1

EXT-SDIN1

EXT-SDOUT3

EXT-LRCLKI2/JX2

EXT-CLKO

EXT-SDOUT4

EXT-SDIN3

EXT-LRLK1

EXT-SDIN4

DAC-SDTI1

EXT-EXTCLK

LEVELSHIFT

LS-BITCLK1

LS-LRCLK1

LS-X-SDIN2B

LS-X-LRCLK1

LS-X-SDOUT1

LS-X-BITCLK1

LS-SDIN2B

LS-SDIN1

LS-SDOUT2B

LS-SDOUT1

LS-X-SDOUT2B

LS-X-SDIN1

LS-X-CONFIG-BITLRIO

POWER

AK4118A

TRX-BICK

TRX-LRCK

TRX-PDN

TX-CLK

TX-DAT

RX-CLK2

RX-DAT

RX-CLK

AK7736A

DSP-SDIN3

DSP-BITCLKI3

DSP-LRCLKI3

DSP-SDIN2C

DSP-JX0

DSP-EXPDN

DSP-SDIN2A

DSP-CLKO

DSP-BITCLKO

DSP-LRCLKO

DSP-PDN

DSP-I2CSEL

DSP-RDY

DSP-SDOUT2A

DSP-SDOUT3

DSP-SDOUT4

DSP-SDOUT2B

DSP-SDOUT1

DSP-SDIN1

DSP-SDIN2B

DSP-LRCLK1

DSP-BITCLK1

DSP-SCLK/SCL

DSP-SI/CAD0

DSP-SDA

DSP-SDIN4

DSP-BITCLKI2/JX1

DSP-LRCLKI2/JX2

DSP-SO

DSP-STO

DSP-XTI

DSP-TESTI2

DSP-TESTI1

DSP-TESTI3

DSP-RQN/CAD1

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AKM AK7736AVQ Evaluation Board Manual

AKM AK7736AVQ Evaluation Board Manual

AKM AK7736AVQ Evaluation Board Manual

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