[AKD7757-A]
<KM109001> 2013/12
- 1 -
GENERAL DESCRIPTION
The AKD7757-A is an evaluation board for AK7757, which is a highly integrated digital signal processor
with an integrated 4ch DAC, a stereo ADC with input selector, a mono ADC and an integrated digital audio
interface. This board is composed of a main board and a sub board. The AKD7757-A can be set-up by a
PC via USB port. RCA connector is used for both input and output of the analog signal. Digital audio
interfaces are also integrated, enabling to Interface with a digital audio system via optical connectors or
SMUX-PORTs.
Ordering Guide
AKD7757-A --- Evaluation board for the AK7757
Control software is packed with the evaluation board.
FUNCTION
Read/Write access to PRAM, CRAM, OFREG and registers of the AK7757
Compatible with 2 types of digital audio interface
- Optical input (x1) / Optical output (x1)
- 10pin header for interface with external data source (x2)
ADC1 6ch input (differential input 3ch, single-end input 3ch), ADC2 1ch input, DAC 4ch
output
USB port for board control
AK7757FPGA
(XC95144XL)
USB
AIN1(S) 2ch
AOUT 4ch
SMUX1 SMUX2
10 Pin Header
Amp
RegulatorRegulator
GND+12V
3.3V3.3VUSB 3.3V
Regulator
PIC18F4550
Opt In
Opt Out
AK4118A
Amp
AIN(D) 4ch
AIN(S) 1ch
AINT(D) 1ch
Amp
(Note) AK4118A has DIR, DIT and X’tal oscillator.
Figure 1. AKD7757-A Block Diagram
AK7757 Evaluation Board Rev.0
AKD7757-A
[AKD7757-A]
<KM109001> 2013/12
- 2 -
Evaluation Board Diagram
Board Diagram
Figure 2. AKD7757-A Board Diagram
Description
(1) AIN/DAC (RCA Jack)
AIN: Analog input jacks. DAC: Analog output jacks.
(2) AK4118A
AK4118A has DIR, DIT and X’tal oscillator. It transports digital data to AK7757 when working in master mode and
outputs data from AK7757 when working in slave mode.
(3) SPDIF-IN/SPDIF-OUT (Optical Connector)
SPDIF-IN (Input): Supports sampling frequencies from 8 to 48kHz. Optical digital signal input to the AK4118A.
SPDIF-OUT (Output): Supports sampling frequencies from 8 to 48kHz. Optical digital signal output from the
AK4118A.
(4) +12V/GND (Power supply)
Connect to +12V and GND according to the following operation sequence.
(5) PIC18F4550
USB control chip. Control registers of the AK7757, the XC95144XL and the AK4118A can be set by a PC via USB
port.
[AKD7757-A]
<KM109001> 2013/12
- 3 -
(6) SW1
Toggle type switch. Use this switch to select the clock source between [TX-CLK] and [XTL] for changing the clock
mode of the AK4118A. Please refer to Table 3 and Table 4 about the setting of other jumper pins.
(7) SW2
Push type switch. Use this switch to initialize the PIC18F4550. When connecting the evaluation board to a PC, it is
required to initialize the PIC18F4550 once by pushing down this switch.
(8) XC95144XL(Xilinx)
FPGA for data path control. It is possible to run a variety of tests by way of controlling the data path via control
software.
(9) SMUX PORT (PORT1/PORT2)
10 pin header for interfacing with external data sources. The AKD7757-A has two SMUX ports, enabling to connect
other audio systems.
Pin I/O Function pin I/O Function
1 I MCLK 2 P GND
3 I BITCLK 4 P GND
5 I LRCLK 6 P GND
7 I SDTI 8 P GND
9 P VDD 10 O SDTO
Table 1. Pin Assignment of SMUX Port
[AKD7757-A]
<KM109001> 2013/12
- 4 -
Evaluation Board Manual
Operation Sequence
(1) Set up the power supply lines.
Jumper Pin Setting
JP2
AVD D
(Short
)
JP1
DVDD
(Short)
JP7
PVDD
(Short)
JP6
PIC-VDD-SEL
DVDD
USB-3.3V
USB-5V
Connection of power supply lines
N
ame Colo
r
Volta
g
e Commen
t
Attention
+12V Red +9
~
+12V Regulator,
Power suppl
y
for op-amp
This jack is always needed.
GND Blac
k
0V Ground This
j
ack is alwa
y
s needed.
Table 2. Power Supply Connection
Each supply line should be distributed separately from the power supply unit. The power of the AK7757 and
peripheral devices is supplied by two 12V=>3.3V regulators mounted on the evaluation board.
(2) Set up the evaluation mode, jumper pins and connectors according to the following section.
(3) Connect the AKD7757-A to a PC with the USB cable that is packed with the board.
It is required to initialize the USB control chip once by pushing down the SW2.
(4) Power On.
(5) Start the control soft and setup the registers.
Evaluation Mode
In case of evaluating the AK7757 using the AK4118A, it is necessary to adjust audio interface formats of the
AK7757 and the AK4118A to correspond with each other. Refer to the AK7757’s datasheet for audio interface
format of the AK7757. Refer to Table 10 for audio interface format of the AK4118A.
Applicable Evaluation Mode
(1) Evaluation mode of ADC and DAC via SMUX-PORT: CKM Master Mode = 0/1
(2) Evaluation mode of ADC and DAC via SMUX-PORT: CKM Slave Mode = 2/3/
(3) Evaluation mode of DSP via SMUX-PORT: CKM Master Mode = 0/1
(4) Evaluation mode of DSP via SMUX-PORT: CKM Slave Mode = 2/3
Refer to the “CONTROL SOFT MANUAL” paragraph and the datasheet of the AK7757 to set up FPGA, AK4118A
and AK7757 by a PC.
[AKD7757-A]
<KM109001> 2013/12
- 5 -
(1) Evaluation mode of ADC and DAC via SMUX-PORT: CKM Master Mode = 0/1
SMUX-POUT is used. Set the clock mode of the AK7757 to CKM Master Mode 0 (12.288MHz) or CKM Master
Mode 1 (18.432MHz). AK7757 supplies BICK and LRCK to the SMUX-PORT and the SMUX-PORT outputs the
data from SDOUT1, SDOUT2, SDOUT3 or SDOUTM to SDIN1 or SDIN2.
[Jumper Setting]
JP10
XTI-SEL
CRY EXT
[Connector Setting]
For evaluating ADC1, RCA1/RCA2 (differential input 1), RCA3 (differential input 2), RCA5/RCA6
(single-ended input 1) and RCA7 (single-ended input 2) are available. For evaluating ADC2, RCA4 (differential
input) is available. For evaluating DAC, use terminals of the sub board or main board. Refer to Table 3 and Table
4 to set up the jumpers.
(2) Evaluation mode of ADC and DAC via SMUX-PORT: CKM Slave Mode = 2/3
SMUX-PORT is used. Set the clock mode of the AK7757 to CKM Slave Mode 2/3.
SMUX-PORT supplies MCLK, BICK, LRCK and digital data to the AK7757.
(MCLK is needed only in CKM Slave Mode 2.)
[Jumper Setting]
JP10
XTI-SEL
CRY EXT
(It is needed only when CKM Slave Mode = 2)
[Connector Setting]
For evaluating ADC1, RCA1/RCA2 (differential input 1), RCA3 (differential input 2), RCA5/RCA6
(single-ended input 1) and RCA7 (single-ended input 2) are available. For evaluating ADC2, RCA4 (differential
input) is available. For evaluating DAC, use terminals of the sub board or main board. Refer to Table 3 and Table
4 to set up the jumpers.
(3) Evaluation mode of DSP using SMUX-PORT: CKM Master Mode = 0/1
SMUX-PORT and SMUX-PORT2 are used. Set the clock mode of the AK7757 to CKM Master Mode 0
(12.288MHz) or CKM Master Mode 1 (18.432MHz). The AK7757 supplies BICK and LRCK to SMUX-PORT
and SMUX-PORT2. SMUX-PORT outputs data from SDOUT1, SDOUT2 or SDOUTM and SMUX-PORT2
inputs data to SDIN1 or SDIN2.
[Jumper Setting]
JP10
XTI-SEL
CRY EXT
[AKD7757-A]
<KM109001> 2013/12
- 6 -
(4) Evaluation mode of DSP via SMUX-PORT: CKM Slave Mode = 2/3
SMUX-PORT and SMUX PORT2 are used. Set the clock mode of the AK7757 to CKM Slave Mode 2/3.
SMUX PORT is used as an input port for MCLK, BICK and LRCK to the AK7757. (MCLK is needed only in
CKM Slave Mode 2.) SMUX-PORT outputs data from SDOUT1, SDOUT2 or SDOUTM, and SMUX-PORT2
inputs data to SDIN1 or SDIN2.
[Jumper Setting]
JP10
XTI-SEL
CRY EXT
(It is needed only in CKM Slave Mode 2.)
Board Control
The AKD7757-A can be controlled by a PC via general USB port. Connect the USB port on the board to PC with the
cable packed with the AKD7757-A.
Control software is also packed with this board and the software manual is included in this manual.
LED Indicator
[LED] U11: When power is supplied, the LED emits red light. It monitors PC-RQN signal and changes the color
to yellow when the board is communicating with a PC.
[LED] D1: Monitor the status of the IRESTN pin of the AK7757.
“L” → Lighting, “H” → Not Lighting.
[AKD7757-A]
<KM109001> 2013/12
- 7 -
Setting of Jumper Pins
Main board:
Jumper / Switch Setting (Default) Note
SW1 (AK4118A Clock) “TX-CLK”
AK4118A Clock Source
“XTL”: Crystal Clock
“
TX-CLK”: External Clock
JP1 (DVDD) Short DVDD of the AK7757
JP2 (AVDD) Short AVDD of the AK7757
JP3 (AINL) AINL3
Single-end input selector for ADC1
JP4 (AINR) AINR3
JP6 (PIC-VDD-SEL)
“USB 3.3V”
USB chip power supply
“USB-5V”: USB 5V
“USB-3.3V”: USB 3.3V
“DVDD”: Peripheral DVDD 3.3V
JP7 (PVDD)
Short Peripheral DVDD 3.3V
JP11 (AOUTL1N)
Short
DAC1, DAC2 Output
JP12 (AOUTL1P)
Open
JP13 (AOUTR1N)
Short
JP14 (AOUTR1P)
Open
JP15 (AOUTL2N)
Short
JP16 (AOUTL2P)
Open
JP17 (AOUTR2N)
Short
JP18 (AOUTR2P)
Open
Table 3. Setting of Jumper Pins on Main Board
[AKD7757-A]
<KM109001> 2013/12
- 8 -
Sub board:
Jumper / Switch Setting (Default) Note
JP1 (REG-SEL) Short
Regulator(U1) Operation Select
“Short”: ON
“Open”: OFF
JP2 (DVDD18-SEL) Short
DVDD18 of the AK7757
“Short”: Regulator(U1) Output
“Open”: JP2-2 Input
JP3 (AO2R-SEL) “THR”
AOUT2R Output Select of the AK7757
“THR”: RCA4(DAC2R) on the Sub Board
“AMP”: RCA12(DAC2R) on the Main Board
JP4 (AO2L-SEL) “THR”
AOUT2L Output Select of the AK7757
“THR”: RCA3(DAC2L) on the Sub Board
“AMP”: RCA11(DAC2L) on the Main Board
JP5 (AO1R-SEL) “THR”
AOUT1R Output Select of the AK7757
“THR”: RCA2(DAC1R) on the Sub Board
“AMP”: RCA10(DAC1R) on the Main Board
JP7 (AO1L-SEL) “THR”
AOUT1L Output Select of the AK7757
“THR”: RCA1(DAC1L) on the Sub Board
“AMP”: RCA9(DAC1L) on the Main Board
JP6 (SO-SEL) “SO”
SO/SDA Input Select of the AK7757
“SO”: Microprocessor Interface (I2CSEL=L)
“SDA”: I2C-bus Interface (I2CSEL=H)
JP8 (MB-SEL) open
for MICBIAS evaluation of the AK7757
JP9 (MICIN-SEL) “AIN”
AIN/INP Input Select of the AK7757
“AIN”: MIC Single-ended Input
“INP”: MIC Differential Non-inverted Input
JP10 (XTI-SEL) “CRY”
AK7757 Clock Source
“CRY”: Crystal Clock
“EXT”: External Clock
Table 4. Setting of jumper pins on sub board
[AKD7757-A]
<KM109001> 2013/12
- 9 -
Analog Input Circuit
Figure 3. ADC1 Analog Differential Input Circuit 1
For ADC1 analog differential input 1, RCA1(AIN(D)-2R), RCA2(AIN(D)-2L) are available.
The input range of each channel is ±[email protected].
[AKD7757-A]
<KM109001> 2013/12
- 10 -
Figure 4. ADC1 Analog Differential Input Circuit 2
For ADC1 analog differential input 2, RCA3(AIN(D)-IN) is available. Set the JP9 jumper pin on the sub board to INP
setting. The input range of each channel is ±[email protected].
Figure 5. ADC2 Analog Differential Input Circuit
For ADC2 analog differential input, RCA4(AIN(D)-T) is available.
The input range of each channel is [email protected].
[AKD7757-A]
<KM109001> 2013/12
- 11 -
Figure 6. ADC1 Analog Single-ended Input Circuit 1
For ADC1 analog single-ended input 1, RCA5(AIN(S)-L), RCA6(AIN(S)-R) are available.
The input range of each channel is [email protected].
Jumper Pin Setting for Analog Single-ended Input Circuit
Input
1-2 pin 3-4 pin 5-6 pin 7-8 pin
AIN1L/ AIN1R Short Open Open Open Default
Table 5. Jumper Pin Setting for Analog Single-ended Input Circuit of ADC1
Figure 7. ADC1 Analog Single-ended Input Circuit 2
For ADC1 analog single-ended input 2, RCA7(AIN) is available.
The input range of each channel is [email protected].
Invert the Polarity
Invert the Polarity
Invert the Polarity
[AKD7757-A]
<KM109001> 2013/12
- 12 -
Analog Output Circuit
Figure 8. DAC1 Analog Output Circuit on Sub Board
For DAC1 sub board analog output, RCA1(DAC1L), RCA2(DAC1R) are available.
The output range of each channel is 2.2Vpp @3.3V.
Figure 9. DAC2 Analog Output Circuit on Sub Board
For DAC2 sub board analog output, RCA3(DAC2L), RCA4(DAC2R) are available.
The output range of each channel is 2.2Vpp @3.3V.
Load Capacitance
Load Capacitance
Load Capacitance
Load Capacitance
Load Resistance
Load Resistance
Load Resistance
Load Resistance
[AKD7757-A]
<KM109001> 2013/12
- 13 -
Figure 10. DAC1 Analog Output Circuit on Main Board
For DAC1 main board analog output, RCA9(DAC1L), RCA10(DAC1R) are available.
The output range of each channel is 2.2Vpp @3.3V.
Open
Open
[AKD7757-A]
<KM109001> 2013/12
- 14 -
Figure 11. DAC2 Analog Output Circuit on Main Board
For DAC2 main board analog output, RCA11(DAC2L), RCA12(DAC2R) are available.
The output range of each channel is 2.2Vpp @3.3V.
Open
Open
[AKD7757-A]
<KM109001> 2013/12
- 15 -
Digital Input Circuit (External DIR: PORT1)
Figure 12. Digital Input Circuit
For digital input SPDIF-IN, optical connector PORT1 is available.
Digital Output Circuit (External DIT: PORT2)
Figure 13. Digital Output Circuit
For digital output SPDIF-OUT, optical connector PORT2 is available.
[AKD7757-A]
<KM109001> 2013/12
- 16 -
Control Software Manual
Set-up of the Evaluation Board and Control Software
(1) Set up the AKD7757-A according to previous paragraphs of this document.
(2) Connect AKD7757-A to PC with the cable packed Push down the reset button (SW2) to initialize the USB control
chip.
(3) Insert the CD-ROM labeled “AKD7757-A Evaluation Kit” into the CD-ROM drive.
(4) Access the CD-ROM drive and double-click the icon of “AK7757.exe” to start the control software.
AK7757.exe: Control Software for the AK7757
(5) Proceed the evaluation according to the follow sections.
Operation Flow
(1) Start the control software according to the set-up sequence above.
(2) Select the needed dialogue and set for the evaluation. (If the USB cable is disconnected when the control software
is running, it is necessary to quit the control software once and restart to use the software again.)
[AKD7757-A]
<KM109001> 2013/12
- 17 -
Description of Control Software
(1) Main Dialogue
Figure 14. Main Dialogue of Control Software
Control software is used to a download program, to set up the registers of the AK7757 and FPGA and to process a script
file. These functions can be selected by the tab items above. The buttons of control signals that are frequently used and
the initialization buttons are placed outside the tab dialogue. The control interface of the control software, “Serial
(4-wire)” or “I2C”, is displayed in the “Control I/F” window.
[IRSTN]: Initial Reset. It is used to initialize the AK7757.
[CODEC]: CODEC Reset. ACD and DAC will be reset.
[DSP]: DSP Reset.
[Clock]: Clock Reset. Clock Reset is required when changing the clock mode or the frequency of input clock
without initial reset. All registers will not be initialized.
[Board Init]: Initial Reset. It initializes all software setting of the AKD7757; registers of the AK7757, FPGA and
AK4118A.
[READ]: Read out register settings of the AK7757 and display them in “Register” window.
[AKD7757-A]
<KM109001> 2013/12
- 18 -
(2) “DownLoad” Dialogue
Figure 15. “Down Load” Dialogue
Select a file for Source box, Program box, CRAM box or OFREG bix by clicking the [refer] button of each box, or by
drag and drop a file to the box.
Select a file for CRAM box and OFRAM box by clicking [refer] button. CRAM and OFREG writings during RUN are
available. Data is written to the determined address of CRAM/OFRAM during RUN by clicking the [write] button.
[Assemble]: Compiles the source file, and the output file will be selected to the download program automatically.
[Write]: Downloads the program file to the AK7757.
[Assemble Write]: Compiles the source file, and then downloads the program file to the AK7757.
[PRAM read]: Reads the data of PRAM to a temporary file and opens the file.
[CRAM read]: Reads the data of CRAM to a temporary file and opens the file.
[OFREG read]: Reads the data of OFREG to a temporary file and opens the file.
[CRAM SAVE]: Reads the data of CRAM and saves to a file.
[OFREG SAVE]: Reads the data of OFREG and saves to a file.
[MICR1~MIR4]: Reads the data of register MICR1~MIR4 when a program is running and displays the result.
[JX]: JX code setting.
[CRC-Check]: If this box is checked, simple write error check is done by CRC when downloading a file to
theAK7757.
[Auto RUN]: If this box is checked, the AK7757 will be set to run mode automatically after downloading a
program. If this box is not checked, the AK7757 will be set to DSP reset and CODEC reset mode after
downloading a program.
[AKD7757-A]
<KM109001> 2013/12
- 19 -
(3) “REG” Dialogue
Figure 16. “REG1” Dialogue
Set up the registers of the AK7757 by REG1~REG6 dialogues. (It is prohibited to modify TEST and Reserved items.) As
the checkbox is clicked, the data will be written to the AK7757. Register settings must be made during CODEC reset and
DSP reset.
The reference pages of register settings in datasheet are shown below:
Register Reference Page Register Reference Page
CONT00 27 CONT09 36
CONT01 28 CONT0A 36,37
CONT02 29 CONT0B 38
CONT03 30 CONT0C 38,39
CONT04 31 CONT0D 40
CONT05 32 CONT0E 41
CONT06 33 CONT10-13 42
CONT07 34 CONT14-17 43
CONT08 35
Table 6. Reference Page of Register Settings
[AKD7757-A]
<KM109001> 2013/12
- 20 -
(4) “FPGA” Dialogue
Figure 17. “FPGA1” Dialogue
FPGA1/FPGA2 dialogues are used to modify the data path of the AK7757 and the setting of the AK4118A.
(It is prohibited to modify TEST and Reserved items.)
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
/
