KL28Z Reference Manual
MKL28Z512VDC7, MKL28Z512VLL7
Document Number: MKL28ZRM
Rev. 4, 06/2016
KL28Z Reference Manual, Rev. 4, 06/2016
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................43
1.1.1 Purpose...........................................................................................................................................................43
1.1.2 Audience........................................................................................................................................................ 43
1.2 Conventions.................................................................................................................................................................. 43
1.2.1 Numbering systems........................................................................................................................................43
1.2.2 Typographic notation..................................................................................................................................... 44
1.2.3 Special terms..................................................................................................................................................44
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................45
2.2 KL28Z sub-family introduction....................................................................................................................................45
2.3 Feature Summary..........................................................................................................................................................46
2.4 Block Diagram..............................................................................................................................................................49
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................51
3.2 Clock gating..................................................................................................................................................................51
3.3 Module to Module Interconnects..................................................................................................................................52
3.3.1 Interconnection overview...............................................................................................................................52
3.3.2 Analog reference options............................................................................................................................... 52
3.4 Core Modules................................................................................................................................................................53
3.4.1 Introduction....................................................................................................................................................53
3.4.2 ARM Cortex M0+ core .................................................................................................................................53
3.4.3 Debug facilities.............................................................................................................................................. 54
3.4.4 Buses, interconnects, and interfaces.............................................................................................................. 54
3.4.5 System tick timer........................................................................................................................................... 54
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3.4.6 Caches............................................................................................................................................................ 54
3.4.7 Interrupt connections......................................................................................................................................55
3.4.8 Asynchronous Wake-up Interrupt Controller (AWIC).................................................................................. 59
3.5 System Modules............................................................................................................................................................60
3.5.1 Crossbar Switch............................................................................................................................................. 60
3.5.2 Low-Leakage Wake-up Unit (LLWU)...........................................................................................................61
3.5.3 DMAMUXs................................................................................................................................................... 63
3.5.4 Watchdog (WDOG)....................................................................................................................................... 65
3.5.5 System Register File Configuration...............................................................................................................65
3.5.6 Peripheral Clock Control (PCC) Configuration.............................................................................................66
3.5.7 System Register File Configuration...............................................................................................................66
3.6 Security......................................................................................................................................................................... 67
3.6.1 CAU Configuration........................................................................................................................................67
3.7 Analog...........................................................................................................................................................................68
3.7.1 16-bit SAR ADC configuration..................................................................................................................... 68
3.7.2 CMP configuration.........................................................................................................................................71
3.7.3 VREF............................................................................................................................................................. 73
3.7.4 12-bit DAC configuration.............................................................................................................................. 75
3.8 Timers........................................................................................................................................................................... 76
3.8.1 Timer/PWM module configuration................................................................................................................76
3.8.2 LPIT............................................................................................................................................................... 78
3.8.3 Low Power Timer (LPTMR)......................................................................................................................... 79
3.8.4 RTC configuration......................................................................................................................................... 80
3.9 Communication interfaces............................................................................................................................................ 81
3.9.1 Universal Serial Bus (USB) FS Subsystem................................................................................................... 81
3.9.2 LPSPI configuration.......................................................................................................................................87
3.9.3 LPI2C.............................................................................................................................................................88
3.9.4 LPUART configuration..................................................................................................................................89
3.9.5 EMVSIM Configuration................................................................................................................................ 90
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3.9.6 FlexIO ........................................................................................................................................................... 90
3.9.7 I2S configuration............................................................................................................................................91
3.10 Human-machine interfaces (HMI)................................................................................................................................93
3.10.1 GPIO configuration........................................................................................................................................93
3.10.2 TSI configuration........................................................................................................................................... 94
3.11 Signal multiplexing integration.................................................................................................................................... 95
3.11.1 Signal multiplexing configuration................................................................................................................. 95
Chapter 4
Memory Map
4.1 Memory Map ............................................................................................................................................................... 99
4.2 SRAM sizes.................................................................................................................................................................. 99
4.3 System Memory Map....................................................................................................................................................99
4.3.1 Memory Map .................................................................................................................................................99
4.4 Flash Memory Maps..................................................................................................................................................... 101
4.4.1 Flash Memory Map........................................................................................................................................101
4.5 SRAM Memory Map....................................................................................................................................................102
4.6 Bit Manipulation Engine...............................................................................................................................................102
4.7 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................103
4.7.1 AIPS0 Peripheral Slot Assignments.............................................................................................................. 103
4.7.2 AIPS1 Peripheral Slot Assignments.............................................................................................................. 107
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................111
5.2 Clock Sources............................................................................................................................................................... 112
5.3 SCG Output Clocks...................................................................................................................................................... 113
5.3.1 DIVCORE_CLK............................................................................................................................................113
5.3.2 DIVSLOW_CLK........................................................................................................................................... 113
5.3.3 Peripheral functional clocks...........................................................................................................................113
5.4 Peripheral Clock Summary...........................................................................................................................................116
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5.5 DIV3 Peripheral Clocking............................................................................................................................................ 118
5.6 DIV1 Peripheral Clocking............................................................................................................................................ 119
5.7 Programming model......................................................................................................................................................120
5.8 Other Clock Sources..................................................................................................................................................... 121
5.8.1 OSC32KCLK.................................................................................................................................................121
5.8.2 LPO Low Power Oscillator............................................................................................................................121
5.9 Clock definitions...........................................................................................................................................................121
5.10 Clocking details............................................................................................................................................................ 122
5.11 Internal Clocking Requirements................................................................................................................................... 123
5.12 Clock divider values after reset.....................................................................................................................................124
5.13 Clock gating..................................................................................................................................................................125
5.14 Flash Memory Clock.....................................................................................................................................................125
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................127
6.2 Reset..............................................................................................................................................................................128
6.2.1 Power-on reset (POR).................................................................................................................................... 128
6.2.2 System reset sources...................................................................................................................................... 128
6.2.3 MCU resets.................................................................................................................................................... 131
6.2.4 RESET_b pin ................................................................................................................................................ 132
6.2.5 Debug resets...................................................................................................................................................133
6.3 Boot...............................................................................................................................................................................133
6.3.1 Boot sources...................................................................................................................................................133
6.3.2 FOPT boot options.........................................................................................................................................134
6.3.3 Boot sequence................................................................................................................................................ 135
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................139
7.2 Clocking modes............................................................................................................................................................ 139
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7.2.1 Partial Stop.....................................................................................................................................................139
7.2.2 DMA Wakeup................................................................................................................................................140
7.2.3 Compute Operation........................................................................................................................................141
7.2.4 Peripheral Doze..............................................................................................................................................142
7.2.5 Clock gating................................................................................................................................................... 143
7.3 Power Mode Architecture.............................................................................................................................................143
7.4 Power modes.................................................................................................................................................................143
7.5 Entering and exiting power modes............................................................................................................................... 146
7.6 Module operation in low-power modes........................................................................................................................ 146
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................151
8.1.1 Debug security............................................................................................................................................... 151
8.1.2 Flash security................................................................................................................................................. 151
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................153
9.2 Debug port pin descriptions..........................................................................................................................................153
9.3 Debug and Trace Block diagram.................................................................................................................................. 154
9.4 SWD status and control registers..................................................................................................................................155
9.4.1 MDM-AP Control Register............................................................................................................................156
9.4.2 MDM-AP Status Register.............................................................................................................................. 157
9.5 Debug resets..................................................................................................................................................................159
9.6 Micro Trace Buffer (MTB)...........................................................................................................................................160
9.7 Debug in low-power modes..........................................................................................................................................160
9.8 Debug and security....................................................................................................................................................... 161
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................163
10.2 Pinout............................................................................................................................................................................163
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10.2.1 Package types.................................................................................................................................................163
10.2.2 KL28Z Signal Multiplexing and Pin Assignments........................................................................................163
10.2.3 KL28Z Pinouts...............................................................................................................................................168
10.3 Module Signal Description Tables................................................................................................................................170
10.3.1 Core modules................................................................................................................................................. 170
10.3.2 System modules............................................................................................................................................. 171
10.3.3 Clock modules................................................................................................................................................171
10.3.4 Memories and memory interfaces..................................................................................................................171
10.3.5 Analog............................................................................................................................................................172
10.3.6 Timer Modules...............................................................................................................................................172
10.3.7 Communication interfaces............................................................................................................................. 173
10.3.8 Human-machine interfaces (HMI).................................................................................................................177
Chapter 11
Analog-to-Digital Converter (ADC)
11.1 Introduction...................................................................................................................................................................179
11.1.1 Features.......................................................................................................................................................... 179
11.1.2 Block diagram................................................................................................................................................180
11.2 ADC signal descriptions............................................................................................................................................... 181
11.2.1 Analog Power (VDDA)................................................................................................................................. 182
11.2.2 Analog Ground (VSSA).................................................................................................................................182
11.2.3 Voltage Reference Select...............................................................................................................................182
11.2.4 Analog Channel Inputs (ADx)....................................................................................................................... 183
11.2.5 Differential Analog Channel Inputs (DADx).................................................................................................183
11.3 Memory map and register definitions...........................................................................................................................183
11.3.1
ADC Status and Control Registers 1 (ADCx_SC1n).....................................................................................184
11.3.2
ADC Configuration Register 1 (ADCx_CFG1).............................................................................................188
11.3.3
ADC Configuration Register 2 (ADCx_CFG2).............................................................................................189
11.3.4
ADC Data Result Register (ADCx_Rn).........................................................................................................190
11.3.5
Compare Value Registers (ADCx_CVn)....................................................................................................... 192
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11.3.6
Status and Control Register 2 (ADCx_SC2)..................................................................................................193
11.3.7
Status and Control Register 3 (ADCx_SC3)..................................................................................................195
11.3.8
ADC Offset Correction Register (ADCx_OFS).............................................................................................196
11.3.9
ADC Plus-Side Gain Register (ADCx_PG)...................................................................................................197
11.3.10
ADC Minus-Side Gain Register (ADCx_MG).............................................................................................. 197
11.3.11
ADC Plus-Side General Calibration Value Register (ADCx_CLPD)........................................................... 198
11.3.12
ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............................................................199
11.3.13
ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............................................................ 199
11.3.14
ADC Plus-Side General Calibration Value Register (ADCx_CLP3)............................................................ 200
11.3.15
ADC Plus-Side General Calibration Value Register (ADCx_CLP2)............................................................ 200
11.3.16
ADC Plus-Side General Calibration Value Register (ADCx_CLP1)............................................................ 201
11.3.17
ADC Plus-Side General Calibration Value Register (ADCx_CLP0)............................................................ 201
11.3.18
ADC Minus-Side General Calibration Value Register (ADCx_CLMD).......................................................202
11.3.19
ADC Minus-Side General Calibration Value Register (ADCx_CLMS)....................................................... 202
11.3.20
ADC Minus-Side General Calibration Value Register (ADCx_CLM4)....................................................... 203
11.3.21
ADC Minus-Side General Calibration Value Register (ADCx_CLM3)....................................................... 203
11.3.22
ADC Minus-Side General Calibration Value Register (ADCx_CLM2)....................................................... 204
11.3.23
ADC Minus-Side General Calibration Value Register (ADCx_CLM1)....................................................... 204
11.3.24
ADC Minus-Side General Calibration Value Register (ADCx_CLM0)....................................................... 205
11.4 Functional description...................................................................................................................................................205
11.4.1 Clock select and divide control......................................................................................................................206
11.4.2 Voltage reference selection............................................................................................................................207
11.4.3 Hardware trigger and channel selects............................................................................................................ 207
11.4.4 Conversion control.........................................................................................................................................208
11.4.5 Automatic compare function..........................................................................................................................216
11.4.6 Calibration function....................................................................................................................................... 217
11.4.7 User-defined offset function.......................................................................................................................... 219
11.4.8 Temperature sensor........................................................................................................................................220
11.4.9 MCU wait mode operation.............................................................................................................................221
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11.4.10 MCU Normal Stop mode operation...............................................................................................................221
11.5 Initialization information.............................................................................................................................................. 222
11.5.1 ADC module initialization example.............................................................................................................. 223
11.6 Application information................................................................................................................................................225
11.6.1 External pins and routing............................................................................................................................... 225
11.6.2 Sources of error..............................................................................................................................................227
Chapter 12
Crossbar Switch Lite (AXBS-Lite)
12.1 Introduction...................................................................................................................................................................231
12.1.1 Features.......................................................................................................................................................... 231
12.2 Memory Map / Register Definition...............................................................................................................................232
12.3 Functional Description..................................................................................................................................................232
12.3.1 General operation...........................................................................................................................................232
Chapter 13
Bit Manipulation Engine2 (BME2)
13.1 Introduction...................................................................................................................................................................233
13.1.1 Features.......................................................................................................................................................... 234
13.1.2 Modes of operation........................................................................................................................................ 234
13.2 Memory map and register definition.............................................................................................................................234
13.3 Functional description...................................................................................................................................................235
13.3.1 BME decorated stores.................................................................................................................................... 235
13.3.2 BME decorated loads.....................................................................................................................................242
13.4 Application information................................................................................................................................................248
Chapter 14
Kinetis ROM Bootloader
14.1 Chip-Specific Information............................................................................................................................................ 251
14.1.1 Kinetis Bootloader Peripheral Pinmux.......................................................................................................... 251
14.1.2 Bootloader Memory Access...........................................................................................................................252
14.2 Introduction...................................................................................................................................................................252
14.3 Functional Description..................................................................................................................................................254
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14.3.1 Memory Maps................................................................................................................................................254
14.3.2 The Kinetis Bootloader Configuration Area (BCA)......................................................................................255
14.3.3 Start-up Process..............................................................................................................................................257
14.3.4 Clock Configuration.......................................................................................................................................259
14.3.5 Bootloader Entry Point / API Tree.................................................................................................................260
14.3.6 Bootloader Protocol....................................................................................................................................... 261
14.3.7 Bootloader Packet Types............................................................................................................................... 266
14.3.8 Bootloader Command API.............................................................................................................................274
14.3.9 Bootloader Exit state......................................................................................................................................297
14.4 Peripherals Supported................................................................................................................................................... 297
14.4.1 LPI2C Peripheral............................................................................................................................................297
14.4.2 LPSPI Peripheral............................................................................................................................................299
14.4.3 LPUART Peripheral.......................................................................................................................................302
14.4.4 USB peripheral...............................................................................................................................................304
14.5 Get/SetProperty Command Properties..........................................................................................................................308
14.5.1 Property Definitions.......................................................................................................................................310
14.6 SB File Decryption Support..........................................................................................................................................311
14.6.1 Decryption using MMCAU........................................................................................................................... 312
14.7 CRC-32 Check on Application Data.............................................................................................................................313
14.8 Kinetis Bootloader Status Error Codes.........................................................................................................................314
Chapter 15
Cryptographic Acceleration Unit (CAU)
15.1 Introduction...................................................................................................................................................................317
15.2 CAU Block Diagram.....................................................................................................................................................317
15.3 Overview.......................................................................................................................................................................319
15.4 Features.........................................................................................................................................................................320
15.5 Memory map/Register definition..................................................................................................................................320
15.5.1
Status Register (CAUx_CASR)..................................................................................................................... 322
15.5.2
Accumulator (CAUx_CAA).......................................................................................................................... 323
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15.5.3
General Purpose Register (CAUx_CAn)....................................................................................................... 323
15.6 Functional description...................................................................................................................................................324
15.6.1 CAU programming model............................................................................................................................. 324
15.6.2 CAU integrity checks.....................................................................................................................................326
15.6.3 CAU commands.............................................................................................................................................328
15.7 Application/initialization information.......................................................................................................................... 335
15.7.1 Code example.................................................................................................................................................335
15.7.2 Assembler equate values................................................................................................................................336
Chapter 16
Comparator (CMP)
16.1 Introduction...................................................................................................................................................................339
16.1.1 CMP features..................................................................................................................................................339
16.1.2 6-bit DAC key features.................................................................................................................................. 340
16.1.3 ANMUX key features.................................................................................................................................... 340
16.1.4 CMP, DAC and ANMUX diagram................................................................................................................341
16.1.5 CMP block diagram....................................................................................................................................... 342
16.2 Memory map/register definitions..................................................................................................................................344
16.2.1
CMP Control Register 0 (CMPx_CR0)......................................................................................................... 344
16.2.2
CMP Control Register 1 (CMPx_CR1)......................................................................................................... 345
16.2.3
CMP Filter Period Register (CMPx_FPR).....................................................................................................347
16.2.4
CMP Status and Control Register (CMPx_SCR)...........................................................................................347
16.2.5
DAC Control Register (CMPx_DACCR)......................................................................................................348
16.2.6
MUX Control Register (CMPx_MUXCR).................................................................................................... 349
16.3 Functional description...................................................................................................................................................350
16.3.1 CMP functional modes...................................................................................................................................350
16.3.2 Power modes..................................................................................................................................................360
16.3.3 Startup and operation..................................................................................................................................... 361
16.3.4 Low-pass filter............................................................................................................................................... 362
16.4 CMP interrupts..............................................................................................................................................................364
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16.5 DMA support................................................................................................................................................................ 364
16.6 CMP Asynchronous DMA support...............................................................................................................................365
16.7 Digital-to-analog converter...........................................................................................................................................366
16.8 DAC functional description.......................................................................................................................................... 366
16.8.1 Voltage reference source select......................................................................................................................366
16.9 DAC resets....................................................................................................................................................................367
16.10 DAC clocks...................................................................................................................................................................367
16.11 DAC interrupts..............................................................................................................................................................367
16.12 CMP Trigger Mode.......................................................................................................................................................367
Chapter 17
Cyclic Redundancy Check (CRC)
17.1 Introduction...................................................................................................................................................................369
17.1.1 Features.......................................................................................................................................................... 369
17.1.2 Block diagram................................................................................................................................................369
17.1.3 Modes of operation........................................................................................................................................ 370
17.2 Memory map and register descriptions.........................................................................................................................370
17.2.1 CRC Data register (CRC_DATA)................................................................................................................. 371
17.2.2 CRC Polynomial register (CRC_GPOLY).................................................................................................... 372
17.2.3 CRC Control register (CRC_CTRL)..............................................................................................................372
17.3 Functional description...................................................................................................................................................373
17.3.1 CRC initialization/reinitialization..................................................................................................................373
17.3.2 CRC calculations............................................................................................................................................374
17.3.3 Transpose feature........................................................................................................................................... 375
17.3.4 CRC result complement.................................................................................................................................377
Chapter 18
12-bit Digital-to-Analog Converter (DAC)
18.1 Introduction...................................................................................................................................................................379
18.2 Features.........................................................................................................................................................................379
18.3 Block diagram...............................................................................................................................................................379
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18.4 Memory map/register definition................................................................................................................................... 380
18.4.1
DAC Data Low Register (DACx_DATnL)................................................................................................... 382
18.4.2
DAC Data High Register (DACx_DATnH).................................................................................................. 382
18.4.3
DAC Status Register (DACx_SR)................................................................................................................. 382
18.4.4
DAC Control Register (DACx_C0)............................................................................................................... 383
18.4.5
DAC Control Register 1 (DACx_C1)............................................................................................................ 385
18.4.6
DAC Control Register 2 (DACx_C2)............................................................................................................ 386
18.5 Functional description...................................................................................................................................................386
18.5.1 DAC data buffer operation.............................................................................................................................386
18.5.2 DMA operation.............................................................................................................................................. 387
18.5.3 Resets............................................................................................................................................................. 387
18.5.4 Low-Power mode operation...........................................................................................................................388
Chapter 19
Direct Memory Access Multiplexer (DMAMUX)
19.1 Introduction...................................................................................................................................................................389
19.1.1 Overview........................................................................................................................................................389
19.1.2 Features.......................................................................................................................................................... 390
19.1.3 Modes of operation........................................................................................................................................ 390
19.2 External signal description............................................................................................................................................391
19.3 Memory map/register definition................................................................................................................................... 391
19.3.1
Channel Configuration register (DMAMUXx_CHCFGn)............................................................................ 392
19.4 Functional description...................................................................................................................................................392
19.4.1 DMA channels with periodic triggering capability........................................................................................393
19.4.2 DMA channels with no triggering capability.................................................................................................395
19.4.3 Always-enabled DMA sources...................................................................................................................... 395
19.5 Initialization/application information........................................................................................................................... 397
19.5.1 Reset...............................................................................................................................................................397
19.5.2 Enabling and configuring sources..................................................................................................................397
Chapter 20
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Enhanced Direct Memory Access (eDMA)
20.1 Introduction...................................................................................................................................................................401
20.1.1 eDMA system block diagram........................................................................................................................ 401
20.1.2 Block parts..................................................................................................................................................... 402
20.1.3 Features.......................................................................................................................................................... 403
20.2 Modes of operation....................................................................................................................................................... 404
20.3 Memory map/register definition................................................................................................................................... 405
20.3.1 TCD memory................................................................................................................................................. 405
20.3.2 TCD initialization.......................................................................................................................................... 405
20.3.3 TCD structure.................................................................................................................................................405
20.3.4 Reserved memory and bit fields.....................................................................................................................406
20.3.1
Control Register (DMAx_CR).......................................................................................................................412
20.3.2
Error Status Register (DMAx_ES).................................................................................................................415
20.3.3
Enable Request Register (DMAx_ERQ)........................................................................................................417
20.3.4
Enable Error Interrupt Register (DMAx_EEI)...............................................................................................419
20.3.5
Clear Enable Error Interrupt Register (DMAx_CEEI).................................................................................. 420
20.3.6
Set Enable Error Interrupt Register (DMAx_SEEI)...................................................................................... 421
20.3.7
Clear Enable Request Register (DMAx_CERQ)........................................................................................... 422
20.3.8
Set Enable Request Register (DMAx_SERQ)............................................................................................... 423
20.3.9
Clear DONE Status Bit Register (DMAx_CDNE)........................................................................................ 424
20.3.10
Set START Bit Register (DMAx_SSRT)...................................................................................................... 425
20.3.11
Clear Error Register (DMAx_CERR)............................................................................................................426
20.3.12
Clear Interrupt Request Register (DMAx_CINT)..........................................................................................427
20.3.13
Interrupt Request Register (DMAx_INT)......................................................................................................428
20.3.14
Error Register (DMAx_ERR)........................................................................................................................ 429
20.3.15
Hardware Request Status Register (DMAx_HRS)........................................................................................ 431
20.3.16
Enable Asynchronous Request in Stop Register (DMAx_EARS).................................................................433
20.3.17
Channel n Priority Register (DMAx_DCHPRIn).......................................................................................... 434
20.3.18
TCD Source Address (DMAx_TCDn_SADDR)........................................................................................... 435
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20.3.19
TCD Signed Source Address Offset (DMAx_TCDn_SOFF)........................................................................435
20.3.20
TCD Transfer Attributes (DMAx_TCDn_ATTR).........................................................................................436
20.3.21
TCD Minor Byte Count (Minor Loop Mapping Disabled) (DMAx_TCDn_NBYTES_MLNO)................. 437
20.3.22 TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)
(DMAx_TCDn_NBYTES_MLOFFNO)....................................................................................................... 437
20.3.23 TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)
(DMAx_TCDn_NBYTES_MLOFFYES)..................................................................................................... 439
20.3.24
TCD Last Source Address Adjustment (DMAx_TCDn_SLAST).................................................................440
20.3.25
TCD Destination Address (DMAx_TCDn_DADDR)................................................................................... 440
20.3.26
TCD Signed Destination Address Offset (DMAx_TCDn_DOFF)................................................................441
20.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMAx_TCDn_CITER_ELINKYES)...........................................................................................................441
20.3.28 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMAx_TCDn_CITER_ELINKNO).............................................................................................................443
20.3.29
TCD Last Destination Address Adjustment/Scatter Gather Address (DMAx_TCDn_DLASTSGA)...........444
20.3.30
TCD Control and Status (DMAx_TCDn_CSR).............................................................................................444
20.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
(DMAx_TCDn_BITER_ELINKYES)...........................................................................................................447
20.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
(DMAx_TCDn_BITER_ELINKNO).............................................................................................................448
20.4 Functional description...................................................................................................................................................449
20.4.1 eDMA basic data flow................................................................................................................................... 449
20.4.2 Fault reporting and handling..........................................................................................................................452
20.4.3 Channel preemption....................................................................................................................................... 455
20.4.4 Performance................................................................................................................................................... 455
20.5 Initialization/application information........................................................................................................................... 459
20.5.1 eDMA initialization....................................................................................................................................... 459
20.5.2 Programming errors....................................................................................................................................... 461
20.5.3 Arbitration mode considerations....................................................................................................................462
20.5.4 Performing DMA transfers............................................................................................................................ 462
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20.5.5 Monitoring transfer descriptor status............................................................................................................. 466
20.5.6 Channel Linking.............................................................................................................................................468
20.5.7 Dynamic programming.................................................................................................................................. 469
Chapter 21
Smart Card Interface Module (EMV SIM)
21.1 Introduction...................................................................................................................................................................475
21.1.1 Features.......................................................................................................................................................... 475
21.2 Block Diagram..............................................................................................................................................................476
21.3 Design Overview.......................................................................................................................................................... 476
21.4 Signal Description.........................................................................................................................................................478
21.5 Memory Map and Registers..........................................................................................................................................479
21.5.1
Version ID Register (EMVSIMx_VER_ID)..................................................................................................480
21.5.2
Parameter Register (EMVSIMx_PARAM)................................................................................................... 480
21.5.3
Clock Configuration Register (EMVSIMx_CLKCFG)................................................................................. 481
21.5.4
Baud Rate Divisor Register (EMVSIMx_DIVISOR)....................................................................................482
21.5.5
Control Register (EMVSIMx_CTRL)........................................................................................................... 483
21.5.6
Interrupt Mask Register (EMVSIMx_INT_MASK)......................................................................................487
21.5.7
Receiver Threshold Register (EMVSIMx_RX_THD)...................................................................................490
21.5.8
Transmitter Threshold Register (EMVSIMx_TX_THD).............................................................................. 490
21.5.9
Receive Status Register (EMVSIMx_RX_STATUS)....................................................................................492
21.5.10
Transmitter Status Register (EMVSIMx_TX_STATUS)..............................................................................495
21.5.11
Port Control and Status Register (EMVSIMx_PCSR)...................................................................................498
21.5.12
Receive Data Read Buffer (EMVSIMx_RX_BUF).......................................................................................500
21.5.13
Transmit Data Buffer (EMVSIMx_TX_BUF)...............................................................................................501
21.5.14
Transmitter Guard ETU Value Register (EMVSIMx_TX_GETU)...............................................................501
21.5.15
Character Wait Time Value Register (EMVSIMx_CWT_VAL)...................................................................502
21.5.16
Block Wait Time Value Register (EMVSIMx_BWT_VAL)........................................................................ 502
21.5.17
Block Guard Time Value Register (EMVSIMx_BGT_VAL)....................................................................... 503
21.5.18
General Purpose Counter 0 Timeout Value Register (EMVSIMx_GPCNT0_VAL)....................................503
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NXP Semiconductors 17
Section number Title Page
21.5.19
General Purpose Counter 1 Timeout Value (EMVSIMx_GPCNT1_VAL).................................................. 504
21.6 Functional Description..................................................................................................................................................504
21.6.1 Initialization................................................................................................................................................... 504
21.6.2 Smart Card Interface and Control.................................................................................................................. 506
21.6.3 EMV SIM Receiver....................................................................................................................................... 509
21.6.4 EMV SIM Transmitter...................................................................................................................................513
21.6.5 LRC and CRC................................................................................................................................................ 515
21.6.6 Message Handling..........................................................................................................................................517
21.6.7 Protocol Timers..............................................................................................................................................519
21.6.8 Answer To Reset (ATR) Detection................................................................................................................522
Chapter 22
Flexible I/O (FlexIO)
22.1 Introduction...................................................................................................................................................................527
22.1.1 Overview........................................................................................................................................................527
22.1.2 Features.......................................................................................................................................................... 527
22.1.3 Block Diagram............................................................................................................................................... 528
22.1.4 Modes of operation........................................................................................................................................ 529
22.1.5 FlexIO Signal Descriptions............................................................................................................................529
22.2 Memory Map and Registers..........................................................................................................................................529
22.2.1 FLEXIO Register Descriptions......................................................................................................................529
22.3 Functional description...................................................................................................................................................559
22.3.1 Shifter operation.............................................................................................................................................559
22.3.2 Timer operation..............................................................................................................................................565
22.3.3 Pin operation.................................................................................................................................................. 567
22.4 Application Information................................................................................................................................................569
22.4.1 UART Transmit............................................................................................................................................. 569
22.4.2 UART Receive...............................................................................................................................................570
22.4.3 SPI Master......................................................................................................................................................572
22.4.4 SPI Slave........................................................................................................................................................574
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18 NXP Semiconductors
Section number Title Page
22.4.5 I2C Master......................................................................................................................................................575
22.4.6 I2S Master......................................................................................................................................................577
22.4.7 I2S Slave........................................................................................................................................................ 579
22.4.8 Camera Interface............................................................................................................................................580
22.4.9 Motorola 68K/Intel 8080 Bus Interface.........................................................................................................581
22.4.10 Low Power State Machine............................................................................................................................. 583
Chapter 23
Flash Memory Controller (FMC)
23.1 Introduction...................................................................................................................................................................587
23.1.1 Overview........................................................................................................................................................587
23.1.2 Features.......................................................................................................................................................... 588
23.2 Modes of operation....................................................................................................................................................... 588
23.3 External signal description............................................................................................................................................588
23.4 Memory map and register descriptions.........................................................................................................................588
23.5 Flash Access Control (FAC) Function..........................................................................................................................589
23.5.1 Memory map and register definitions............................................................................................................ 589
23.5.2 FAC functional description............................................................................................................................589
23.6 Initialization and application information.....................................................................................................................595
Chapter 24
Flash Memory Module (FTFA)
24.1 Introduction...................................................................................................................................................................597
24.1.1 Features.......................................................................................................................................................... 598
24.1.2 Block Diagram............................................................................................................................................... 598
24.1.3 Glossary......................................................................................................................................................... 599
24.2 External Signal Description.......................................................................................................................................... 600
24.3 Memory Map and Registers..........................................................................................................................................601
24.3.1 Flash Configuration Field Description...........................................................................................................601
24.3.2 Program Flash IFR Map.................................................................................................................................601
24.3.3 Program Flash Erasable IFR Map..................................................................................................................602
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NXP Semiconductors 19
Section number Title Page
24.3.4 Register Descriptions..................................................................................................................................... 603
24.4 Functional Description..................................................................................................................................................617
24.4.1 Flash Protection..............................................................................................................................................617
24.4.2 Flash Access Protection................................................................................................................................. 617
24.4.3 Interrupts........................................................................................................................................................ 619
24.4.4 Flash Operation in Low-Power Modes.......................................................................................................... 620
24.4.5 Functional Modes of Operation..................................................................................................................... 620
24.4.6 Flash Reads and Ignored Writes.................................................................................................................... 620
24.4.7 Read While Write (RWW).............................................................................................................................621
24.4.8 Flash Program and Erase................................................................................................................................621
24.4.9 Flash Command Operations...........................................................................................................................621
24.4.10 Margin Read Commands............................................................................................................................... 627
24.4.11 Flash Command Description..........................................................................................................................628
24.4.12 Security.......................................................................................................................................................... 647
24.4.13 Reset Sequence.............................................................................................................................................. 650
Chapter 25
Interrupt Multiplexer (INTMUX)
25.1 About this module.........................................................................................................................................................651
25.1.1 Introduction....................................................................................................................................................651
25.1.2 Features.......................................................................................................................................................... 651
25.1.3 Block diagram................................................................................................................................................651
25.2 Memory Map and register definition............................................................................................................................ 652
25.2.1
Channel n Control Status Register (INTMUXx_CHn_CSR)........................................................................ 653
25.2.2
Channel n Vector Number Register (INTMUXx_CHn_VEC)......................................................................654
25.2.3
Channel n Interrupt Enable Register (INTMUXx_CHn_IER_31_0)............................................................ 655
25.2.4
Channel n Interrupt Pending Register (INTMUXx_CHn_IPR_31_0)...........................................................655
25.3 Functional Description..................................................................................................................................................656
25.3.1 Configuring Output Channels........................................................................................................................ 656
25.3.2 INTMUX Vectors.......................................................................................................................................... 656
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20 NXP Semiconductors
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