Section number Title Page
5.3.3.1 Initial checks and configurations.........................................................................................................40
5.3.3.2 Runtime checks....................................................................................................................................40
5.3.4 Internal RC oscillators......................................................................................................................................... 40
5.3.4.1 Initial checks and configurations.........................................................................................................41
5.3.4.2 Runtime checks....................................................................................................................................41
5.4 Flash................................................................................................................................................................................. 42
5.4.1 Flash memory...................................................................................................................................................... 42
5.4.1.1 EEPROM............................................................................................................................................. 42
5.4.1.2 Runtime checks....................................................................................................................................43
5.4.1.3 Security................................................................................................................................................44
5.5 SRAM...............................................................................................................................................................................44
5.5.1 Error Correction Code (ECC)..............................................................................................................................44
5.6 Processing modules.......................................................................................................................................................... 45
5.6.1 Cortex-M4 Structural Core Self Test (SCST)..................................................................................................... 45
5.6.2 Disabled modes of operation............................................................................................................................... 45
5.6.2.1 Debug mode.........................................................................................................................................45
5.6.3 Additional configuration information..................................................................................................................46
5.6.3.1 Stack.................................................................................................................................................... 47
5.6.3.2 WCT101xS configuration....................................................................................................................47
5.6.4 Crossbar Switch (AXBS-Lite).............................................................................................................................49
5.6.4.1 Runtime checks....................................................................................................................................49
5.6.5 Memory protection unit....................................................................................................................................... 49
5.6.5.1 Memory Protection Unit (MPU)..........................................................................................................49
5.6.5.2 Initial checks and configurations.........................................................................................................50
5.6.6 Nested Vectored Interrupt Controller (NVIC).....................................................................................................50
5.6.6.1 Periodic low latency IRQs...................................................................................................................50
5.6.6.2 Runtime checks....................................................................................................................................51
5.6.7 Enhanced Direct Memory Access (eDMA).........................................................................................................51
5.6.7.1 Runtime checks....................................................................................................................................51
MWCT101xS Safety Manual, Rev. 2, Aug 2018
NXP Semiconductors 5