KL27 Sub-Family Reference Manual
Supports: MKL27Z32VFM4, MKL27Z64VFM4, MKL27Z32VLH4,
MKL27Z64VLH4, MKL27Z32VDA4, MKL27Z64VDA4,
MKL27Z32VFT4, MKL27Z64VFT4, MKL27Z32VMP4,
MKL27Z64VMP4
Document Number: KL27P64M48SF2RM
Rev. 4.1, 07/2016
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................37
1.1.1 Purpose...........................................................................................................................................................37
1.1.2 Audience........................................................................................................................................................ 37
1.2 Conventions.................................................................................................................................................................. 37
1.2.1 Numbering systems........................................................................................................................................37
1.2.2 Typographic notation..................................................................................................................................... 38
1.2.3 Special terms..................................................................................................................................................38
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................39
2.1.1 Sub-family introduction................................................................................................................................. 39
2.2 Module functional categories........................................................................................................................................40
2.2.1 ARM Cortex-M0+ core modules................................................................................................................... 41
2.2.2 System modules............................................................................................................................................. 41
2.2.3 Memories and memory interfaces..................................................................................................................42
2.2.4 Clocks.............................................................................................................................................................42
2.2.5 Security and integrity modules...................................................................................................................... 43
2.2.6 Analog modules............................................................................................................................................. 43
2.2.7 Timer modules............................................................................................................................................... 43
2.2.8 Communication interfaces............................................................................................................................. 44
2.2.9 Human-machine interfaces............................................................................................................................ 44
2.3 Module to module interconnects...................................................................................................................................45
2.3.1 Interconnection overview...............................................................................................................................45
2.3.2 Analog reference options............................................................................................................................... 47
Chapter 3
Core Overview
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3.1 ARM Cortex-M0+ core introduction............................................................................................................................49
3.1.1 Buses, interconnects, and interfaces.............................................................................................................. 49
3.1.2 System tick timer........................................................................................................................................... 49
3.1.3 Debug facilities.............................................................................................................................................. 49
3.1.4 Core privilege levels...................................................................................................................................... 50
3.2 Nested vectored interrupt controller (NVIC) ...............................................................................................................50
3.2.1 Interrupt priority levels.................................................................................................................................. 50
3.2.2 Non-maskable interrupt..................................................................................................................................50
3.2.3 Interrupt channel assignments........................................................................................................................50
3.3 AWIC introduction....................................................................................................................................................... 53
3.3.1 Wake-up sources............................................................................................................................................53
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................55
4.2 System memory map.....................................................................................................................................................55
4.3 Bit Manipulation Engine...............................................................................................................................................56
4.4 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................56
4.4.1 Peripheral bridge (AIPS-Lite) memory map..................................................................................................57
4.5 Interrupts.......................................................................................................................................................................61
4.5.1 Interrupt priority levels.................................................................................................................................. 61
4.5.2 Non-maskable interrupt..................................................................................................................................61
4.5.3 Interrupt channel assignments........................................................................................................................61
4.6 SRAM sizes.................................................................................................................................................................. 63
4.7 Flash memory............................................................................................................................................................... 64
4.8 System Register file......................................................................................................................................................64
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................65
5.2 Programming model......................................................................................................................................................65
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5.3 High-level device clocking diagram............................................................................................................................. 65
5.4 Clock definitions...........................................................................................................................................................66
5.4.1 Device clock summary...................................................................................................................................67
5.5 Internal clocking requirements..................................................................................................................................... 69
5.5.1 Clock divider values after reset......................................................................................................................70
5.5.2 VLPR mode clocking.....................................................................................................................................70
5.6 Clock gating..................................................................................................................................................................71
5.7 Module clocks...............................................................................................................................................................71
5.7.1 PMC 1-kHz LPO clock..................................................................................................................................72
5.7.2 COP clocking................................................................................................................................................. 72
5.7.3 RTC clocking................................................................................................................................................. 73
5.7.4 RTC_CLKOUT and CLKOUT32K clocking................................................................................................73
5.7.5 LPTMR clocking............................................................................................................................................74
5.7.6 TPM clocking.................................................................................................................................................75
5.7.7 USB FS device only controller clocking........................................................................................................75
5.7.8 LPUART clocking......................................................................................................................................... 76
5.7.9 FlexIO clocking..............................................................................................................................................77
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................79
6.2 Reset..............................................................................................................................................................................79
6.2.1 Power-on reset (POR).................................................................................................................................... 80
6.2.2 System reset sources...................................................................................................................................... 80
6.2.3 MCU resets.................................................................................................................................................... 83
6.2.4 RESET pin .................................................................................................................................................... 84
6.3 Boot...............................................................................................................................................................................84
6.3.1 Boot sources...................................................................................................................................................85
6.3.2 FOPT boot options.........................................................................................................................................85
6.3.3 Boot sequence................................................................................................................................................ 87
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Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................91
7.2 Clocking modes............................................................................................................................................................ 91
7.2.1 Partial Stop.....................................................................................................................................................91
7.2.2 DMA Wakeup................................................................................................................................................92
7.2.3 Compute Operation........................................................................................................................................93
7.2.4 Peripheral Doze..............................................................................................................................................94
7.2.5 Clock gating................................................................................................................................................... 95
7.3 Power modes.................................................................................................................................................................95
7.4 Entering and exiting power modes............................................................................................................................... 97
7.5 Module operation in low-power modes........................................................................................................................ 98
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................103
8.1.1 Flash security................................................................................................................................................. 103
8.1.2 Security interactions with other modules.......................................................................................................103
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................105
9.2 Debug port pin descriptions..........................................................................................................................................105
9.3 SWD status and control registers..................................................................................................................................106
9.3.1 MDM-AP Control Register............................................................................................................................107
9.3.2 MDM-AP Status Register.............................................................................................................................. 108
9.4 Debug resets..................................................................................................................................................................110
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................110
9.6 Debug in low-power modes..........................................................................................................................................111
9.7 Debug and security....................................................................................................................................................... 112
Chapter 10
Pinouts and Packaging
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10.1 Introduction...................................................................................................................................................................113
10.2 Signal multiplexing integration.................................................................................................................................... 113
10.2.1 Clock gating................................................................................................................................................... 114
10.2.2 Signal multiplexing constraints......................................................................................................................114
10.3 KL27 Signal Multiplexing and Pin Assignments......................................................................................................... 114
10.4 KL27 Family Pinouts....................................................................................................................................................117
10.5 Module Signal Description Tables................................................................................................................................121
10.5.1 Core modules................................................................................................................................................. 121
10.5.2 System modules............................................................................................................................................. 121
10.5.3 Clock modules................................................................................................................................................122
10.5.4 Memories and memory interfaces..................................................................................................................122
10.5.5 Analog............................................................................................................................................................122
10.5.6 Timer Modules...............................................................................................................................................123
10.5.7 Communication interfaces............................................................................................................................. 124
10.5.8 Human-machine interfaces (HMI).................................................................................................................126
Chapter 11
Port Control and Interrupts (PORT)
11.1 Chip-specific PORT information..................................................................................................................................127
11.2 Port control and interrupt summary.............................................................................................................................. 128
11.3 Introduction...................................................................................................................................................................129
11.4 Overview.......................................................................................................................................................................129
11.4.1 Features.......................................................................................................................................................... 129
11.4.2 Modes of operation........................................................................................................................................ 130
11.5 External signal description............................................................................................................................................131
11.6 Detailed signal description............................................................................................................................................131
11.7 Memory map and register definition.............................................................................................................................131
11.7.1
Pin Control Register n (PORTx_PCRn).........................................................................................................137
11.7.2
Global Pin Control Low Register (PORTx_GPCLR)....................................................................................140
11.7.3
Global Pin Control High Register (PORTx_GPCHR)...................................................................................140
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11.7.4
Interrupt Status Flag Register (PORTx_ISFR).............................................................................................. 141
11.8 Functional description...................................................................................................................................................141
11.8.1 Pin control......................................................................................................................................................141
11.8.2 Global pin control.......................................................................................................................................... 142
11.8.3 External interrupts..........................................................................................................................................142
Chapter 12
System Integration Module (SIM)
12.1 Chip-specific SIM information.....................................................................................................................................145
12.1.1 COP clocks.....................................................................................................................................................145
12.2 Introduction...................................................................................................................................................................145
12.2.1 Features.......................................................................................................................................................... 145
12.3 Memory map and register definition.............................................................................................................................146
12.3.1 System Options Register 1 (SIM_SOPT1).................................................................................................... 147
12.3.2 System Options Register 2 (SIM_SOPT2).................................................................................................... 148
12.3.3 System Options Register 4 (SIM_SOPT4).................................................................................................... 150
12.3.4 System Options Register 5 (SIM_SOPT5).................................................................................................... 151
12.3.5 System Options Register 7 (SIM_SOPT7).................................................................................................... 153
12.3.6 System Device Identification Register (SIM_SDID).....................................................................................154
12.3.7 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................155
12.3.8 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................157
12.3.9 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................159
12.3.10 System Clock Gating Control Register 7 (SIM_SCGC7)..............................................................................161
12.3.11 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................161
12.3.12 Flash Configuration Register 1 (SIM_FCFG1)............................................................................................. 163
12.3.13 Flash Configuration Register 2 (SIM_FCFG2)............................................................................................. 165
12.3.14 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................166
12.3.15 Unique Identification Register Mid Low (SIM_UIDML)............................................................................. 166
12.3.16 Unique Identification Register Low (SIM_UIDL)........................................................................................ 167
12.3.17 COP Control Register (SIM_COPC)............................................................................................................. 167
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12.3.18 Service COP (SIM_SRVCOP).......................................................................................................................169
12.4 Functional description...................................................................................................................................................169
12.4.1 COP watchdog operation............................................................................................................................... 169
Chapter 13
Kinetis ROM Bootloader
13.1 Chip-Specific Information............................................................................................................................................ 173
13.2 Introduction...................................................................................................................................................................173
13.3 Functional Description..................................................................................................................................................175
13.3.1 Memory Maps................................................................................................................................................175
13.3.2 The Kinetis Bootloader Configuration Area (BCA)......................................................................................176
13.3.3 Start-up Process..............................................................................................................................................177
13.3.4 Clock Configuration.......................................................................................................................................179
13.3.5 Bootloader Entry Point...................................................................................................................................180
13.3.6 Bootloader Protocol....................................................................................................................................... 181
13.3.7 Bootloader Packet Types............................................................................................................................... 186
13.3.8 Bootloader Command API.............................................................................................................................193
13.3.9 Bootloader Exit state......................................................................................................................................208
13.4 Peripherals Supported................................................................................................................................................... 209
13.4.1 I2C Peripheral................................................................................................................................................ 209
13.4.2 SPI Peripheral................................................................................................................................................ 211
13.4.3 LPUART Peripheral.......................................................................................................................................213
13.4.4 USB peripheral...............................................................................................................................................216
13.5 Get/SetProperty Command Properties..........................................................................................................................220
13.5.1 Property Definitions.......................................................................................................................................221
13.6 Kinetis Bootloader Status Error Codes.........................................................................................................................222
Chapter 14
System Mode Controller (SMC)
14.1 Chip-specific SMC information....................................................................................................................................225
14.2 Introduction...................................................................................................................................................................225
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14.3 Modes of operation....................................................................................................................................................... 225
14.4 Memory map and register descriptions.........................................................................................................................227
14.4.1 Power Mode Protection register (SMC_PMPROT).......................................................................................228
14.4.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................229
14.4.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................231
14.4.4 Power Mode Status register (SMC_PMSTAT)............................................................................................. 232
14.5 Functional description...................................................................................................................................................233
14.5.1 Power mode transitions..................................................................................................................................233
14.5.2 Power mode entry/exit sequencing................................................................................................................ 236
14.5.3 Run modes......................................................................................................................................................238
14.5.4 Wait modes.................................................................................................................................................... 240
14.5.5 Stop modes.....................................................................................................................................................241
14.5.6 Debug in low power modes........................................................................................................................... 244
Chapter 15
Power Management Controller (PMC)
15.1 Introduction...................................................................................................................................................................247
15.2 Features.........................................................................................................................................................................247
15.3 Low-voltage detect (LVD) system................................................................................................................................247
15.3.1 LVD reset operation.......................................................................................................................................248
15.3.2 LVD interrupt operation.................................................................................................................................248
15.3.3 Low-voltage warning (LVW) interrupt operation......................................................................................... 248
15.4 I/O retention..................................................................................................................................................................249
15.5 Memory map and register descriptions.........................................................................................................................249
15.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1).......................................................... 250
15.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2).......................................................... 251
15.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................252
Chapter 16
Crossbar Switch Lite (AXBS-Lite)
16.1 Chip-specific AXBS-Lite information..........................................................................................................................255
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16.1.1 Crossbar-light switch master assignments..................................................................................................... 255
16.1.2 Crossbar switch slave assignments................................................................................................................ 255
16.2 Introduction...................................................................................................................................................................255
16.2.1 Features.......................................................................................................................................................... 256
16.3 Memory Map / Register Definition...............................................................................................................................256
16.4 Functional Description..................................................................................................................................................256
16.4.1 General operation...........................................................................................................................................256
16.4.2 Arbitration......................................................................................................................................................257
16.5 Initialization/application information........................................................................................................................... 259
Chapter 17
Peripheral Bridge (AIPS-Lite)
17.1 Chip-specific AIPS-Lite information............................................................................................................................261
17.1.1 Number of peripheral bridges........................................................................................................................ 261
17.1.2 Memory maps................................................................................................................................................ 261
17.2 Introduction...................................................................................................................................................................261
17.2.1 Features.......................................................................................................................................................... 261
17.2.2 General operation...........................................................................................................................................262
17.3 Functional description...................................................................................................................................................262
17.3.1 Access support............................................................................................................................................... 262
Chapter 18
Low-Leakage Wakeup Unit (LLWU)
18.1 Chip-specific LLWU information.................................................................................................................................263
18.1.1 LLWU interrupt............................................................................................................................................. 263
18.1.2 Wake-up Sources........................................................................................................................................... 263
18.2 Introduction...................................................................................................................................................................264
18.2.1 Features.......................................................................................................................................................... 264
18.2.2 Modes of operation........................................................................................................................................ 265
18.2.3 Block diagram................................................................................................................................................266
18.3 LLWU signal descriptions............................................................................................................................................ 267
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18.4 Memory map/register definition................................................................................................................................... 267
18.4.1 LLWU Pin Enable 1 register (LLWU_PE1)..................................................................................................268
18.4.2 LLWU Pin Enable 2 register (LLWU_PE2)..................................................................................................269
18.4.3 LLWU Pin Enable 3 register (LLWU_PE3)..................................................................................................270
18.4.4 LLWU Pin Enable 4 register (LLWU_PE4)..................................................................................................271
18.4.5 LLWU Module Enable register (LLWU_ME).............................................................................................. 272
18.4.6 LLWU Flag 1 register (LLWU_F1)...............................................................................................................274
18.4.7 LLWU Flag 2 register (LLWU_F2)...............................................................................................................276
18.4.8 LLWU Flag 3 register (LLWU_F3)...............................................................................................................277
18.4.9 LLWU Pin Filter 1 register (LLWU_FILT1)................................................................................................ 279
18.4.10 LLWU Pin Filter 2 register (LLWU_FILT2)................................................................................................ 280
18.5 Functional description...................................................................................................................................................281
18.5.1 LLS mode.......................................................................................................................................................282
18.5.2 VLLS modes.................................................................................................................................................. 282
18.5.3 Initialization................................................................................................................................................... 282
Chapter 19
Direct Memory Access Multiplexer (DMAMUX)
19.1 Chip-specific DMAMUX information......................................................................................................................... 283
19.1.1 DMA MUX Request Sources........................................................................................................................ 283
19.1.2 DMA transfers via PIT trigger.......................................................................................................................285
19.2 Introduction...................................................................................................................................................................285
19.2.1 Overview........................................................................................................................................................285
19.2.2 Features.......................................................................................................................................................... 286
19.2.3 Modes of operation........................................................................................................................................ 286
19.3 External signal description............................................................................................................................................287
19.4 Memory map/register definition................................................................................................................................... 287
19.4.1
Channel Configuration register (DMAMUXx_CHCFGn)............................................................................ 287
19.5 Functional description...................................................................................................................................................288
19.5.1 DMA channels with periodic triggering capability........................................................................................289
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19.5.2 DMA channels with no triggering capability.................................................................................................291
19.5.3 Always-enabled DMA sources...................................................................................................................... 291
19.6 Initialization/application information........................................................................................................................... 293
19.6.1 Reset...............................................................................................................................................................293
19.6.2 Enabling and configuring sources..................................................................................................................293
Chapter 20
Reset Control Module (RCM)
20.1 Introduction...................................................................................................................................................................297
20.2 Reset memory map and register descriptions............................................................................................................... 297
20.2.1 System Reset Status Register 0 (RCM_SRS0).............................................................................................. 298
20.2.2 System Reset Status Register 1 (RCM_SRS1).............................................................................................. 299
20.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................ 300
20.2.4 Reset Pin Filter Width register (RCM_RPFW)............................................................................................. 301
20.2.5 Force Mode Register (RCM_FM)..................................................................................................................303
20.2.6 Mode Register (RCM_MR)........................................................................................................................... 303
20.2.7 Sticky System Reset Status Register 0 (RCM_SSRS0).................................................................................304
20.2.8 Sticky System Reset Status Register 1 (RCM_SSRS1).................................................................................305
Chapter 21
DMA Controller Module
21.1 Introduction...................................................................................................................................................................307
21.1.1 Overview........................................................................................................................................................307
21.1.2 Features.......................................................................................................................................................... 308
21.2 DMA Transfer Overview..............................................................................................................................................309
21.3 Memory Map/Register Definition.................................................................................................................................310
21.3.1
Source Address Register (DMA_SARn)....................................................................................................... 311
21.3.2
Destination Address Register (DMA_DARn)............................................................................................... 312
21.3.3
DMA Status Register / Byte Count Register (DMA_DSR_BCRn)...............................................................313
21.3.4
DMA Control Register (DMA_DCRn)..........................................................................................................315
21.4 Functional Description..................................................................................................................................................319
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21.4.1 Transfer requests (Cycle-Steal and Continuous modes)................................................................................319
21.4.2 Channel initialization and startup.................................................................................................................. 320
21.4.3 Dual-Address Data Transfer Mode................................................................................................................321
21.4.4 Advanced Data Transfer Controls: Auto-Alignment.....................................................................................322
21.4.5 Termination....................................................................................................................................................323
Chapter 22
Miscellaneous Control Module (MCM)
22.1 Introduction...................................................................................................................................................................325
22.1.1 Features.......................................................................................................................................................... 325
22.2 Memory map/register descriptions............................................................................................................................... 325
22.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................326
22.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC).............................................................. 326
22.2.3 Platform Control Register (MCM_PLACR)..................................................................................................327
22.2.4 Compute Operation Control Register (MCM_CPO)..................................................................................... 330
Chapter 23
Timer/PWM Module (TPM)
23.1 Chip-specific TPM information....................................................................................................................................333
23.1.1 TPM instantiation information.......................................................................................................................333
23.1.2 Clock options................................................................................................................................................. 334
23.1.3 Trigger options...............................................................................................................................................334
23.1.4 Global timebase..............................................................................................................................................335
23.1.5 TPM interrupts............................................................................................................................................... 335
23.2 Introduction...................................................................................................................................................................336
23.2.1 TPM Philosophy............................................................................................................................................ 336
23.2.2 Features.......................................................................................................................................................... 336
23.2.3 Modes of operation........................................................................................................................................ 337
23.2.4 Block diagram................................................................................................................................................337
23.3 TPM Signal Descriptions..............................................................................................................................................338
23.3.1 TPM_EXTCLK — TPM External Clock...................................................................................................... 338
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23.3.2 TPM_CHn — TPM Channel (n) I/O Pin.......................................................................................................339
23.4 Memory Map and Register Definition..........................................................................................................................339
23.4.1
Status and Control (TPMx_SC)..................................................................................................................... 341
23.4.2
Counter (TPMx_CNT)................................................................................................................................... 342
23.4.3
Modulo (TPMx_MOD)..................................................................................................................................343
23.4.4
Channel (n) Status and Control (TPMx_CnSC).............................................................................................344
23.4.5
Channel (n) Value (TPMx_CnV)...................................................................................................................346
23.4.6
Capture and Compare Status (TPMx_STATUS)...........................................................................................346
23.4.7
Channel Polarity (TPMx_POL)..................................................................................................................... 348
23.4.8
Configuration (TPMx_CONF).......................................................................................................................349
23.5 Functional description...................................................................................................................................................352
23.5.1 Clock domains................................................................................................................................................352
23.5.2 Prescaler.........................................................................................................................................................353
23.5.3 Counter...........................................................................................................................................................353
23.5.4 Input Capture Mode....................................................................................................................................... 356
23.5.5 Output Compare Mode...................................................................................................................................357
23.5.6 Edge-Aligned PWM (EPWM) Mode.............................................................................................................358
23.5.7 Center-Aligned PWM (CPWM) Mode..........................................................................................................360
23.5.8 Registers Updated from Write Buffers.......................................................................................................... 362
23.5.9 DMA.............................................................................................................................................................. 362
23.5.10 Output triggers............................................................................................................................................... 363
23.5.11 Reset Overview..............................................................................................................................................363
23.5.12 TPM Interrupts...............................................................................................................................................364
Chapter 24
Analog-to-Digital Converter (ADC)
24.1 Chip-specific ADC information....................................................................................................................................365
24.1.1 ADC instantiation information.......................................................................................................................365
24.1.2 DMA Support on ADC.................................................................................................................................. 366
24.1.3 ADC0 connections/channel assignment.........................................................................................................366
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24.1.4 ADC analog supply and reference connections............................................................................................. 367
24.1.5 ADC Reference Options................................................................................................................................ 368
24.1.6 Alternate clock............................................................................................................................................... 368
24.2 Introduction...................................................................................................................................................................368
24.2.1 Features.......................................................................................................................................................... 369
24.2.2 Block diagram................................................................................................................................................369
24.3 ADC signal descriptions............................................................................................................................................... 370
24.3.1 Analog Power (VDDA)................................................................................................................................. 371
24.3.2 Analog Ground (VSSA).................................................................................................................................371
24.3.3 Voltage Reference Select...............................................................................................................................371
24.3.4 Analog Channel Inputs (ADx)....................................................................................................................... 372
24.3.5 Differential Analog Channel Inputs (DADx).................................................................................................372
24.4 Memory map and register definitions...........................................................................................................................372
24.4.1
ADC Status and Control Registers 1 (ADCx_SC1n).....................................................................................373
24.4.2
ADC Configuration Register 1 (ADCx_CFG1).............................................................................................377
24.4.3
ADC Configuration Register 2 (ADCx_CFG2).............................................................................................378
24.4.4
ADC Data Result Register (ADCx_Rn).........................................................................................................379
24.4.5
Compare Value Registers (ADCx_CVn)....................................................................................................... 381
24.4.6
Status and Control Register 2 (ADCx_SC2)..................................................................................................382
24.4.7
Status and Control Register 3 (ADCx_SC3)..................................................................................................384
24.4.8
ADC Offset Correction Register (ADCx_OFS).............................................................................................385
24.4.9
ADC Plus-Side Gain Register (ADCx_PG)...................................................................................................386
24.4.10
ADC Minus-Side Gain Register (ADCx_MG).............................................................................................. 386
24.4.11
ADC Plus-Side General Calibration Value Register (ADCx_CLPD)........................................................... 387
24.4.12
ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............................................................388
24.4.13
ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............................................................ 388
24.4.14
ADC Plus-Side General Calibration Value Register (ADCx_CLP3)............................................................ 389
24.4.15
ADC Plus-Side General Calibration Value Register (ADCx_CLP2)............................................................ 389
24.4.16
ADC Plus-Side General Calibration Value Register (ADCx_CLP1)............................................................ 390
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24.4.17
ADC Plus-Side General Calibration Value Register (ADCx_CLP0)............................................................ 390
24.4.18
ADC Minus-Side General Calibration Value Register (ADCx_CLMD).......................................................391
24.4.19
ADC Minus-Side General Calibration Value Register (ADCx_CLMS)....................................................... 391
24.4.20
ADC Minus-Side General Calibration Value Register (ADCx_CLM4)....................................................... 392
24.4.21
ADC Minus-Side General Calibration Value Register (ADCx_CLM3)....................................................... 392
24.4.22
ADC Minus-Side General Calibration Value Register (ADCx_CLM2)....................................................... 393
24.4.23
ADC Minus-Side General Calibration Value Register (ADCx_CLM1)....................................................... 393
24.4.24
ADC Minus-Side General Calibration Value Register (ADCx_CLM0)....................................................... 394
24.5 Functional description...................................................................................................................................................394
24.5.1 Clock select and divide control......................................................................................................................395
24.5.2 Voltage reference selection............................................................................................................................396
24.5.3 Hardware trigger and channel selects............................................................................................................ 396
24.5.4 Conversion control.........................................................................................................................................397
24.5.5 Automatic compare function..........................................................................................................................405
24.5.6 Calibration function....................................................................................................................................... 406
24.5.7 User-defined offset function.......................................................................................................................... 408
24.5.8 Temperature sensor........................................................................................................................................409
24.5.9 MCU wait mode operation.............................................................................................................................410
24.5.10 MCU Normal Stop mode operation...............................................................................................................410
24.5.11 MCU Low-Power Stop mode operation........................................................................................................ 411
24.6 Initialization information.............................................................................................................................................. 412
24.6.1 ADC module initialization example.............................................................................................................. 412
24.7 Application information................................................................................................................................................414
24.7.1 External pins and routing............................................................................................................................... 414
24.7.2 Sources of error..............................................................................................................................................416
Chapter 25
Comparator (CMP)
25.1 Chip-specific CMP information....................................................................................................................................421
25.1.1 CMP instantiation information.......................................................................................................................421
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NXP Semiconductors 17
Section number Title Page
25.1.2 CMP input connections..................................................................................................................................421
25.1.3 CMP external references................................................................................................................................422
25.1.4 CMP trigger mode..........................................................................................................................................422
25.2 Introduction...................................................................................................................................................................423
25.2.1 CMP features..................................................................................................................................................423
25.2.2 6-bit DAC key features.................................................................................................................................. 424
25.2.3 ANMUX key features.................................................................................................................................... 424
25.2.4 CMP, DAC and ANMUX diagram................................................................................................................424
25.2.5 CMP block diagram....................................................................................................................................... 425
25.3 Memory map/register definitions..................................................................................................................................427
25.3.1
CMP Control Register 0 (CMPx_CR0)......................................................................................................... 427
25.3.2
CMP Control Register 1 (CMPx_CR1)......................................................................................................... 428
25.3.3
CMP Filter Period Register (CMPx_FPR).....................................................................................................429
25.3.4
CMP Status and Control Register (CMPx_SCR)...........................................................................................430
25.3.5
DAC Control Register (CMPx_DACCR)......................................................................................................431
25.3.6
MUX Control Register (CMPx_MUXCR).................................................................................................... 431
25.4 Functional description...................................................................................................................................................432
25.4.1 CMP functional modes...................................................................................................................................433
25.4.2 Power modes..................................................................................................................................................436
25.4.3 Startup and operation..................................................................................................................................... 437
25.4.4 Low-pass filter............................................................................................................................................... 438
25.5 CMP interrupts..............................................................................................................................................................440
25.6 DMA support................................................................................................................................................................ 440
25.7 CMP Asynchronous DMA support...............................................................................................................................440
25.8 Digital-to-analog converter...........................................................................................................................................441
25.9 DAC functional description.......................................................................................................................................... 441
25.9.1 Voltage reference source select......................................................................................................................441
25.10 DAC resets....................................................................................................................................................................442
25.11 DAC clocks...................................................................................................................................................................442
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18 NXP Semiconductors
Section number Title Page
25.12 DAC interrupts..............................................................................................................................................................442
25.13 CMP Trigger Mode.......................................................................................................................................................442
Chapter 26
Voltage Reference (VREFV1)
26.1 Introduction...................................................................................................................................................................443
26.1.1 Overview........................................................................................................................................................444
26.1.2 Features.......................................................................................................................................................... 444
26.1.3 Modes of Operation....................................................................................................................................... 444
26.1.4 VREF Signal Descriptions.............................................................................................................................445
26.2 Memory Map and Register Definition..........................................................................................................................445
26.2.1 VREF Trim Register (VREF_TRM)..............................................................................................................446
26.2.2 VREF Status and Control Register (VREF_SC)............................................................................................447
26.3 Functional Description..................................................................................................................................................448
26.3.1 Voltage Reference Disabled, SC[VREFEN] = 0........................................................................................... 448
26.3.2 Voltage Reference Enabled, SC[VREFEN] = 1............................................................................................ 449
26.4 Internal voltage regulator..............................................................................................................................................450
26.5 Initialization/Application Information..........................................................................................................................451
Chapter 27
Multipurpose Clock Generator Lite (MCG_Lite)
27.1 Introduction ..................................................................................................................................................................453
27.1.1 Features ......................................................................................................................................................... 453
27.1.2 Block diagram ...............................................................................................................................................454
27.2 Memory map and register definition.............................................................................................................................454
27.2.1 MCG Control Register 1 (MCG_C1).............................................................................................................455
27.2.2 MCG Control Register 2 (MCG_C2).............................................................................................................456
27.2.3 MCG Status Register (MCG_S).................................................................................................................... 457
27.2.4 MCG Status and Control Register (MCG_SC)..............................................................................................457
27.2.5 MCG Miscellaneous Control Register (MCG_MC)......................................................................................458
27.3 Functional description...................................................................................................................................................459
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NXP Semiconductors 19
Section number Title Page
27.3.1 Clock mode switching ...................................................................................................................................459
27.3.2 LIRC divider 1 .............................................................................................................................................. 460
27.3.3 LIRC divider 2 .............................................................................................................................................. 460
27.3.4 Enable LIRC in Stop mode ........................................................................................................................... 460
27.3.5 MCG-Lite in Low-power mode .................................................................................................................... 461
27.3.6 HIRC USB recovery ..................................................................................................................................... 461
Chapter 28
Oscillator (OSC)
28.1 Chip-specific OSC information.................................................................................................................................... 463
28.1.1 OSC modes of operation with MCG_Lite and RTC......................................................................................463
28.2 Introduction...................................................................................................................................................................463
28.3 Features and Modes...................................................................................................................................................... 463
28.4 Block Diagram..............................................................................................................................................................464
28.5 OSC Signal Descriptions.............................................................................................................................................. 465
28.6 External Crystal / Resonator Connections.................................................................................................................... 465
28.7 External Clock Connections......................................................................................................................................... 467
28.8 Memory Map/Register Definitions...............................................................................................................................467
28.8.1 OSC Memory Map/Register Definition.........................................................................................................468
28.9 Functional Description..................................................................................................................................................469
28.9.1 OSC module states.........................................................................................................................................469
28.9.2 OSC module modes....................................................................................................................................... 471
28.9.3 Counter...........................................................................................................................................................473
28.9.4 Reference clock pin requirements..................................................................................................................473
28.10 Reset..............................................................................................................................................................................473
28.11 Low power modes operation.........................................................................................................................................474
28.12 Interrupts.......................................................................................................................................................................474
Chapter 29
Real Time Clock (RTC)
29.1 Chip-specific RTC information.................................................................................................................................... 475
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20 NXP Semiconductors
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