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NXP
KL2x
NXP KL2x Reference guide
Type
Reference guide
Brand
NXP
Size
9.22 MB
Pages
807
Language
English
View document
NXP KL2x Reference guide
Type
Reference guide
Brand
NXP
Size
4.42 MB
Pages
939
Language
English
Table of contents
Purpose
39
Audience
39
Numbering systems
39
Typographic notation
40
Special terms
40
Sub-family introduction
41
ARM Cortex-M0+ core modules
43
System modules
43
Memories and memory interfaces
44
Clocks
44
Security and integrity modules
45
Analog modules
45
Timer modules
45
Communication interfaces
46
Human-machine interfaces
47
Interconnection overview
47
Analog reference options
49
Buses, interconnects, and interfaces
51
System tick timer
51
Debug facilities
51
Core privilege levels
52
Interrupt priority levels
52
Non-maskable interrupt
52
Interrupt channel assignments
52
Determining the bitfield and register location for configuring a particular interrupt
54
Wake-up sources
55
Flash memory map
57
Flash security
58
Flash modes
58
Erase all flash contents
58
FTFA_FOPT register
59
SRAM sizes
59
SRAM ranges
59
SRAM retention in low power modes
60
Read-after-write sequence and required serialization of memory operations
62
Peripheral bridge (AIPS-Lite) memory map
63
Device clock summary
69
Clock divider values after reset
72
VLPR mode clocking
72
PMC 1-kHz LPO clock
74
COP clocking
74
RTC clocking
75
RTC_CLKOUT and CLKOUT32K clocking
75
LPTMR clocking
76
TPM clocking
77
USB FS device only controller clocking
77
LPUART clocking
78
FlexIO clocking
79
I2S/SAI clocking
80
Power-on reset (POR)
82
System reset sources
82
External pin reset (RESET)
82
RESET pin filter
82
Low-voltage detect (LVD)
83
Computer operating properly (COP) watchdog timer
83
Low leakage wakeup (LLWU)
83
Stop mode acknowledge error (SACKERR)
84
Software reset (SW)
84
Lockup reset (LOCKUP)
84
MDM-AP system reset request
85
MCU resets
85
RESET pin
86
Boot sources
87
FOPT boot options
87
Boot sequence
89
Partial Stop
91
DMA Wakeup
92
Compute Operation
93
Peripheral Doze
94
Clock gating
95
Flash security
103
Security interactions with other modules
103
Security interactions with Debug
104
MDM-AP Control Register
107
MDM-AP Status Register
108
Clock gating
114
Signal multiplexing constraints
114
Core modules
120
System modules
120
Clock modules
121
Analog
121
Timer Modules
122
Communication interfaces
123
Human-machine interfaces (HMI)
126
Features
129
Modes of operation
130
Run mode
130
Wait mode
130
Stop mode
130
Debug mode
130
Pin control
141
Global pin control
142
External interrupts
142
COP clocks
145
Features
145
SIM
146
SIM_SOPT1
147
SIM_SOPT1CFG
148
SIM_SOPT2
150
SIM_SOPT4
152
SIM_SOPT5
153
SIM_SOPT7
155
SIM_SDID
156
SIM_SCGC4
158
SIM_SCGC5
160
SIM_SCGC6
162
SIM_SCGC7
164
SIM_CLKDIV1
164
SIM_FCFG1
166
SIM_FCFG2
167
SIM_UIDMH
168
SIM_UIDML
169
SIM_UIDL
169
SIM_COPC
170
SIM_SRVCOP
171
COP watchdog operation
172
Memory Maps
177
The Kinetis Bootloader Configuration Area (BCA)
178
Start-up Process
179
Clock Configuration
181
Bootloader Entry Point
182
Bootloader Protocol
183
Command with no data phase
183
Command with incoming data phase
184
Command with outgoing data phase
186
Bootloader Packet Types
188
Ping packet
188
Ping Response Packet
189
Framing Packet
189
Command packet
191
Data packet
193
Response packet
193
Bootloader Command API
195
Execute command
195
Reset command
196
GetProperty command
197
SetProperty command
199
FlashEraseAll command
201
FlashEraseRegion command
202
FlashEraseAllUnsecure command
203
FlashSecurityDisable command
204
WriteMemory command
206
Read memory command
208
Bootloader Exit state
210
I2C Peripheral
211
SPI Peripheral
213
USB peripheral
215
Property Definitions
220
SMC
228
SMC_PMPROT
228
SMC_PMCTRL
229
SMC_STOPCTRL
230
SMC_PMSTAT
232
Power mode transitions
232
Power mode entry/exit sequencing
235
Stop mode entry sequence
235
Stop mode exit sequence
236
Aborted stop mode entry
236
Transition to wait modes
236
Transition from stop modes to Debug mode
236
Run modes
236
RUN mode
237
Very-Low Power Run (VLPR) mode
237
Wait modes
238
WAIT mode
238
Very-Low-Power Wait (VLPW) mode
238
Stop modes
239
STOP mode
239
Very-Low-Power Stop (VLPS) mode
240
Low-Leakage Stop (LLS) mode
240
Very-Low-Leakage Stop (VLLSx) modes
241
Debug in low power modes
242
LVD reset operation
244
LVD interrupt operation
244
Low-voltage warning (LVW) interrupt operation
244
PMC
245
PMC_LVDSC1
246
PMC_LVDSC2
247
PMC_REGSC
248
Features
251
MCM
251
MCM_PLASC
252
MCM_PLAMC
252
MCM_PLACR
253
MCM_CPO
256
Crossbar-light switch master assignments
259
Crossbar switch slave assignments
259
Features
260
General operation
260
Arbitration
261
Arbitration during undefined length bursts
261
Fixed-priority operation
261
Round-robin priority operation
262
Wake-up Sources
265
Features
266
Modes of operation
267
LLS mode
267
VLLS modes
267
Non-low leakage modes
267
Debug mode
267
Block diagram
268
LLWU
270
LLWU_PE1
270
LLWU_PE2
271
LLWU_PE3
272
LLWU_PE4
273
LLWU_ME
274
LLWU_F1
276
LLWU_F2
278
LLWU_F3
279
LLWU_FILT1
281
LLWU_FILT2
282
LLS mode
284
VLLS modes
284
Initialization
284
Number of peripheral bridges
285
Memory maps
285
Features
285
General operation
286
AIPS
286
AIPS_MPRA
286
AIPS_PACRn
288
Access support
293
DMA MUX Request Sources
295
DMA transfers via PIT trigger
297
Overview
297
Features
298
Modes of operation
298
DMA channels with periodic triggering capability
301
DMA channels with no triggering capability
303
Always-enabled DMA sources
303
Reset
305
Enabling and configuring sources
305
Overview
309
Features
310
DMA
313
DMA_SARn
313
DMA_DARn
314
DMA_DSR_BCRn
315
DMA_DCRn
317
Transfer requests (Cycle-Steal and Continuous modes)
321
Channel initialization and startup
322
Channel prioritization
322
Programming the DMA Controller Module
322
Dual-Address Data Transfer Mode
323
Advanced Data Transfer Controls: Auto-Alignment
324
Termination
325
RCM
327
RCM_SRS0
328
RCM_SRS1
329
RCM_RPFC
330
RCM_RPFW
331
RCM_FM
333
RCM_MR
333
RCM_SSRS0
334
RCM_SSRS1
335
ADC instantiation information
337
DMA Support on ADC
337
ADC0 connections/channel assignment
338
ADC analog supply and reference connections
339
Alternate clock
339
Features
340
Block diagram
341
Analog Power (VDDA)
342
Analog Ground (VSSA)
342
Voltage Reference Select
342
Analog Channel Inputs (ADx)
343
Differential Analog Channel Inputs (DADx)
343
Clock select and divide control
366
Voltage reference selection
367
Hardware trigger and channel selects
367
Conversion control
368
Initiating conversions
368
Completing conversions
369
Aborting conversions
369
Power control
370
Sample time and total conversion time
370
Conversion time examples
373
Typical conversion time configuration
373
Long conversion time configuration
374
Short conversion time configuration
375
Hardware average function
375
Automatic compare function
376
Calibration function
377
User-defined offset function
379
Temperature sensor
380
MCU wait mode operation
381
MCU Normal Stop mode operation
381
Normal Stop mode with ADACK disabled
381
Normal Stop mode with ADACK enabled
382
MCU Low-Power Stop mode operation
382
ADC module initialization example
383
Initialization sequence
383
Pseudo-code example
383
External pins and routing
385
Analog supply pins
385
Analog voltage reference pins
386
Analog input pins
387
Sources of error
387
Sampling error
387
Pin leakage error
388
Noise-induced errors
388
Code width and quantization error
389
Linearity errors
390
Code jitter, non-monotonicity, and missing codes
390
CMP instantiation information
393
CMP input connections
393
CMP external references
394
CMP trigger mode
394
CMP features
395
6-bit DAC key features
396
ANMUX key features
396
CMP, DAC and ANMUX diagram
396
CMP block diagram
397
CMP functional modes
405
Disabled mode (# 1)
406
Continuous mode (#s 2A & 2B)
406
Sampled, Non-Filtered mode (#s 3B)
407
Sampled, Filtered mode (#s 4B)
408
Power modes
408
Wait mode operation
408
Stop mode operation
409
Low-Leakage mode operation
409
Background Debug Mode Operation
409
Startup and operation
409
Low-pass filter
410
Enabling filter modes
410
Latency issues
411
Voltage reference source select
413
DAC data buffer operation
421
DAC data buffer interrupts
421
Modes of DAC data buffer operation
422
DMA operation
423
Resets
423
Low-Power mode operation
423
Overview
426
Features
426
Modes of Operation
426
VREF Signal Descriptions
427
VREF
427
VREF_TRM
428
VREF_SC
429
Voltage Reference Disabled, SC[VREFEN] = 0
430
Voltage Reference Enabled, SC[VREFEN] = 1
430
SC[MODE_LV]=00
431
SC[MODE_LV] = 01
431
SC[MODE_LV] = 10
431
SC[MODE_LV] = 11
432
Features
435
Block diagram
436
MCG
437
MCG_C1
437
MCG_C2
438
MCG_S
439
MCG_SC
439
MCG_MC
440
Clock mode switching
441
LIRC divider 1
442
LIRC divider 2
442
Enable LIRC in Stop mode
442
MCG-Lite in Low-power mode
442
HIRC USB recovery
443
OSC modes of operation with MCG_Lite and RTC
445
OSC module states
451
Off
452
Oscillator startup
452
Oscillator Stable
453
External Clock mode
453
OSC module modes
453
Low-Frequency, High-Gain Mode
454
Low-Frequency, Low-Power Mode
454
High-Frequency, High-Gain Mode
454
High-Frequency, Low-Power Mode
455
Counter
455
Reference clock pin requirements
455
TPM instantiation information
457
Clock options
458
Trigger options
458
Global timebase
459
TPM interrupts
459
TPM Philosophy
460
Features
460
Modes of operation
461
Block diagram
461
TPM_EXTCLK — TPM External Clock
462
TPM_CHn — TPM Channel (n) I/O Pin
463
Clock domains
476
Counter Clock Mode
476
Prescaler
477
Counter
477
Up counting
477
Up-down counting
478
Counter Reset
479
Global time base (GTB)
479
Counter trigger
479
Input Capture Mode
480
Output Compare Mode
481
Edge-Aligned PWM (EPWM) Mode
482
Center-Aligned PWM (CPWM) Mode
484
Registers Updated from Write Buffers
486
MOD Register Update
486
CnV Register Update
486
DMA
486
Output triggers
487
Reset Overview
487
TPM Interrupts
488
Timer Overflow Interrupt
488
Channel (n) Interrupt
488
PIT/DMA periodic trigger assignments
489
PIT/ADC triggers
489
PIT/TPM triggers
489
PIT/DAC triggers
489
Block diagram
490
Features
490
PIT
491
PIT_MCR
492
PIT_LTMR64H
493
PIT_LTMR64L
493
PIT_LDVALn
494
PIT_CVALn
494
PIT_TCTRLn
495
PIT_TFLGn
496
General operation
496
Timers
497
Debug mode
498
Interrupts
498
Chained timers
498
LPTMR instantiation information
503
LPTMR pulse counter input options
503
LPTMR prescaler/glitch filter clocking options
503
Features
504
Modes of operation
505
Detailed signal descriptions
505
LPTMR power and reset
510
LPTMR clocking
510
LPTMR prescaler/glitch filter
511
Prescaler enabled
511
Prescaler bypassed
511
Glitch filter
511
Glitch filter bypassed
512
LPTMR compare
512
LPTMR counter
512
LPTMR hardware trigger
513
LPTMR interrupt
513
RTC Instantiation Information
515
RTC_CLKOUT options
515
Features
515
Modes of operation
516
RTC signal descriptions
516
RTC clock output
516
RTC
517
RTC_TSR
517
RTC_TPR
517
RTC_TAR
518
RTC_TCR
518
RTC_CR
520
RTC_SR
522
RTC_LR
523
RTC_IER
524
Power, clocking, and reset
525
Oscillator control
525
Software reset
525
Supervisor access
525
Time counter
526
Compensation
526
Time alarm
527
Update mode
527
Register lock
528
Interrupt
528
Universal Serial Bus (USB) FS Subsystem
529
USB Wakeup
529
USB Power Distribution
530
USB power management
532
References
532
USB
533
USBFS Features
534
Data Structures
534
On-chip transceiver required external components
534
Buffer Descriptor Table
536
USB data transfers—Receive (Rx) and Transmit (Tx)
537
Addressing BDT entries
538
Buffer Descriptors (BDs)
538
USB transaction
541
Overview
565
Features
566
Modes of Operation
567
Features
570
Modes of operation
570
Block diagrams
571
SPI system block diagram
571
SPI module block diagram
572
SPSCK — SPI Serial Clock
575
MOSI — Master Data Out, Slave Data In
575
MISO — Master Data In, Slave Data Out
575
SS — Slave Select
575
General
590
Master mode
590
Slave mode
592
SPI FIFO Mode
593
SPI Transmission by DMA
594
Transmit by DMA
594
Receive by DMA
595
Data Transmission Length
596
SPI clock formats
597
SPI baud rate generation
600
Special features
600
SS Output
600
Bidirectional mode (MOMI or SISO)
601
Error conditions
602
Mode fault error
602
Low-power mode options
603
SPI in Run mode
603
SPI in Wait mode
603
SPI in Stop mode
604
Reset
604
Interrupts
605
MODF
605
SPRF
605
SPTEF
606
SPMF
606
TNEAREF
606
RNFULLF
606
Asynchronous interrupt in low-power modes
607
Initialization sequence
607
Pseudo-Code Example
608
I2C instantiation information
613
Features
614
Modes of operation
614
Block diagram
615
I2C protocol
629
START signal
630
Slave address transmission
630
Data transfers
631
STOP signal
631
Repeated START signal
631
Arbitration procedure
632
Clock synchronization
632
Handshaking
633
Clock stretching
633
I2C divider and hold values
633
10-bit address
634
Master-transmitter addresses a slave-receiver
635
Master-receiver addresses a slave-transmitter
635
Address matching
636
System management bus specification
637
Timeouts
637
SCL low timeout
637
SCL high timeout
637
CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT
638
FAST ACK and NACK
639
Resets
639
Interrupts
639
Byte transfer interrupt
640
Address detect interrupt
640
Stop Detect Interrupt
641
Exit from low-power/stop modes
641
Arbitration lost interrupt
641
Timeout interrupt in SMBus
641
Programmable input glitch filter
642
Address matching wake-up
642
DMA support
643
Double buffering mode
644
LPUART0 and LPUART1 overview
649
Features
649
Modes of operation
650
Signal Descriptions
651
Block diagram
651
Baud rate generation
667
Transmitter functional description
668
Send break and queued idle
669
Receiver functional description
670
Data sampling technique
671
Receiver wakeup operation
671
Idle-line wakeup
673
Address-mark wakeup
673
Data match wakeup
673
Address Match operation
674
Idle Match operation
674
Match On Match Off operation
675
Additional LPUART functions
675
8-bit, 9-bit and 10-bit data modes
675
Idle length
676
Loop mode
677
Single-wire operation
677
Interrupts and status flags
677
UART2 Overview
679
Features
679
Modes of operation
681
Run mode
681
Stop mode
681
Detailed signal descriptions
682
Transmitter
710
Transmitter character length
711
Transmission bit order
711
Character transmission
712
Transmitting break characters
713
Idle characters
714
Receiver
714
Receiver character length
715
Receiver bit ordering
715
Character reception
716
Data sampling
716
Framing errors
721
Receiving break characters
721
Baud rate tolerance
722
Slow data tolerance
722
Fast data tolerance
723
Receiver wakeup
724
Idle input line wakeup (C1[WAKE] = 0)
724
Address mark wakeup (C1[WAKE] = 1)
725
Match address operation
725
Baud rate generation
726
Data format (non ISO-7816)
728
Eight-bit configuration
728
Nine-bit configuration
728
Timing examples
729
Eight-bit format with parity disabled
730
Eight-bit format with parity enabled
730
Nine-bit format with parity disabled
730
Nine-bit format with parity enabled
730
Non-memory mapped tenth bit for parity
731
Single-wire operation
731
Loop operation
731
ISO-7816/smartcard support
732
Initial characters
733
Protocol T = 0
733
Protocol T = 1
734
Wait time and guard time parameters
735
ATR Duration Time Counter
736
Baud rate generation
737
UART restrictions in ISO-7816 operation
737
RXEDGIF description
738
RxD edge detect sensitivity
738
Clearing RXEDGIF interrupt request
739
Exit from low-power modes
739
ISO-7816 initialization sequence
740
Transmission procedure for (C7816[TTYPE] = 0)
741
Transmission procedure for (C7816[TTYPE] = 1)
741
Initialization sequence (non ISO-7816)
741
Overrun (OR) flag implications
742
Overrun operation
743
Overrun NACK considerations
743
Match address registers
744
Clearing 7816 wait timer (WT, BWT, CWT) interrupts
744
Legacy and reverse compatibility considerations
744
FlexIO Instantiation
747
FlexIO Trigger options
747
Features
748
Block Diagram
749
Modes of operation
749
FlexIO Signal Descriptions
750
FLEXIO
750
FLEXIO_VERID
752
FLEXIO_PARAM
753
FLEXIO_CTRL
754
FLEXIO_SHIFTSTAT
755
FLEXIO_SHIFTERR
756
FLEXIO_TIMSTAT
756
FLEXIO_SHIFTSIEN
757
FLEXIO_SHIFTEIEN
758
FLEXIO_TIMIEN
758
FLEXIO_SHIFTSDEN
759
FLEXIO_SHIFTCTLn
759
FLEXIO_SHIFTCFGn
761
FLEXIO_SHIFTBUFn
762
FLEXIO_SHIFTBUFBISn
763
FLEXIO_SHIFTBUFBYSn
763
FLEXIO_SHIFTBUFBBSn
764
FLEXIO_TIMCTLn
764
FLEXIO_TIMCFGn
766
FLEXIO_TIMCMPn
768
Shifter operation
769
Timer operation
771
Pin operation
773
UART Transmit
774
UART Receive
775
SPI Master
777
SPI Slave
779
I2C Master
781
I2S Master
783
I2S Slave
784
Instantiation information
787
I2S Interrupts
787
I2S/SAI clocking
787
I2S/SAI operation in low power modes
789
Features
790
Block diagram
791
Modes of operation
791
SAI clocking
814
SAI resets
816
Synchronous modes
817
Frame sync configuration
817
Data FIFO
818
Data alignment
818
FIFO pointers
819
FIFO packing
820
Word mask register
821
Interrupts and DMA requests
821
FIFO warning flag
821
FIFO error flag
821
Sync error flag
822
Word start flag
822
GPIO instantiation information
823
Pull devices and directions
823
GPIO accessibility in the memory map
823
Features
824
Modes of operation
824
GPIO signal descriptions
824
Detailed signal description
825
General-purpose input
835
General-purpose output
835
IOPORT
836
Overview
838
Features
838
Modes of operation
839
BME decorated stores
840
Decorated store logical AND (AND)
842
Decorated store logical OR (OR)
843
Decorated store logical XOR (XOR)
844
Decorated store bit field insert (BFI)
845
BME decorated loads
847
Decorated load: load-and-clear 1 bit (LAC1)
850
Decorated Load: Load-and-Set 1 Bit (LAS1)
851
Decorated load unsigned bit field extract (UBFX)
852
Additional details on decorated addresses and GPIO accesses
853
Overview
857
Features
860
Modes of operation
861
MTB_RAM Memory Map
862
MTB
862
MTB_POSITION
864
MTB_MASTER
865
MTB_FLOW
867
MTB_BASE
869
MTB_MODECTRL
869
MTB_TAGSET
870
MTB_TAGCLEAR
870
MTB_LOCKACCESS
871
MTB_LOCKSTAT
871
MTB_AUTHSTAT
871
MTB_DEVICEARCH
872
MTB_DEVICECFG
873
MTB_DEVICETYPID
873
MTB_PERIPHIDn
874
MTB_COMPIDn
874
MTB_DWT Memory Map
874
MTBDWT
875
MTBDWT_CTRL
876
MTBDWT_COMPn
877
MTBDWT_MASKn
877
MTBDWT_FCT0
878
MTBDWT_FCT1
880
MTBDWT_TBCTRL
881
MTBDWT_DEVICECFG
883
MTBDWT_DEVICETYPID
883
MTBDWT_PERIPHIDn
884
MTBDWT_COMPIDn
884
System ROM Memory Map
884
ROM
885
ROM_ENTRYn
886
ROM_TABLEMARK
887
ROM_SYSACCESS
887
ROM_PERIPHIDn
888
ROM_COMPIDn
888
Overview
889
Features
889
Features
893
Program Flash Memory Features
894
Other Flash Memory Module Features
894
Block Diagram
894
Glossary
895
Flash Configuration Field Description
897
Program Flash IFR Map
897
Program Once Field
898
Register Descriptions
898
FTFA
898
FTFA_FSTAT
899
FTFA_FCNFG
901
FTFA_FSEC
902
FTFA_FOPT
903
FTFA_FCCOBn
904
FTFA_FPROTn
905
Flash Protection
907
Interrupts
908
Flash Operation in Low-Power Modes
909
Wait Mode
909
Stop Mode
909
Functional Modes of Operation
909
Flash Reads and Ignored Writes
909
Read While Write (RWW)
910
Flash Program and Erase
910
Flash Command Operations
910
Command Write Sequence
910
Load the FCCOB Registers
911
Launch the Command by Clearing CCIF
911
Command Execution and Error Reporting
911
Flash Commands
913
Flash Commands by Mode
915
Allowed Simultaneous Flash Operations
915
Margin Read Commands
916
Flash Command Description
917
Read 1s Block Command
917
Read 1s Section Command
918
Program Check Command
919
Read Resource Command
921
Program Longword Command
922
Erase Flash Block Command
923
Erase Flash Sector Command
924
Suspending an Erase Flash Sector Operation
925
Resuming a Suspended Erase Flash Sector Operation
925
Aborting a Suspended Erase Flash Sector Operation
925
Read 1s All Blocks Command
927
Read Once Command
928
Program Once Command
929
Erase All Blocks Command
930
Triggering an Erase All External to the Flash Memory Module
931
Verify Backdoor Access Key Command
931
Erase All Blocks Unsecure Command
932
Security
933
Flash Memory Access by Mode and Security
934
Changing the Security State
934
Unsecuring the Chip Using Backdoor Key Access
934
Reset Sequence
935
View document
NXP KL2x Reference guide
Type
Reference guide
Brand
NXP
Size
7.58 MB
Pages
1401
Language
English
View document
NXP KL2x Reference guide
Type
Reference guide
Brand
NXP
Size
4.40 MB
Pages
891
Language
English
View document
NXP KL2x Reference guide
Type
Reference guide
Brand
NXP
Size
8.79 MB
Pages
764
Language
English
Table of contents
Purpose
31
Audience
31
Numbering systems
31
Typographic notation
32
Special terms
32
ARM® Cortex™-M0+ Core Modules
37
System Modules
38
Memories and Memory Interfaces
39
Clocks
39
Security and Integrity modules
39
Analog modules
40
Timer modules
40
Communication interfaces
41
Human-machine interfaces
41
Module to Module Interconnects
43
Analog reference options
46
ARM Cortex-M0+ Core Configuration
46
ARM Cortex M0+ Core
47
Buses, Interconnects, and Interfaces
48
System Tick Timer
48
Debug Facilities
48
Core Privilege Levels
49
Nested Vectored Interrupt Controller (NVIC) Configuration
49
Interrupt priority levels
49
Non-maskable interrupt
50
Interrupt channel assignments
50
Determining the bitfield and register location for configuring a particular interrupt
52
Asynchronous wake-up interrupt controller (AWIC) configuration
52
Wake-up sources
53
SIM Configuration
54
System Mode Controller (SMC) Configuration
54
VLLS2 not supported
55
PMC Configuration
55
Low-Leakage Wake-up Unit (LLWU) Configuration
56
LLWU interrupt
57
Wake-up Sources
57
MCM Configuration
58
Crossbar-Light Switch Configuration
59
Crossbar-Light Switch Master Assignments
60
Crossbar Switch Slave Assignments
60
Peripheral Bridge Configuration
60
Number of peripheral bridges
61
Memory maps
61
DMA request multiplexer configuration
61
DMA MUX Request Sources
62
DMA transfers via PIT trigger
64
DMA Controller Configuration
64
Computer Operating Properly (COP) Watchdog Configuration
65
COP clocks
66
COP watchdog operation
66
Clock Gating
67
MCG Configuration
68
MCG FLL modes
68
OSC Configuration
69
OSC modes of operation with MCG and RTC
69
Flash Memory Configuration
70
Flash Memory Sizes
70
Flash Memory Map
71
Flash Security
71
Flash Modes
71
Erase All Flash Contents
72
FTFA_FOPT Register
72
Flash Memory Controller Configuration
72
SRAM Configuration
73
SRAM Sizes
73
SRAM Ranges
74
SRAM retention in low power modes
75
12-bit SAR ADC Configuration
75
ADC Instantiation Information
76
DMA Support on ADC
77
ADC0 Connections/Channel Assignment
77
ADC Analog Supply and Reference Connections
78
ADC Reference Options
78
CMP Configuration
78
CMP Instantiation Information
79
CMP input connections
80
CMP external references
80
CMP trigger mode
80
Timer/PWM Module Configuration
81
TPM Instantiation Information
81
Clock Options
82
Trigger Options
82
Global Timebase
83
TPM Interrupts
83
PIT Configuration
84
PIT/DMA Periodic Trigger Assignments
84
PIT/ADC Triggers
84
PIT/TPM Triggers
85
PIT/DAC Triggers
85
Low-power timer configuration
85
LPTMR Instantiation Information
85
LPTMR pulse counter input options
86
LPTMR prescaler/glitch filter clocking options
86
RTC configuration
87
RTC Instantiation Information
87
RTC_CLKOUT options
87
Universal Serial Bus (USB) FS Subsystem
88
USB Wakeup
88
USB Power Distribution
88
USB power management
90
USB controller configuration
91
USB Voltage Regulator Configuration
91
SPI configuration
92
SPI Instantiation Information
93
I2C Configuration
93
IIC Instantiation Information
94
UART Configuration
94
UART0 overview
94
UART1 and UART2 Overview
95
GPIO Configuration
95
GPIO Instantiation Information
96
Pull Devices and Directions
96
Port Control and Interrupt Summary
96
GPIO accessibility in the memory map
97
Alternate Non-Volatile IRC User Trim Description
100
Read-after-write sequence and required serialization of memory operations
102
Peripheral Bridge (AIPS-Lite) Memory Map
103
Modules Restricted Access in User Mode
106
Device clock summary
111
Clock divider values after reset
113
VLPR mode clocking
114
PMC 1-kHz LPO clock
116
COP clocking
116
RTC clocking
117
LPTMR clocking
117
TPM clocking
118
USB FS OTG Controller clocking
118
UART clocking
119
Power-on reset (POR)
122
System reset sources
122
External pin reset (RESET)
122
Reset pin filter
122
Low-voltage detect (LVD)
123
Computer operating properly (COP) watchdog timer
123
Low leakage wakeup (LLWU)
124
Multipurpose clock generator loss-of-clock (LOC)
124
MCG loss-of-lock (LOL) reset
124
Stop mode acknowledge error (SACKERR)
125
Software reset (SW)
125
Lockup reset (LOCKUP)
125
MDM-AP system reset request
125
MCU Resets
125
Reset Pin
127
Debug resets
127
Resetting the Debug subsystem
127
Boot sources
128
FOPT boot options
128
Boot sequence
129
Partial Stop
131
DMA Wakeup
132
Compute Operation
133
Peripheral Doze
134
Clock Gating
135
Security Interactions with Debug
144
MDM-AP Control Register
147
MDM-AP Status Register
148
Port control and interrupt module features
154
Clock gating
155
Signal multiplexing constraints
155
KL24 Signal Multiplexing and Pin Assignments
155
KL24 Pinouts
158
Core Modules
162
System Modules
163
Clock Modules
163
Memories and Memory Interfaces
163
Analog
163
Timer Modules
164
Communication Interfaces
165
Human-Machine Interfaces (HMI)
167
Features
169
Modes of operation
170
Run mode
170
Wait mode
170
Stop mode
170
Debug mode
170
Pin control
181
Global pin control
182
External interrupts
182
Features
185
SIM
186
SIM_SOPT1
187
SIM_SOPT1CFG
188
SIM_SOPT2
189
SIM_SOPT4
191
SIM_SOPT5
193
SIM_SOPT7
194
SIM_SDID
196
SIM_SCGC4
198
SIM_SCGC5
200
SIM_SCGC6
201
SIM_SCGC7
203
SIM_CLKDIV1
203
SIM_FCFG1
205
SIM_FCFG2
206
SIM_UIDMH
207
SIM_UIDML
208
SIM_UIDL
208
SIM_COPC
209
SIM_SRVCOP
210
SMC
213
SMC_PMPROT
213
SMC_PMCTRL
215
SMC_STOPCTRL
216
SMC_PMSTAT
217
Power mode transitions
218
Power mode entry/exit sequencing
221
Stop mode entry sequence
222
Stop mode exit sequence
223
Aborted stop mode entry
223
Transition to wait modes
223
Transition from stop modes to Debug mode
223
Run modes
223
RUN mode
224
Very-Low Power Run (VLPR) mode
224
Wait modes
225
WAIT mode
225
Very-Low-Power Wait (VLPW) mode
225
Stop modes
226
STOP mode
226
Very-Low-Power Stop (VLPS) mode
227
Low-Leakage Stop (LLS) mode
227
Very-Low-Leakage Stop (VLLSx) modes
228
Debug in low power modes
229
LVD reset operation
232
LVD interrupt operation
232
Low-voltage warning (LVW) interrupt operation
232
PMC
233
PMC_LVDSC1
234
PMC_LVDSC2
235
PMC_REGSC
236
Features
239
Modes of operation
240
LLS mode
240
VLLS modes
240
Non-low leakage modes
240
Debug mode
240
Block diagram
241
LLWU
243
LLWU_PE1
243
LLWU_PE2
244
LLWU_PE3
245
LLWU_PE4
246
LLWU_ME
247
LLWU_F1
249
LLWU_F2
251
LLWU_F3
252
LLWU_FILT1
254
LLWU_FILT2
255
LLS mode
257
VLLS modes
257
Initialization
257
RCM
259
RCM_SRS0
259
RCM_SRS1
261
RCM_RPFC
262
RCM_RPFW
263
Overview
266
Features
266
Modes of Operation
267
BME Decorated Stores
268
Decorated Store Logical AND (AND)
270
Decorated Store Logical OR (OR)
271
Decorated Store: Logical XOR (XOR)
272
Decorated Store Bit Field Insert (BFI)
273
BME Decorated Loads
274
Decorated Load Load-and-Clear 1 Bit (LAC1)
278
Decorated Load: Load-and-Set 1 Bit (LAS1)
279
Decorated Load Unsigned Bit Field Extract (UBFX)
280
Additional Details on Decorated Addresses and GPIO Accesses
281
Features
285
MCM
285
MCM_PLASC
286
MCM_PLAMC
287
MCM_PLACR
287
MCM_CPO
290
Overview
293
Features
296
Modes of Operation
297
MTB_RAM Memory Map
298
MTB
298
MTB_POSITION
300
MTB_MASTER
301
MTB_FLOW
303
MTB_BASE
304
MTB_MODECTRL
304
MTB_TAGSET
305
MTB_TAGCLEAR
305
MTB_LOCKACCESS
306
MTB_LOCKSTAT
306
MTB_AUTHSTAT
307
MTB_DEVICEARCH
308
MTB_DEVICECFG
308
MTB_DEVICETYPID
309
MTB_PERIPHIDn
309
MTB_COMPIDn
310
MTB_DWT Memory Map
310
MTBDWT
310
MTBDWT_CTRL
311
MTBDWT_COMPn
312
MTBDWT_MASKn
313
MTBDWT_FCT0
314
MTBDWT_FCT1
316
MTBDWT_TBCTRL
317
MTBDWT_DEVICECFG
319
MTBDWT_DEVICETYPID
319
MTBDWT_PERIPHIDn
320
MTBDWT_COMPIDn
320
System ROM Memory Map
320
ROM
321
ROM_ENTRYn
322
ROM_TABLEMARK
323
ROM_SYSACCESS
323
ROM_PERIPHIDn
324
ROM_COMPIDn
324
Features
325
General operation
326
Arbitration
327
Arbitration During Undefined Length Bursts
327
Fixed-priority operation
327
Round-robin priority operation
328
Features
329
General operation
329
Access support
330
Overview
331
Features
332
Modes of operation
332
DMA channels with periodic triggering capability
335
DMA channels with no triggering capability
337
Always-enabled DMA sources
337
Reset
338
Enabling and configuring sources
338
Overview
343
Features
344
DMA
347
DMA_SARn
347
DMA_DARn
348
DMA_DSR_BCRn
349
DMA_DCRn
351
Transfer Requests (Cycle-Steal and Continuous Modes)
355
Channel Initialization and Startup
355
Channel Prioritization
356
Programming the DMA Controller Module
356
Dual-Address Data Transfer Mode
357
Advanced Data Transfer Controls: Auto-Alignment
358
Termination
359
Features
361
Modes of Operation
364
MCG
365
MCG_C1
366
MCG_C2
367
MCG_C3
368
MCG_C4
368
MCG_C5
370
MCG_C6
371
MCG_S
372
MCG_SC
374
MCG_ATCVH
375
MCG_ATCVL
375
MCG_C7
376
MCG_C8
376
MCG_C9
377
MCG_C10
377
MCG mode state diagram
378
MCG modes of operation
378
MCG mode switching
381
Low Power Bit Usage
382
MCG Internal Reference Clocks
382
MCG Internal Reference Clock
382
External Reference Clock
383
MCG Fixed frequency clock
383
MCG PLL clock
384
MCG Auto TRIM (ATM)
384
MCG module initialization sequence
385
Initializing the MCG
385
Using a 32.768 kHz reference
387
MCG mode switching
388
Example 1: Moving from FEI to PEE mode: External Crystal = 4 MHz, MCGOUTCLK frequency = 48 MHz
389
Example 2: Moving from PEE to BLPI mode: MCGOUTCLK frequency =32 kHz
393
Example 3: Moving from BLPI to FEE mode
395
OSC Module States
404
Off
405
Oscillator Start-Up
405
Oscillator Stable
406
External Clock Mode
406
OSC Module Modes
406
Low-Frequency, Low-Power Mode
407
Counter
407
Reference Clock Pin Requirements
407
Overview
409
Features
409
Features
414
Program Flash Memory Features
414
Other Flash Memory Module Features
414
Block Diagram
414
Glossary
415
Flash Configuration Field Description
416
Program Flash IFR Map
417
Program Once Field
417
Register Descriptions
418
FTFA
418
FTFA_FSTAT
419
FTFA_FCNFG
420
FTFA_FSEC
422
FTFA_FOPT
423
FTFA_FCCOBn
424
FTFA_FPROTn
425
Flash Protection
427
Interrupts
427
Flash Operation in Low-Power Modes
428
Wait Mode
428
Stop Mode
428
Functional Modes of Operation
428
Flash Reads and Ignored Writes
428
Read While Write (RWW)
429
Flash Program and Erase
429
Flash Command Operations
429
Command Write Sequence
429
Load the FCCOB Registers
430
Launch the Command by Clearing CCIF
430
Command Execution and Error Reporting
430
Flash Commands
432
Flash Commands by Mode
433
Margin Read Commands
434
Flash Command Description
435
Read 1s Section Command
435
Program Check Command
436
Read Resource Command
437
Program Longword Command
438
Erase Flash Sector Command
440
Suspending an Erase Flash Sector Operation
440
Resuming a Suspended Erase Flash Sector Operation
441
Aborting a Suspended Erase Flash Sector Operation
441
Read 1s All Blocks Command
442
Read Once Command
443
Program Once Command
444
Erase All Blocks Command
445
Triggering an Erase All External to the Flash Memory Module
446
Verify Backdoor Access Key Command
446
Security
448
Flash Memory Access by Mode and Security
448
Changing the Security State
448
Unsecuring the Chip Using Backdoor Key Access
449
Reset Sequence
450
Features
451
Block diagram
452
Analog Power (VDDA)
454
Analog Ground (VSSA)
454
Voltage Reference Select
454
Analog Channel Inputs (ADx)
455
Clock select and divide control
472
Voltage reference selection
473
Hardware trigger and channel selects
473
Conversion control
474
Initiating conversions
475
Completing conversions
476
Aborting conversions
476
Power control
476
Sample time and total conversion time
477
Conversion time examples
479
Typical conversion time configuration
479
Short conversion time configuration
480
Hardware average function
481
Automatic compare function
481
Calibration function
483
User-defined offset function
484
Temperature sensor
485
MCU wait mode operation
486
MCU Normal Stop mode operation
486
Normal Stop mode with ADACK disabled
486
Normal Stop mode with ADACK enabled
487
MCU Low-Power Stop mode operation
487
ADC module initialization example
488
Initialization sequence
488
Pseudo-code example
488
External pins and routing
490
Analog supply pins
490
Analog voltage reference pins
491
Analog input pins
492
Sources of error
492
Sampling error
492
Pin leakage error
493
Noise-induced errors
493
Code width and quantization error
494
Linearity errors
494
Code jitter, non-monotonicity, and missing codes
495
CMP functional modes
508
Disabled mode (# 1)
510
Continuous mode (#s 2A & 2B)
510
Sampled, Non-Filtered mode (#s 3A & 3B)
511
Sampled, Filtered mode (#s 4A & 4B)
512
Windowed mode (#s 5A & 5B)
514
Windowed/Resampled mode (# 6)
516
Windowed/Filtered mode (#7)
517
Power modes
517
Wait mode operation
517
Stop mode operation
518
Low-Leakage mode operation
518
Background Debug Mode Operation
518
Startup and operation
518
Low-pass filter
519
Enabling filter modes
519
Latency issues
520
Voltage reference source select
523
TPM Philosophy
525
Features
525
Modes of Operation
526
Block Diagram
526
TPM_EXTCLK — TPM External Clock
527
TPM_CHn — TPM Channel (n) I/O Pin
528
Clock Domains
539
Counter Clock Mode
539
Prescaler
540
Counter
540
Up Counting
540
Up-Down Counting
541
Counter Reset
542
Input Capture Mode
542
Output Compare Mode
543
Edge-Aligned PWM (EPWM) Mode
544
Center-Aligned PWM (CPWM) Mode
546
Registers Updated from Write Buffers
548
MOD Register Update
548
CnV Register Update
548
DMA
548
Reset Overview
549
TPM Interrupts
549
Timer Overflow Interrupt
550
Channel (n) Interrupt
550
Block diagram
551
Features
552
PIT
553
PIT_MCR
553
PIT_LTMR64H
555
PIT_LTMR64L
555
PIT_LDVALn
556
PIT_CVALn
556
PIT_TCTRLn
557
PIT_TFLGn
558
General operation
558
Timers
558
Debug mode
560
Interrupts
560
Chained timers
560
Features
565
Modes of operation
565
Detailed signal descriptions
566
LPTMR power and reset
571
LPTMR clocking
571
LPTMR prescaler/glitch filter
571
Prescaler enabled
572
Prescaler bypassed
572
Glitch filter
572
Glitch filter bypassed
572
LPTMR compare
573
LPTMR counter
573
LPTMR hardware trigger
574
LPTMR interrupt
574
Features
575
Modes of operation
575
RTC Signal Descriptions
575
RTC clock output
576
RTC
576
RTC_TSR
577
RTC_TPR
577
RTC_TAR
578
RTC_TCR
578
RTC_CR
579
RTC_SR
581
RTC_LR
582
RTC_IER
583
Power, clocking, and reset
584
Oscillator control
584
Software reset
584
Supervisor access
585
Time counter
585
Compensation
585
Time alarm
586
Update mode
586
Register lock
587
Interrupt
587
USB
589
USB On-The-Go
590
USB-FS Features
591
Data Structures
591
Buffer Descriptor Table
592
RX vs. TX as a USB target device or USB host
593
Addressing BDT entries
594
Buffer Descriptors (BDs)
594
USB transaction
597
OTG dual role A device operation
626
OTG dual role B device operation
627
Overview
629
Features
630
Modes of Operation
631
Features
633
Modes of Operation
634
Block Diagrams
635
SPI System Block Diagram
635
SPI Module Block Diagram
635
SPSCK — SPI Serial Clock
637
MOSI — Master Data Out, Slave Data In
638
MISO — Master Data In, Slave Data Out
638
SS — Slave Select
638
General
646
Master Mode
647
Slave Mode
648
SPI Transmission by DMA
649
Transmit by DMA
650
Receive by DMA
651
SPI Clock Formats
651
SPI Baud Rate Generation
654
Special Features
655
SS Output
655
Bidirectional Mode (MOMI or SISO)
655
Error Conditions
656
Mode Fault Error
657
Low Power Mode Options
657
SPI in Run Mode
657
SPI in Wait Mode
657
SPI in Stop Mode
658
Reset
659
Interrupts
659
MODF
660
SPRF
660
SPTEF
660
SPMF
660
Asynchronous interrupt in low power modes
660
Initialization Sequence
661
Pseudo-Code Example
662
Features
665
Modes of operation
666
Block diagram
666
I2C protocol
680
START signal
680
Slave address transmission
681
Data transfers
681
STOP signal
682
Repeated START signal
682
Arbitration procedure
682
Clock synchronization
683
Handshaking
683
Clock stretching
683
I2C divider and hold values
684
10-bit address
685
Master-transmitter addresses a slave-receiver
685
Master-receiver addresses a slave-transmitter
686
Address matching
687
System management bus specification
687
Timeouts
687
SCL low timeout
688
SCL high timeout
688
CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT
688
FAST ACK and NACK
689
Resets
690
Interrupts
690
Byte transfer interrupt
691
Address detect interrupt
691
Stop Detect Interrupt
691
Exit from low-power/stop modes
691
Arbitration lost interrupt
691
Timeout interrupt in SMBus
692
Programmable input glitch filter
692
Address matching wakeup
693
DMA support
693
Features
699
Modes of operation
700
Block diagram
700
Baud rate generation
716
Transmitter functional description
716
Send break and queued idle
717
Receiver functional description
718
Data sampling technique
719
Receiver wakeup operation
720
Idle-line wakeup
720
Address-mark wakeup
720
Match address operation
721
Additional UART functions
721
8-bit, 9-bit and 10-bit data modes
721
Loop mode
722
Single-wire operation
722
Interrupts and status flags
723
Features
725
Modes of operation
725
Block diagram
726
Baud rate generation
739
Transmitter functional description
740
Send break and queued idle
741
Receiver functional description
742
Data sampling technique
743
Receiver wakeup operation
743
Idle-line wakeup
744
Address-mark wakeup
744
Interrupts and status flags
745
DMA Operation
746
Additional UART functions
747
8- and 9-bit data modes
747
Stop mode operation
747
Loop mode
747
Single-wire operation
748
Features
749
Modes of operation
749
GPIO signal descriptions
750
Detailed signal description
750
General-purpose input
761
General-purpose output
761
IOPORT
762
View document
NXP KL2x Reference guide
Type
Reference guide
Brand
NXP
Size
9.94 MB
Pages
881
Language
English
View document