Semtech Altera Arria 10, a powerful and versatile FPGA, offers a comprehensive suite of features for a wide range of applications. With its advanced 20 nm TriGate+ process technology, it delivers exceptional performance, power efficiency, and integration capabilities. The Arria 10 FPGA boasts a rich fabric of logic elements, DSP blocks, and embedded memory, making it ideal for demanding applications such as video processing, high-speed networking, and software-defined radio. Its cutting-edge transceivers support various protocols and data rates, enabling high-performance connectivity.
Semtech Altera Arria 10, a powerful and versatile FPGA, offers a comprehensive suite of features for a wide range of applications. With its advanced 20 nm TriGate+ process technology, it delivers exceptional performance, power efficiency, and integration capabilities. The Arria 10 FPGA boasts a rich fabric of logic elements, DSP blocks, and embedded memory, making it ideal for demanding applications such as video processing, high-speed networking, and software-defined radio. Its cutting-edge transceivers support various protocols and data rates, enabling high-performance connectivity.
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Revision History
Contents
1. RDK-12GSRD-INTEL00 User Guide.............................................................................................................4
1.1 Hardware ...............................................................................................................................................4
1.1.1 Power..........................................................................................................................................5
1.1.2 Inputs and Outputs................................................................................................................5
1.1.3 Jumpers......................................................................................................................................6
1.1.4 Test Points.................................................................................................................................6
1.1.5 Assembly ...................................................................................................................................7
1.2 Integrating with Intel’s Loopback Reference Design ............................................................7
1.2.1 Device Initialization and GSPI Control............................................................................8
1.2.2 Automatic Fractional Rate Selection...............................................................................9
1.2.3 Requirements ..........................................................................................................................9
1.3 Software .............................................................................................................................................. 10
1.3.1 Software Setup Instructions ............................................................................................ 10
2. RDK-12GSRD-INTEL00 Schematics ......................................................................................................... 15
3. RDK-12GSRD-INTEL00 Board Layout ..................................................................................................... 22
4. RDK-12GSRD-INTEL00 Bill of Materials ................................................................................................. 24
Version ECO PCN Date Changes and/or Modifications
2 048965 — October 2019 Changes made to Table 4-1: Bill of Materials.
1 044340 — November 2018
GS12141 and GS12181 referencing updated to GS12241 and
GS12281 respectively. RDK-12GSRD-ALTRA00 updated to
RDK-12GSRD-INTEL00.
0 035268 — February 2017 New Document.
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Overview
Together with the RDK-12GSRD-INTEL00 Evaluation Board, this document serves as a
guide for evaluating the GS12241 and the GS12281. The GS12241 is a Semtech 12G
UHD-SDI Re-timing Adaptive Cable Equalizer. For more information on the GS12241,
please refer to the Product Data Sheet (
PDS-061386). The GS12281 is a Semtech 12G
UHD-SDI Re-timing Cable Driver. For more information on the GS12281, please refer to
the Product Data Sheet (
PDS-061385). This document is partitioned into the following
sections:
• RDK-12GSRD-INTEL00 User Guide
• RDK-12GSRD-INTEL00 Schematics
• RDK-12GSRD-INTEL00 Board Layout
• RDK-12GSRD-INTEL00 Bill of Materials
Figure A below shows a block diagram of the features and the functions of the
RDK-12GSRD-INTEL00.
The board includes one 12G SDI input connector, one GS12241 equalizer, a clock
output, a GS12281 multi-rate cable driver, one 12G SDI output connector, a 27MHz
crystal and a status indication LED.
The RDK-12GSRD-INTEL00 also includes an external GSPI dongle to control the GS12241
and the GS12281 through the GSPI ports on the devices.
Figure A: Block Diagram
FMC Connector
12G-SDI EQ
GS12241
12G-SDI CD
GS12281
LMH1981
Sync stripper
LMH1983
Line lock clock
LMK03328
Lower jitter PLL
12G-SDI IN
12G-SDI OUT
DPx_M2C
DPx_C2M
GENLOCK IN
SYNC_IN_HVF
SYNC_OUT_HVF
297MHz
27MHz
24.576MHz
AUDIO_CLK
12V
3.3V
VADJ
4 pair serdes out
4 pair serdes in
GSPI_7_GPIO
16_GPIO
12V
3.3V
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1. RDK-12GSRD-INTEL00 User Guide
1.1 Hardware
Figure 1-1 shows the inputs, outputs and power connections for the
RDK-12GSRD-INTEL00 Daughter Card.
Figure 1-1: RDK-12GSRD-INTEL00 Evaluation Board (Top View)
SDI_OUT
(J2)
SDI_IN
(J1)
CLOCK
(J5)
GS12281
GS12241
Jumper
(J4):
1–2 = FPGA Control
2–3 = 297MHz/1.001
NC = 297MHz
External
GSPI
Dongle
Interface
(J9)
1
2
3
LED
(D1)
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Figure 1-2: RDK-12GSRD-INTEL00 Evaluation Board (Bottom View)
1.1.1 Power
The RDK-12GSRD-INTEL00 Daughter Card obtains 3.3V from the Intel evaluation board
via the FMC-FPGA connector (J6) as shown in
Figure 1-2 above.
LED D1 is used to indicate if there is voltage present.
1.1.2 Inputs and Outputs
The RDK-12GSRD-INTEL00 Daughter Card includes GS12241 and GS12281 SRD devices.
The 75Ω BNC connector J1 is an SDI input and the 75Ω BNC connector J2 is an SDI
output.
The GS12241 automatically adjusts its gain to equalize and restore signals received over
different lengths of coaxial cable having loss characteristics similar to Belden 1694A, and
over multiple standards operating from 1Mb/s to 11.88Gb/s.
The GS12281 has programmable pre-emphasis to improve the transmitted eye quality
over different cable lengths.
The GS12241 also has programmable pre-emphasis to improve the output eye quality.
FMC–FPGA
Connector
(J6)
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1.1.3 Jumpers
By default, jumper J4 is installed to allow the FPGA to automatically control the frame
rate. See
Table 1-1 below for more details.
1.1.4 Test Points
Figure 1-3: Test Points
Table 1-1: Jumper (J4)
Jumper Position Frame Rate
1 2 FPGA controlled
2 3 297MHz / 1.001
No Connect (NC) 297MHz
Table 1-2: Test Points
Test Point Function
TP1 Programmable GPIO0 for the GS12241
TP3 Programmable GPIO2 for the GS12241
TP4 Programmable GPIO3 for the GS12241
TP9 Programmable GPIO0 for the GS12281
TP10 Programmable GPIO1 for the GS12281
TP11 Programmable GPIO2 for the GS12281
TP12 Programmable GPIO3 for the GS12281
81
41
1
2
3
TP1, TP3, TP4
TP9, TP10, TP11, TP12
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1.1.5 Assembly
Figure 1-4: Assembly
1.2 Integrating with Intel’s Loopback Reference Design
To achieve full functionality of the RDK-12GSRD-INTEL00 Daughter Card some special
provisions are required in Arria 10 FPGA implementation. The sections below outline
these requirements. This content assumes that the FPGA design uses Intel's SDI II
MegaCore receiver and transmitter IP, and was tested with Intel's "Multi Rate (up to 12G)
SDI II Reference Design for Arria 10 Devices".
Figure 2-5 shows details of all signals on the FMC connector that interfaces with the
RDK-12GSRD-INTEL00 Daughter Card to the Arria 10 GX development board. Intel's SDI
II Reference Design shows example usage when the Daughter Card is plugged into the
FMC-B socket on the main board.
Applink Dongle
Semtech Daughter Card
Arria 10 Evaluation Board
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1.2.1 Device Initialization and GSPI Control
As described in an Application Note (PDS-061485), the GS12241 and GS12281 devices
on the RDK-12GSRD-INTEL00 Daughter Card may require configuration data to be
written on power-up. The logic described in the Application Note performs all of the
necessary initialization when correctly interfaced to the Daughter Card. This section
assumes the use of the provided gspi_init_top_wrap.v sample implementation to
achieve this. This module should be connected as follows to operate correctly:
gspi_init_top_wrap gspi_init_top_wrap_inst (
// reset and clocking
.clk_100m (clk_fpga_b2_p ), // 100MHz clock
.clk_100m_reset_n (cpu_resetn ), // synchronous reset
// start, busy, done handshake
.gspi_init_start (1'b1 ),
.gspi_init_busy ( ),
.gspi_init_done (gspi_init_done ),
// GSPI interface
.gspi_sclk (gspi_sclk ),
.gspi_scs_n (gspi_scs_n ),
.gspi_sdout (gspi_sdout )
);
assign gspi_fpga_en_n = gspi_init_done ? 1'b1 : 1'b0;
assign gspi_header_en_n = gspi_init_done ? 1'b0 : 1'b1;
The GSPI control signals map to the FMC-B connector as follows (naming is based on
Arria 10 GX development board schematic signal names):
// GSPI interface on FMC Port B
assign fmcb_la_tx_n10 = gspi_sdout;
// daughtercard's sdin
assign fmcb_la_tx_p10 = gspi_sclk;
// daughtercard needs to tie the two CSs together post level
// shifter, so must drive with same value to prevent contention
assign fmcb_la_tx_p16 = gspi_scs_n[0]; // gspi_scs_n_gs12241;
assign fmcb_la_tx_n15 = gspi_scs_n[0]; // gspi_scs_n_gs12281;
assign fmcb_la_rx_p9 = gspi_header_en_n;
assign fmcb_la_rx_n9 = gspi_fpga_en_n;
Note: The gspi_fpga_en_n and gspi_hea der_en_n signals must be driven with opposite
values to prevent signal contention on the Daughter Card. When driven as shown
above, an External GSPI Dongle can still be connected to the J9 header on the Daughter
Card, and the GSPI Initialization IP will take control of the GSPI bus for the required
initialization.
Also, as shown above, the chip select signals going to the GS12241 and GS12281 devices
must be driven with the same value to prevent contention on the Daughter Card.
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1.2.2 Automatic Fractional Rate Selection
Whole frame rates, also known as PAL frame rates, can be any of: 24, 25, 30, 50, 60 frames
per second. Above SD-SDI serial rates, they are transmitted over SDI bit rates that are a
multiple of 1.485Gb/s, and Intel's SDI II MegaCore transmitter requires a Tx reference
clock of 297MHz.
Fractional frame rates, also known as NTSC frame rates, are typically 23.98, 29.97, or
59.94 video frames per second, or (whole rate)/1.001. Above SD-SDI serial rates, they are
transmitted over SDI bit rates that are a multiple of 1.485Gbps/1.001, and Intel's SDI II
MegaCore transmitter requires a Tx reference clock of 297MHz/1.001.
RDK-12GSRD-INTEL00 Daughter Card can generate both 297MHz and 297MHz/1.001 Tx
reference clock for the FPGA's use (fed to the Arria 10 GX development board
differentially over pins D4 and D5 of the FMC connector). The rate can be manually
selected using jumper J4 (see
Figure 1-1 and Table 1-1). For any change in this setting to
take effect, the LMK03328 PLL must be power-cycled by toggling its PDN pin.
Automatic fractional rate selection can be achieved with FPGA logic as follows:
• Set J4 jumper in 1-2 position to enable FPGA control. This makes the control
available on pin G27 of FMC connector, which is connected to the FPGA on main
board
• In the FPGA design, connect this pin to the inverse of sdi_rx_clkout_is_ntsc_paln
output of the SDI II MegaCore receiver, as an open-collector output. Corresponding
Verilog code could look like this:
assign lmk03328_ntsc_clk_n = ~sdi_rx_clkout_is_ntsc_paln;
assign fmcb_la_rx_p10 = lmk03328_ntsc_clk_n ? 1'bz : 1'b0;
• The LMK03328 PLL's power-down (PDN) input is connected to pin H34 of FMC
connector. In the FPGA design, wait for any changes on sdi_rx_clkout_is_ntsc_paln
and sdi_rx_frame_locked outputs from the SDI II MegaCore receiver. When
observed, toggle the PDN signal LOW than HIGH, also driving the output as an
open-collector. Corresponding Verilog code could look like this:
reset_on_toggle #(
.RESET_DEFAULT_STATE (1'b0)
) lmk_autorst_inst (
.clk (clk_fpga_b2_p ),
.clk_reset_n (cpu_resetn ),
.observed (sdi_rx_clkout_is_ntsc_paln_forced^rx_frame_locked),
.out_reset_n (lmk03328_powerdown_n )
);
assign fmcb_la_tx_p15 = lmk03328_powerdown_n ? 1'bz : 1'b0;
1.2.3 Requirements
For this automatic fractional rate selection functionality to work, the following
configuration is required:
• SDI II MegaCore's receiver's rx_core_refclk and rx_cdr_refclk must be connected to
148.5MHz clock. In the Reference Design this is achieved by setting SDI REFCLK
frequency on the Arria 10 GX development board to 148.5MHz (SW6.3 must be
OFF)
• SDI II MegaCore's receiver's sdi_rx_coreclk_is_ntsc_paln input must be set to '0'
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1.3 Software
This guide provides instructions for using the software associated with the
RDK-12GSRD-INTEL00 Reference Design Board.
1.3.1 Software Setup Instructions
Upon execution of the setup file, the following window will appear as shown in
Figure 1-5. To install the software you must click next and follow the steps listed in the
setup window.
Figure 1-5: RDK-12GSRD-INTEL00 Software Installation Window
After accepting the EULA, the following dialogue box will be displayed, which provides
some additional information on the installation.
Figure 1-6: Important Installation Information
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If the Microsoft Visual C++ 2010 Redistributable is not already installed, you will be
prompted to accept the license agreement, as shown in
Figure 1-7 below.
Figure 1-7: Microsoft EULA Installation
Once installation is complete, the following dialogue will appear. There is an option to
launch the application immediately following installation.
Figure 1-8: Software Requirements
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2. RDK-12GSRD-INTEL00 Schematics
Figure 2-1: SDI In
Install R49 & R3 to
disable rfclk_in
CHANGED R33 TO 0R
UPDATE PORT DIRECTIONS
CHANGED R32 TO 0R
Default to have his GSPI path enabled
Added FPGA control to the GSPI path by
Replaced resistor R57 to 10K
VCC_1.8V
VCC_1.8V
V_ADJ
V_ADJ
VCC_1.8V
VCC_1.8V
VCC_1.8V
V_ADJ
VCC_1.8V
V_ADJ
GSPI_SDIN
GSPI_SCLK
GSPI_CS_GS12241
FMC_GSPI_SDIN
FMC_GSPI_SCLK
FMC_GSPI_CS_GS12241
FMC_GSPI_CS_GS122 81
FMC_GS12241_GPIO0
FMC_GS12241_GPIO2
FMC_GS12241_GPIO3
GSPI_SDOUT
REF_CLK_OUT
GSPI_OUT_IN
FMC_GS12241_OUT+
FMC_GS12241_OUT-
FMC_GSPI_SDOUT
GSPI_SCLK
GSPI_SDIN
GSPI_CS_GS12281
GSPI_CS_GS12241
FMC_GSPI_OEn
C7
4.7μF
C6
100nF
R5 22Ω
C5
100nF
TP22
GPIO2
C15
470nF
C14
0.1μF
C1
100nF
U2
TXB0304
VCCA
1
A1
2
A2
3
A3
4
A4
5
GND
6
B4
7
B3
8
B2
9
B1
10
VCCB
11
OE
12
C13
0.1μF
R6 22Ω
C4
100nF
R57
10kΩ
R3
NC/100kΩ
C2
100nF
C16
10μF
R2 30kΩ
R7 22Ω
TP3
GPIO2
U3
74AVC4TD245BQ
VCCA
1
A1
3
A2
4
A3
5
A4
6
GND
8
OE
9
B4
11
B3
12
B2
13
B1
14
VCCB
16
TAB
17
DIR1
2
DIR2
15
DIR3
10
DIR4
7
U1
GS12241
VEE_SDI1
1
SDI
2
SDI
3
VCC_SDI
4
NC3
5
NC1
6
NC2
7
VEE_SDI2
8
NC4
9
CS
10
SDIN
11
SDOUT
12
SCLK
13
VSS1
14
VSS2
15
VDD
16
GPIO0
17
GPIO1
18
VEE_CORE1
19
VCC_CORE1
20
VEEO1
21
DDO1/RCO
22
DDO1/RCO
23
VCCO_1
24
VCCO_0
25
DDO0
26
DDO0
27
VEEO2
28
VCC_CORE2
29
NC5
30
VEE_CORE2
31
REF_CLK
32
GPIO2
33
VCO_FILT
34
VCC_CORE3
35
GPIO3
36
VEE_CORE3
37
VEE_CORE4
38
LF+
39
LF-
40
TAB
TAB
R1
0Ω
R32
0Ω
TP1
GPIO1
X1
ASDMB
EN
1
GND
2
output
3
VDD
4
C3
1μF
C9
4.7μF
TP4
GPIO3
C8 4.7μF
TP5
GSPI_SDIN
R49 NC/100kΩ
R48 10kΩ
TP6
GSPI_SCLK
TP7
GSPI_CS_GS12241
J1
Cambridge C-SX-141 edge
1
3
2
R4 22Ω
C10
10μF
C11 4.7μF
R33
0Ω
C12
100nF
TP8
GSPI_CS_GS12281
TP2
GSPI_SDOUT
C18
0.1μF
27MHz_CLK_IN
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Figure 2-2: SDI Out
Default to have his GSPI path enabled
Added FPGA control to the GSPI path by
Replaced resistor R59 to 10K
VCC_1.8V
V_ADJ
VCC_1.8V
VCC_1.8V
VCC_2.5V
3.3VVCC_1.8V
3.3V_A
VCC_1.8V
VCC_2.5V
GSPI_OUT_IN
GSPI_SCLK
GSPI_CS_GS12281
FMC_GS12281_IN+
FMC_GS12281_IN-
REF_CLK_OUT
I2C_SCL
I2C_SDA
GSPI_SDOUT
FMC_GS12281_GPIO2
FMC_GS12281_GPIO0
FMC_GS12281_GPIO3
FMC_GS12281_GPIO1
GSPI_SDIN
GSPI_SCLK
GSPI_CS_GS12281
GSPI_CS_GS12241
GSPI_SDOUT
GSPI_OEn
C20
10μF
TP10
GPIO5
C29 4.7μF
R43
0Ω
C32
0.1μF
C33
470nF
C21
1μF
TP11
GPIO6
R41
0Ω
R44
0Ω
C30 100nF
C22
100nF
TP12
GPIO7
C34
10μF
C109 0.1μF
R54 0Ω
TP13
GPIO0
C26 4.7μF
U17
74AVC4TD245BQ
VCCA
1
A1
3
A2
4
A3
5
A4
6
GND
8
OE
9
B4
11
B3
12
B2
13
B1
14
VCCB
16
TAB
17
DIR1
2
DIR2
15
DIR3
10
DIR4
7
R36
0Ω
J9
FCI98414G0616ULF
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
R38 0Ω
R42
DNP
TP21
GPIO1
C23
100nF
C107
0.1μF
C27 4.7μF
R39 0Ω
R34 5Ω
R55 0Ω
R9 30kΩ
R40
10kΩ
C24
100nF
C108
0.1μF
R8
75Ω
R59 10kΩ
U4
GS12281
VEE_DDI1
1
NC1
2
NC2
3
VCC_DDI
4
TERM
5
DDI
6
DDI
7
VEE_DDI2
8
NC3
9
CS
10
SDIN
11
SDOUT
12
SCLK
13
VSS1
14
VSS2
15
VDD
16
GPIO0
17
GPIO1
18
VEE_CORE1
19
VCCO1P8_1
20
VEEO2
21
SDO1
22
SDO1
23
VCCO_1
24
VCCO_0
25
SDO0
26
SDO0
27
VEEO1
28
VCCO1P8_0
29
NC4
30
VEE_CORE2
31
REF_CLK
32
GPIO2
33
VCO_FILT
34
VCC_CORE
35
GPIO3
36
VEE_CORE3
37
VEE_CORE4
38
LF+
39
LF-
40
TAB
TAB
C19
100nF
U5
TXB0304
VCCA
1
A1
2
A2
3
A3
4
A4
5
GND
6
B4
7
B3
8
B2
9
B1
10
VCCB
11
OE
12
J2
Cambridge C-SX-141 edge
1
3
2
C25
100nF
R35 0Ω
TP15GPIO0
R56 0Ω
C28 4.7μF
C31
0.1μF
TP9
GPIO4
R37
DNP
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Figure 2-3: Clock Circuit, Genlock
3.3V_A
3.3V_PLL2
3.3V_PLL1
3.3V_A
3.3V_OUT1
3.3V_A
3.3V_A
3.3V_A
3.3V_PLL2
3.3V_A
3.3V_PLL1
3.3V_A
3.3V_OUT1
3.3V_A
3.3V_A
3.3V_A
3.3V_A
3.3V_A
FPGA_HSYNCn
FPGA_VSYNCn
FPGA_FLDn
LMH1983_INIT
I2C_SCL
I2C_SDA
FMC_AUDIO_CLK+
FMC_AUDIO_CLK-
LMH1983_NO_REF
LMH1983_NO_ALIGN
LMH1983_NO_LOCK
LMH1981_FLD2n
LMH1981_HSYNCn
LMH1981_VSYNCn
LMH1981_VIDEO_FMT
LMK03328_PDN
I2C_SDA
I2C_SCL
27MHz
CLK_297MHz+
CLK_297MHz-
CLK_RATE_SEL
L1
BLM15AG221SN1D
C80
0.1μF
C1010.1μF
C77
0.1μF
J4
CON3
1
2
3
C430.1μF
C51 33nF
U6
LMH1983
VDD1
1
VDD2
2
HIN
3
VIN
4
FIN
5
INIT
6
ADDR
7
SDA
8
SCL
9
VDD3
10
NO_LOCK
11
NO_ALIGN
12
NO_REF
13
CLKOUT4-
14
CLKOUT4+
15
VDD6
16
FOUT4(OSCin)
17
GND1
18
VDD4
19
VDD5
20
GND2
21
FOUT3
22
CLKOUT3+
23
CLKOUT3-
24
CBYP3
25
CBYP4
26
CBYP2
27
CLKOUT2+
28
CLKOUT2-
29
FOUT2
30
VDD7
31
VDD8
32
XOin-
33
XOin+
34
CLKOUT1-
35
CLKOUT1+
36
FOUT1
37
VDD9
38
GND3
39
VC_LPF
40
DAP
41
C56
0.1μF
C38
0.1uF
C60
1μF
L3
BLM15AG221SN1D
R11
3kΩ
U8
LMP7711MK
OUTPUT
1
V-
2
+IN
3
-IN
4
EN
5
V+
6
C440.1μF
C41 0.1μF
C52 33nF
C1020.1μF
R15
10kΩ
C57
1μF
C75
10μF
C53
47μF
C54
0.1μF
C50 10μF
C74
0.1μF
C36
10uF
R10 3kΩ
C68
0.1μF
C76
0.1μF
C61
0.1μF
C72
10μF
C70
1μF
C64
0.1μF
C45 0.1μF
C980.1μF
X2
357LB3C027M
1
1
EOH
2
GND
3
OUTPUT
4
NC
5
VCC
6
J5
Cambridge C-SX-141 edge
1
3
2
C400.1μF
C67
0.1μF
C55
1μF
C73
0.1μF
C49 10μF
C46 0.1μF
L2
BLM15AG221SN1D
C58
0.1μF
C78
10μF
U9
LMH1981
REXT
1
GND1
2
VCC1
3
VIN
4
GND2
5
VCC2
6
HSOUT
7
VSOUT
8
VFOUT
9
GND3
10
VCC3
11
CSOUT
12
BPOUT
13
OEOUT
14
C990.1μF
R12
17.4kΩ
C390.1μF
R60
10kΩ
R16
75Ω
C63
0.1μF
C65
0.1μF
C66
22μF
R13
10kΩ
U7
LMK03328
STATUS0
1
STATUS1
2
CAP_DIG
3
VDD_DIG
4
VDD_IN
5
PRIREF_P
6
PRIREF_N
7
REFSEL
8
HW_SW_CTRL
9
SECREF_P
10
SECREF_N
11
GPIO0
12
PDN
13
OUT0_P
14
OUT0_N
15
OUT1_N
16
OUT1_P
17
VDDO_01
18
VDDO_23
19
OUT2_P
20
OUT2_N
21
OUT3_N
22
OUT3_P
23
GPIO1
24
SDA
25
SCL
26
VDD_PLL2
27
CAP_PLL2
28
LF2
29
GPIO2
30
GPIO3
31
GPIO4
32
GPIO5
33
LF1
34
CAP_PLL1
35
VDD_PLL1
36
VDDO_4
37
OUT4_N
38
OUT4_P
39
VDDO_5
40
OUT5_N
41
OUT5_P
42
VDDO_6
43
OUT6_N
44
OUT6_P
45
VDDO_7
46
OUT7_N
47
OUT7_P
48
PAD
49
C59
1μF
C71
0.1μF
C1000.1μF
C79
0.1μF
C4222μF
C37
0.1uF
C48 10μF
C47 0.1μF
C62
22μF
R14 10kΩ
C69
0.1μF
RDK-12GSRD-INTEL00
Evaluation Board User Guide Rev.2
PDS-061487 October 2019
18 of 26
Semtech
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Figure 2-4: Level Translators
I
2
C Level Shift
V_ADJ to 3.3V Translation
3.3V_A
V_ADJ
V_ADJ
3.3V_A
V_ADJ
3.3V_A
V_ADJ
3.3V_A
V_ADJ
3.3V_A
3.3V_A
FMC_FPGA_HSYNCn
FMC_FPGA_VSYNCn
FMC_FPGA_FLDn
FMC_LMH1983_INIT
FPGA_HSYNCn
FPGA_VSYNCn
FPGA_FLDn
LMH1983_INIT
FMC_I2C_SDA
FMC_I2C_SCL
FMC_LMH1981_HSYNCn
FMC_LMH1981_VSYNCn
FMC_LMH1981_VIDEO_FMT
FMC_LMH1981_FLD2n
I2C_SCL
I2C_SDA
LMH1981_HSYNCn
LMH1981_VSYNCn
LMH1981_VIDEO_FMT
LMH1981_FLDn
LMH1983_NO_REF
LMH1983_NO_ALIGN
LMH1983_NO_LOCK
FMC_LMH1983_NO_REF
FMC_LMH1983_NO_ALIGN
FMC_LMH1983_NO_LOCK
FPGA_STATUS1
FMC_FPGA_STATUS1
C81
0.1μF
R17 22Ω
R24
4.75kΩ
C84
0.1μF
R21
4.75kΩ
U14
PCA9306DCUR
GND
1
VREF1
2
SCL1
3
SDA1
4
SDA2
5
SCL2
6
VREF2
7
EN
8
U10
74AVC4TD245BQ
VCCA
1
A1
3
A2
4
A3
5
A4
6
GND
8
OE
9
B4
11
B3
12
B2
13
B1
14
VCCB
16
TAB
17
DIR1
2
DIR2
15
DIR3
10
DIR4
7
J3
CON3
1
1
2
2
3
3
vss1
4
vss2
5
U13
74AVC4TD245BQ
VCCA
1
A1
3
A2
4
A3
5
A4
6
GND
8
OE
9
B4
11
B3
12
B2
13
B1
14
VCCB
16
TAB
17
DIR1
2
DIR2
15
DIR3
10
DIR4
7
R18 22Ω
R22
4.75kΩ
C82
0.1μF
TP18
HSYNC
R19 22Ω
R47
10kΩ
R45
10kΩ
TP19
VSYNC
R23
4.75kΩ
R20 22Ω
U11
74AVC4TD245BQ
VCCA
1
A1
3
A2
4
A3
5
A4
6
GND
8
OE
9
B4
11
B3
12
B2
13
B1
14
VCCB
16
TAB
17
DIR1
2
DIR2
15
DIR3
10
DIR4
7
C86
0.1μF
C85
0.1μF
TP20
FLD2n
R46
10kΩ
3.3V to V_ADJ Translation
RDK-12GSRD-INTEL00
Evaluation Board User Guide Rev.2
PDS-061487 October 2019
19 of 26
Semtech
Proprietary & Confidential
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Figure 2-5: FMC Connector
Key features of the FMC specication include:
• Up to 20 high-speed dierential pairs supporting 10Gb/s signaling.
• 4 dierential clocks supporting 2GHz signaling.
• 80 dierential I/O or 160 single ended general purpose I/O.
• IPMI programming and card information access.
• Support for user selectable I/O voltage standards.
3.3V
12V
V_ADJ
V_ADJ
V_ADJ
V_ADJ
3.3V
FMC_AUDIO_CLK+
FMC_AUDIO_CLK-
CLK_297MHz-
CLK_297MHz+
FMC_I2C_SDA
FMC_I2C_SCL
FPGA_STATUS1
LMK03328_PDN
FMC_LMH1981_HSYNCn
FMC_LMH1981_VSYNCn
FMC_LMH1981_VIDEO_FMT
FMC_LMH1981_FLD2n
FMC_FPGA_HSYNCn
FMC_FPGA_VSYNCn
FMC_FPGA_FLDn
FMC_LMH1983_INIT
FMC_LMH1983_NO_REF
FMC_LMH1983_NO_ALIGN
FMC_LMH1983_NO_LOCK
FMC_GSPI_SDOUT
FMC_GS12241_GPIO0
FMC_GS12241_GPIO2
FMC_GS12241_GPIO3
FMC_GSPI_SDIN
FMC_GSPI_SCLK
FMC_GSPI_CS_GS12241
FMC_GSPI_CS_GS12281
FMC_GS12281_GPIO0
FMC_GS12281_GPIO2
FMC_GS12281_GPIO1
FMC_GS12281_GPIO3
FMC_120_GSPI_SDIN
FMC_120_GSPI_SDOUT
FMC_120_GPIO13
FMC_120_GPIO14
FMC_120_GSPI_CLK
FMC_120_GSPI_CS1
FMC_120_GPIO9
FMC_120_GPIO10
FMC_120_GSPI_CS2
FMC_120_GSPI_CS3
FMC_120_GSPI_CS4
FMC_120_GPIO5
FMC_120_GPIO6
FMC_120_GPIO1
FMC_120_GPIO2
FMC_120_GPIO3
FMC_120_GPIO4
FMC_120_GPIO7
FMC_120_GPIO8
FMC_120_GPIO11
FMC_120_GPIO12
FMC_120_GPIO15
FMC_120_GPIO16
FMC_12G_IN4-
FMC_12G_IN4+
FMC_12G_IN3-
FMC_12G_IN3+
FMC_12G_IN2-
FMC_12G_IN2+
FMC_12G_OUT2-
FMC_12G_OUT2+
FMC_12G_OUT3-
FMC_12G_OUT3+
FMC_12G_OUT4-
FMC_12G_OUT4+
FMC_GS12241_OUT+
FMC_GS12241_OUT-
FMC_GSPI_OEn
GSPI_OEn
FMC_12G_IN1-
FMC_12G_IN1+
FMC_GS12281_IN+
FMC_GS12281_IN-
FMC_12G_OUT1-
FMC_12G_OUT1+
CLK_RATE_SEL
TP25
GPIO5
J6B
asp-134488-01_0
GND41
C1
DP0_C2M_P
C2
DP0_C2M_N
C3
GND42
C4
GND43
C5
DP0_M2C_P
C6
DP0_M2C_N
C7
GND44
C8
GND45
C9
LA06_P
C10
LA06_N
C11
GND46
C12
GND47
C13
LA10_P
C14
LA10_N
C15
GND48
C16
GND49
C17
LA14_P
C18
LA14_N
C19
GND50
C20
GND51
C21
LA_18_P_CC
C22
LA_18_N_CC
C23
GND52
C24
GND53
C25
LA27_P
C26
LA27_N
C27
GND54
C28
GND55
C29
SCL
C30
SDA
C31
GND56
C32
GND57
C33
GA0
C34
12P0V1
C35
GND58
C36
12P0V2
C37
GND59
C38
3P3V1
C39
GND60
C40
PG_C2M
D1
GND61
D2
GND62
D3
GBTCLK0_M2C_P
D4
GBTCLK0_M2C_N
D5
GND63
D6
GND64
D7
LA01_P_CC
D8
LA01_N_CC
D9
GND65
D10
LA05_P
D11
LA05_N
D12
GND66
D13
LA09_P
D14
LA09_N
D15
GND67
D16
LA13_P
D17
LA13_N
D18
GND68
D19
LA17_P_CC
D20
LA17_N_CC
D21
GND69
D22
LA23_P
D23
LA23_N
D24
GND70
D25
LA26_P
D26
LA26_N
D27
GND71
D28
TCK
D29
TDI
D30
TDO
D31
3P3VAUX
D32
TMS
D33
TRST_L
D34
GA1
D35
3P3V2
D36
GND72
D37
3P3V3
D38
GND73
D39
3P3V4
D40
J6D
asp-134488-01_0
GND104
G1
CLK1_M2C_P
G2
CLK1_M2C_N
G3
GND105
G4
GND106
G5
LA00_P_CC
G6
LA00_N_CC
G7
GND107
G8
LA03_P
G9
LA03_N
G10
GND108
G11
LA08_P
G12
LA08_N
G13
GND109
G14
LA12_P
G15
LA12_N
G16
GND110
G17
LA16_P
G18
LA16_N
G19
GND111
G20
LA20_P
G21
LA20_N
G22
GND112
G23
LA22_P
G24
LA22_N
G25
GND113
G26
LA25_P
G27
LA25_N
G28
GND114
G29
LA29_P
G30
LA29_N
G31
GND115
G32
LA31_P
G33
LA31_N
G34
GND116
G35
LA33_P
G36
LA33_N
G37
GND117
G38
VADJ3
G39
GND118
G40
VREF_A_M2C
H1
PRSNT_M2C_L
H2
GND119
H3
CLK0_M2C_P
H4
CLK0_M2C_N
H5
GND120
H6
LA02_P
H7
LA02_N
H8
GND121
H9
LA04_P
H10
LA04_N
H11
GND122
H12
LA07_P
H13
LA07_N
H14
GND123
H15
LA11_P
H16
LA11_N
H17
GND124
H18
LA15_P
H19
LA15_N
H20
GND125
H21
LA19_P
H22
LA19_N
H23
GND126
H24
LA21_P
H25
LA21_N
H26
GND127
H27
LA24_P
H28
LA24_N
H29
GND128
H30
LA28_P
H31
LA28_N
H32
GND129
H33
LA30_P
H34
LA30_N
H35
GND130
H36
LA32_P
H37
LA32_N
H38
GND131
H39
VADJ4
H40
J6C
asp-134488-01_0
GND74
E1
HA01_P_CC
E2
HA01_N_CC
E3
GND75
E4
GND76
E5
HA05_P
E6
HA05_N
E7
GND77
E8
HA09_P
E9
HA09_N
E10
GND78
E11
HA13_P
E12
HA13_N
E13
GND79
E14
HA16_P
E15
HA16_N
E16
GND80
E17
HA20_P
E18
HA20_N
E19
GND81
E20
HB03_P
E21
HB03_N
E22
GND82
E23
HB05_P
E24
HB05_N
E25
GND83
E26
HB09_P
E27
HB09_N
E28
GND84
E29
HB13_P
E30
HB13_N
E31
GND85
E32
HB19_P
E33
HB19_N
E34
GND86
E35
HB21_P
E36
HB21_N
E37
GND87
E38
VADJ1
E39
GND88
E40
PG_M2C
F1
GND89
F2
GND90
F3
HA00_P_CC
F4
HA00_N_CC
F5
GND91
F6
HA04_P
F7
HA04_N
F8
GND92
F9
HA08_P
F10
HA08_N
F11
GND93
F12
HA12_P
F13
HA12_N
F14
GND94
F15
HA15_P
F16
HA15_N
F17
GND95
F18
HA19_P
F19
HA19_N
F20
GND96
F21
HB02_P
F22
HB02_N
F23
GND97
F24
HB04_P
F25
HB04_N
F26
GND98
F27
HB08_P
F28
HB08_N
F29
GND99
F30
HB12_P
F31
HB12_N
F32
GND100
F33
HB16_P
F34
HB16_N
F35
GND101
F36
HB20_P
F37
HB20_N
F38
GND102
F39
VADJ2
F40
J6A
asp-134488-01_0
GND1
A1
DP1_M2C_P
A2
DP1_M2C_N
A3
GND2
A4
GND3
A5
DP2_M2C_P
A6
DP2_M2C_N
A7
GND4
A8
GND5
A9
DP3_M2C_P
A10
DP3_M2C_N
A11
GND6
A12
GND7
A13
DP4_M2C_P
A14
DP4_M2C_N
A15
GND8
A16
GND9
A17
DP5_M2C_P
A18
DP5_M2C_N
A19
GND10
A20
GND11
A21
DP1_C2M_P
A22
DP1_C2M_N
A23
GND12
A24
GND13
A25
DP2_C2M_P
A26
DP2_C2M_N
A27
GND14
A28
GND15
A29
DP3_C2M_P
A30
DP3_C2M_N
A31
GND16
A32
GND17
A33
DP4_C2M_P
A34
DP4_C2M_N
A35
GND18
A36
GND19
A37
DP5_C2M_P
A38
DP5_C2M_N
A39
GND20
A40
RES1
B1
GND21
B2
GND22
B3
DP9_M2C_P
B4
DP9_M2C_N
B5
GND23
B6
GND24
B7
DP8_M2C_P
B8
DP8_M2C_N
B9
GND25
B10
GND26
B11
DP7_M2C_P
B12
DP7_M2C_N
B13
GND27
B14
GND28
B15
DP6_M2C_P
B16
DP6_M2C_N
B17
GND29
B18
GND30
B19
GBTCLK1_M2C_P
B20
GBTCLK1_M2C_N
B21
GND31
B22
GND32
B23
DP9_C2M_P
B24
DP9_C2M_N
B25
GND33
B26
GND34
B27
DP8_C2M_P
B28
DP8_C2M_N
B29
GND35
B30
GND36
B31
DP7_C2M_P
B32
DP7_C2M_N
B33
GND37
B34
GND38
B35
DP6_C2M_P
B36
DP6_C2M_N
B37
GND39
B38
GND40
B39
RES0
B40
TP23
GPIO3
C103
10μF
TP24
GPIO4
J6E
asp-134488-01_0
GND132
J1
CLK3_M2C_P
J2
CLK3_M2C_N
J3
GND133
J4
GND134
J5
HA03_P
J6
HA03_N
J7
GND135
J8
HA07_P
J9
HA07_N
J10
GND136
J11
HA11_P
J12
HA11_N
J13
GND137
J14
HA14_P
J15
HA14_N
J16
GND138
J17
HA18_P
J18
HA18_N
J19
GND139
J20
HA22_P
J21
HA22_N
J22
GND140
J23
HB01_P
J24
HB01_N
J25
GND141
J26
HB07_P
J27
HB07_N
J28
GND142
J29
HB11_P
J30
HB11_N
J31
GND143
J32
HB15_P
J33
HB15_N
J34
GND144
J35
HB18_P
J36
HB18_N
J37
GND145
J38
VIO_B_M2C_1
J39
GND146
J40
VREF_B_M2C
K1
GND147
K2
GND148
K3
CLK2_M2C_P
K4
CLK2_M2C_N
K5
GND149
K6
HA02_P
K7
HA02_N
K8
GND150
K9
HA06_P
K10
HA06_N
K11
GND151
K12
HA10_P
K13
HA10_N
K14
GND152
K15
HA17_P_CC
K16
HA17_N_CC
K17
GND153
K18
HA21_P
K19
HA21_N
K20
GND154
K21
HA23_P
K22
HA23_N
K23
GND155
K24
HB00_P_CC
K25
HB00_N_CC
K26
GND156
K27
HB06_P_CC
K28
HB06_N_CC
K29
GND157
K30
HB10_P
K31
HB10_N
K32
GND158
K33
HB14_P
K34
HB14_N
K35
GND159
K36
HB17_P_CC
K37
HB17_N_CC
K38
GND160
K39
VIO_B_M2C_2
K40
RDK-12GSRD-INTEL00
Evaluation Board User Guide Rev.2
PDS-061487 October 2019
20 of 26
Semtech
Proprietary & Confidential
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Figure 2-6: Expansion Connector
3.3V
12V
12V
3.3V
12V
3.3V
3.3V
12V
FMC_120_GPIO14
FMC_120_GPIO3
FMC_120_GSPI_SDOUT
FMC_120_GPIO13
FMC_120_GPIO5
FMC_120_GSPI_SDIN
FMC_120_GPIO6
FMC_120_GPIO12
FMC_120_GSPI_CS3
FMC_120_GSPI_CS2
FMC_120_GSPI_CS4
FMC_120_GPIO7
FMC_120_GPIO4
FMC_120_GSPI_CS1
FMC_120_GPIO2
FMC_120_GPIO8
FMC_120_GPIO11
FMC_120_GPIO15
FMC_120_GPIO16
FMC_120_GPIO1
FMC_120_GSPI_CLK
FMC_120_GPIO10
FMC_120_GPIO9
FMC_12G_IN2-
FMC_12G_IN2+
FMC_12G_IN1-
FMC_12G_IN1+
FMC_12G_IN4-
FMC_12G_IN4+
FMC_12G_IN3-
FMC_12G_IN3+
FMC_12G_OUT1-
FMC_12G_OUT1+
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Semtech Altera Arria 10, a powerful and versatile FPGA, offers a comprehensive suite of features for a wide range of applications. With its advanced 20 nm TriGate+ process technology, it delivers exceptional performance, power efficiency, and integration capabilities. The Arria 10 FPGA boasts a rich fabric of logic elements, DSP blocks, and embedded memory, making it ideal for demanding applications such as video processing, high-speed networking, and software-defined radio. Its cutting-edge transceivers support various protocols and data rates, enabling high-performance connectivity.
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