Semtech Altera Arria 10 User guide

Altera Arria 10
Brand
Semtech
Model
Altera Arria 10
Type
User guide

Semtech Altera Arria 10 offers a full-featured evaluation platform for Semtech's GS12141 and GS12181 12G UHD-SDI devices. It enables signal re-timing, equalization, and cable driving for professional broadcast applications. With its comprehensive set of features, the board simplifies the integration of these devices into complex video systems, making it an ideal tool for engineers working with high-speed video and broadcast technologies.

Semtech Altera Arria 10 offers a full-featured evaluation platform for Semtech's GS12141 and GS12181 12G UHD-SDI devices. It enables signal re-timing, equalization, and cable driving for professional broadcast applications. With its comprehensive set of features, the board simplifies the integration of these devices into complex video systems, making it an ideal tool for engineers working with high-speed video and broadcast technologies.

Intel FPGA Arria 10 Reference Design Daughter Card
Evaluation Board User Guide
1 of 26
Semtech
Proprietary & Confidential
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
www.semtech.com
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
2 of 26
Semtech
Proprietary & Confidential
www.semtech.com
Revision History
Contents
1. RDK-12GSRD-ALTRA00 User Guide...........................................................................................................4
1.1 Hardware ...............................................................................................................................................4
1.1.1 Power..........................................................................................................................................5
1.1.2 Inputs and Outputs................................................................................................................5
1.1.3 Jumpers......................................................................................................................................6
1.1.4 Test Points.................................................................................................................................6
1.1.5 Assembly ...................................................................................................................................7
1.2 Integrating with Intel’s Loopback Reference Design ............................................................7
1.2.1 Device Initialization and GSPI Control............................................................................8
1.2.2 Automatic Fractional Rate Selection...............................................................................9
1.2.3 Requirements ..........................................................................................................................9
1.3 Software .............................................................................................................................................. 10
1.3.1 Software Setup Instructions ............................................................................................ 10
2. RDK-12GSRD-ALTRA00 Schematics ....................................................................................................... 15
3. RDK-12GSRD-ALTRA00 Board Layout ................................................................................................... 22
4. RDK-12GSRD-ALTRA00 Bill of Materials................................................................................................ 24
Version ECO PCN Date Changes and/or Modifications
0 035268 — February 2017 New Document.
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
3 of 26
Semtech
Proprietary & Confidential
www.semtech.com
Overview
Together with the RDK-12GSRD-ALTRA00 Evaluation Board, this document serves as a
guide for evaluating the GS12141 and the GS12181. The GS12141 is a Semtech 12G
UHD-SDI Re-timing Adaptive Cable Equalizer. For more information on the GS12141,
please refer to the Product Data Sheet (PDS-060553). The GS12181 is a Semtech 12G
UHD-SDI Re-timing Cable Driver. For more information on the GS12181, please refer to
the Product Data Sheet (PDS-060905). This document is partitioned into the following
sections:
• RDK-12GSRD-ALTRA00 User Guide
• RDK-12GSRD-ALTRA00 Schematics
• RDK-12GSRD-ALTRA00 Board Layout
• RDK-12GSRD-ALTRA00 Bill of Materials
Figure A below shows a block diagram of the features and the functions of the
RDK-12GSRD-ALTRA00.
The board includes one 12G SDI input connector, one GS12141 equalizer, a clock
output, a GS12181 multi-rate cable driver, one 12G SDI output connector, a 27MHz
crystal and a status indication LED.
The RDK-12GSRD-ALTRA00 also includes an external GSPI dongle to control the
GS12141 and the GS12181 through the GSPI ports on the devices.
Figure A: Block Diagram
FMC Connector
12G-SDI EQ
GS12141
12G-SDI CD
GS12181
LMH1981
Sync stripper
LMH1983
Line lock clock
LMK03328
Lower jitter PLL
12G-SDI IN
12G-SDI OUT
DPx_M2C
DPx_C2M
GENLOCK IN
SYNC_IN_HVF
SYNC_OUT_HVF
297MHz
27MHz
24.576MHz
AUDIO_CLK
12V
3.3V
VADJ
4 pair serdes out
4 pair serdes in
GSPI_7_GPIO
16_GPIO
12V
3.3V
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
4 of 26
Semtech
Proprietary & Confidential
www.semtech.com
1. RDK-12GSRD-ALTRA00 User Guide
1.1 Hardware
Figure 1-1 shows the inputs, outputs and power connections for the
RDK-12GSRD-ALTRA00 Daughter Card.
Figure 1-1: RDK-12GSRD-ALTRA00 Evaluation Board (Top View)
SDI_OUT
(J2)
SDI_IN
(J1)
CLOCK
(J5)
GS12181
GS12141
Jumper
(J4):
1–2 = FPGA Control
2–3 = 297MHz/1.001
NC = 297MHz
External
GSPI
Dongle
Interface
(J9)
1
2
3
LED
(D1)
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
5 of 26
Semtech
Proprietary & Confidential
www.semtech.com
Figure 1-2: RDK-12GSRD-ALTRA00 Evaluation Board (Bottom View)
1.1.1 Power
The RDK-12GSRD-ALTRA00 Daughter Card obtains 3.3V from the Intel evaluation board
via the FMC-FPGA connector (J6) as shown in
Figure 1-2 above.
LED D1 is used to indicate if there is voltage present.
1.1.2 Inputs and Outputs
The RDK-12GSRD-ALTRA00 Daughter Card includes GS12141 and GS12181 SRD devices.
The 75Ω BNC connector J1 is an SDI input and the 75Ω BNC connector J2 is an SDI
output.
The GS12141 automatically adjusts its gain to equalize and restore signals received over
different lengths of coaxial cable having loss characteristics similar to Belden 1694A, and
over multiple standards operating from 1Mb/s to 11.88Gb/s.
The GS12181 has programmable pre-emphasis to improve the transmitted eye quality
over different cable lengths.
The GS12141 also has programmable pre-emphasis to improve the output eye quality.
FMC–FPGA
Connector
(J6)
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
6 of 26
Semtech
Proprietary & Confidential
www.semtech.com
1.1.3 Jumpers
By default, jumper J4 is installed to allow the FPGA to automatically control the frame
rate. See
Table 1-1 below for more details.
1.1.4 Test Points
Figure 1-3: Test Points
Table 1-1: Jumper (J4)
Jumper Position Frame Rate
1 2 FPGA controlled
2 3 297MHz / 1.001
No Connect (NC) 297MHz
Table 1-2: Test Points
Test Point Function
TP1 Programmable GPIO0 for the GS12141
TP3 Programmable GPIO2 for the GS12141
TP4 Programmable GPIO3 for the GS12141
TP9 Programmable GPIO0 for the GS12181
TP10 Programmable GPIO1 for the GS12181
TP11 Programmable GPIO2 for the GS12181
TP12 Programmable GPIO3 for the GS12181
81
41
1
2
3
TP1, TP3, TP4
TP9, TP10, TP11, TP12
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
7 of 26
Semtech
Proprietary & Confidential
www.semtech.com
1.1.5 Assembly
Figure 1-4: Assembly
1.2 Integrating with Intel’s Loopback Reference Design
To achieve full functionality of the RDK-12GSRD-ALTRA00 Daughter Card some special
provisions are required in Arria 10 FPGA implementation. The sections below outline
these requirements. This content assumes that the FPGA design uses Intel's SDI II
MegaCore receiver and transmitter IP, and was tested with Intel's "Multi Rate (up to 12G)
SDI II Reference Design for Arria 10 Devices".
Figure 2-5 shows details of all signals on the FMC connector that interfaces with the
RDK-12GSRD-ALTRA00 Daughter Card to the Arria 10 GX development board. Intel's SDI
II Reference Design shows example usage when the Daughter Card is plugged into the
FMC-B socket on the main board.
Applink Dongle
Semtech Daughter Card
Altera Evaluation Board
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
8 of 26
Semtech
Proprietary & Confidential
www.semtech.com
1.2.1 Device Initialization and GSPI Control
As described in an Application Note (PDS-061485), the GS12141 and GS12181 devices
on the RDK-12GSRD-ALTRA00 Daughter Card may not have final production settings
and may require configuration data to be written on power-up. The logic described in
the Application Note performs all of the necessary initialization when correctly
interfaced to the Daughter Card. This section assumes the use of the provided
gspi_init_top_wrap.v sample implementation to achieve this. This module should be
connected as follows to operate correctly:
gspi_init_top_wrapgspi_init_top_wrap_inst(
//resetandclocking
.clk_100m(clk_fpga_b2_p),//100MHzclock
.clk_100m_reset_n(cpu_resetn),//synchronousreset
//start,busy,donehandshake
.gspi_init_start(1'b1),
.gspi_init_busy(),
.gspi_init_done(gspi_init_done),
//GSPIinterface
.gspi_sclk(gspi_sclk),
.gspi_scs_n(gspi_scs_n),
.gspi_sdout(gspi_sdout)

);
assigngspi_fpga_en_n=gspi_init_done?1'b1:1'b0;
assigngspi_header_en_n=gspi_init_done?1'b0:1'b1;
The GSPI control signals map to the FMC-B connector as follows (naming is based on
Arria 10 GX development board schematic signal names):
//GSPIinterfaceonFMCPortB
assignfmcb_la_tx_n10=gspi_sdout;
//daughtercard'ssdin
assignfmcb_la_tx_p10=gspi_sclk;
//daughtercardneedstotiethetwoCSstogetherpostlevel
//shifter,somustdrivewithsamevaluetopreventcontention
assignfmcb_la_tx_p16=gspi_scs_n[0];//gspi_scs_n_gs12141;
assignfmcb_la_tx_n15=gspi_scs_n[0];//gspi_scs_n_gs12181;
assignfmcb_la_rx_p9=gspi_header_en_n;
assignfmcb_la_rx_n9=gspi_fpga_en_n;
Note: The gspi_fpga_en_n and gspi_hea der_en_n signals must be driven with opposite
values to prevent signal contention on the Daughter Card. When driven as shown
above, an External GSPI Dongle can still be connected to the J9 header on the Daughter
Card, and the GSPI Initialization IP will take control of the GSPI bus for the required
initialization.
Also, as shown above, the chip select signals going to the GS12141 and GS12181 devices
must be driven with the same value to prevent contention on the Daughter Card.
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
9 of 26
Semtech
Proprietary & Confidential
www.semtech.com
1.2.2 Automatic Fractional Rate Selection
Whole frame rates, also known as PAL frame rates, can be any of: 24, 25, 30, 50, 60 frames
per second. Above SD-SDI serial rates, they are transmitted over SDI bit rates that are a
multiple of 1.485Gb/s, and Intel's SDI II MegaCore transmitter requires a Tx reference
clock of 297MHz.
Fractional frame rates, also known as NTSC frame rates, are typically 23.98, 29.97, or
59.94 video frames per second, or (whole rate)/1.001. Above SD-SDI serial rates, they are
transmitted over SDI bit rates that are a multiple of 1.485Gbps/1.001, and Intel's SDI II
MegaCore transmitter requires a Tx reference clock of 297MHz/1.001.
RDK-12GSRD-ALTRA00 Daughter Card can generate both 297MHz and 297MHz/1.001 Tx
reference clock for the FPGA's use (fed to the Arria 10 GX development board
differentially over pins D4 and D5 of the FMC connector). The rate can be manually
selected using jumper J4 (see
Figure 1-1 and Table 1-1). For any change in this setting to
take effect, the LMK03328 PLL must be power-cycled by toggling its PDN pin.
Automatic fractional rate selection can be achieved with FPGA logic as follows:
• Set J4 jumper in 1-2 position to enable FPGA control. This makes the control
available on pin G27 of FMC connector, which is connected to the FPGA on main
board
• In the FPGA design, connect this pin to the inverse of sdi_rx_clkout_is_ntsc_paln
output of the SDI II MegaCore receiver, as an open-collector output. Corresponding
Verilog code could look like this:
assignlmk03328_ntsc_clk_n=~sdi_rx_clkout_is_ntsc_paln;
assignfmcb_la_rx_p10=lmk03328_ntsc_clk_n?1'bz:1'b0;
• The LMK03328 PLL's power-down (PDN) input is connected to pin H34 of FMC
connector. In the FPGA design, wait for any changes on sdi_rx_clkout_is_ntsc_paln
and sdi_rx_frame_locked outputs from the SDI II MegaCore receiver. When
observed, toggle the PDN signal LOW than HIGH, also driving the output as an
open-collector. Corresponding Verilog code could look like this:
reset_on_toggle#(
.RESET_DEFAULT_STATE(1'b0)
)lmk_autorst_inst(
.clk(clk_fpga_b2_p),
.clk_reset_n(cpu_resetn),
.observed(sdi_rx_clkout_is_ntsc_paln_forced^rx_frame_locked),
.out_reset_n(lmk03328_powerdown_n)
);
assignfmcb_la_tx_p15=lmk03328_powerdown_n?1'bz:1'b0;
1.2.3 Requirements
For this automatic fractional rate selection functionality to work, the following
configuration is required:
• SDI II MegaCore's receiver's rx_core_refclk and rx_cdr_refclk must be connected to
148.5MHz clock. In the Reference Design this is achieved by setting SDI REFCLK
frequency on the Arria 10 GX development board to 148.5MHz (SW6.3 must be
OFF)
• SDI II MegaCore's receiver's sdi_rx_coreclk_is_ntsc_paln input must be set to '0'
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
10 of 26
Semtech
Proprietary & Confidential
www.semtech.com
1.3 Software
This guide provides instructions for using the software associated with the
RDK-12GSRD-ALTRA00 Reference Design Board.
1.3.1 Software Setup Instructions
Upon execution of the setup file, the following window will appear as shown in
Figure 1-5. To install the software you must click next and follow the steps listed in the
setup window.
Figure 1-5: RDK-12GSRD-ALTRA00 Software Installation Window
After accepting the EULA, the following dialogue box will be displayed, which provides
some additional information on the installation.
Figure 1-6: Important Installation Information
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
11 of 26
Semtech
Proprietary & Confidential
www.semtech.com
If the Microsoft Visual C++ 2010 Redistributable is not already installed, you will be
prompted to accept the license agreement, as shown in
Figure 1-7 below.
Figure 1-7: Microsoft EULA Installation
Once installation is complete, the following dialogue will appear. There is an option to
launch the application immediately following installation.
Figure 1-8: Software Requirements
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
12 of 26
Semtech
Proprietary & Confidential
www.semtech.com
Figure 1-9: Select Destination Folder
Figure 1-10: Select Start Menu Folder
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
13 of 26
Semtech
Proprietary & Confidential
www.semtech.com
Figure 1-11: Select Additional Tasks
Figure 1-12: Ready To Install
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
14 of 26
Semtech
Proprietary & Confidential
www.semtech.com
Figure 1-13: Installation Complete
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
15 of 26
Semtech
Proprietary & Confidential
www.semtech.com
2. RDK-12GSRD-ALTRA00 Schematics
Figure 2-1: SDI In
Install R49 & R3 to
disable rfclk_in
CHANGED R33 TO 0R
UPDATE PORT DIRECTIONS
CHANGED R32 TO 0R
Default to have his GSPI path enabled
Added FPGA control to the GSPI path by
Replaced resistor R57 to 10K
VCC_1.8V
VCC_1.8V
V_ADJ
V_ADJ
VCC_1.8V
VCC_1.8V
VCC_1.8V
V_ADJ
VCC_1.8V
V_ADJ
GSPI_SDIN
GSPI_SCLK
GSPI_CS_GS12141
FMC_GSPI_SDIN
FMC_GSPI_SCLK
FMC_GSPI_CS_GS12141
FMC_GSPI_CS_GS12181
FMC_GS12141_GPIO0
FMC_GS12141_GPIO2
FMC_GS12141_GPIO3
GSPI_SDOUT
REF_CLK_OUT
GSPI_OUT_IN
FMC_GS12141_OUT+
FMC_GS12141_OUT-
FMC_GSPI_SDOUT
GSPI_SCLK
GSPI_SDIN
GSPI_CS_GS12181
GSPI_CS_GS12141
FMC_GSPI_OEn
C7
4.7μF
C6
10nF
R5 22Ω
C5
10nF
TP22
GPIO2
C15
470nF
C14
0.1μF
C1
10nF
U2
TXB0304
VCCA
1
A1
2
A2
3
A3
4
A4
5
GND
6
B4
7
B3
8
B2
9
B1
10
VCCB
11
OE
12
C13
0.1μF
R6 22Ω
C4
10nF
R57
10kΩ
R3
NC/100kΩ
C2
10nF
C16
1μF
R2 30kΩ
R7 22Ω
TP3
GPIO2
U3
74AVC4TD245BQ
VCCA
1
A1
3
A2
4
A3
5
A4
6
GND
8
OE
9
B4
11
B3
12
B2
13
B1
14
VCCB
16
TAB
17
DIR1
2
DIR2
15
DIR3
10
DIR4
7
U1
GS12141
VEE_SDI1
1
SDI
2
SDI
3
VCC_SDI
4
NC3
5
NC1
6
NC2
7
VEE_SDI2
8
NC4
9
CS
10
SDIN
11
SDOUT
12
SCLK
13
VSS1
14
VSS2
15
VDD
16
GPIO0
17
GPIO1
18
VEE_CORE1
19
VCC_CORE1
20
VEEO1
21
DDO1/RCO
22
DDO1/RCO
23
VCCO_1
24
VCCO_0
25
DDO0
26
DDO0
27
VEEO2
28
VCC_CORE2
29
NC5
30
VEE_CORE2
31
REF_CLK
32
GPIO2
33
VCO_FILT
34
VCC_CORE3
35
GPIO3
36
VEE_CORE3
37
VEE_CORE4
38
LF+
39
LF-
40
TAB
TAB
R1
0Ω
R32
0Ω
TP1
GPIO1
X1
ASDMB
EN
1
GND
2
output
3
VDD
4
C3
10nF
C9
4.7μF
TP4
GPIO3
C8 4.7μF
TP5
GSPI_SDIN
R49 NC/100kΩ
R48 10kΩ
TP6
GSPI_SCLK
TP7
GSPI_CS_GS12141
J1
Cambridge C-SX-141 edge
1
3
2
R4 22Ω
C10
10nF
C11 4.7μF
R33
0Ω
C12
10nF
TP8
GSPI_CS_GS12181
TP2
GSPI_SDOUT
C18
0.1μF
27MHz_CLK_IN
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
16 of 26
Semtech
Proprietary & Confidential
www.semtech.com
Figure 2-2: SDI Out
Default to have his GSPI path enabled
Added FPGA control to the GSPI path by
Replaced resistor R59 to 10K
VCC_1.8V
V_ADJ
VCC_1.8V
VCC_1.8V
VCC_2.5V
3.3VVCC_1.8V
3.3V_A
VCC_1.8V
VCC_2.5V
GSPI_OUT_IN
GSPI_SCLK
GSPI_CS_GS12181
FMC_GS12181_IN+
FMC_GS12181_IN-
REF_CLK_OUT
I2C_SCL
I2C_SDA
GSPI_SDOUT
FMC_GS12181_GPIO2
FMC_GS12181_GPIO0
FMC_GS12181_GPIO3
FMC_GS12181_GPIO1
GSPI_SDIN
GSPI_SCLK
GSPI_CS_GS12181
GSPI_CS_GS12141
GSPI_SDOUT
GSPI_OEn
C20
10nF
TP10
GPIO5
C29 4.7μF
R43
0Ω
C32
0.1μF
C33
470nF
C21
10nF
TP11
GPIO6
R41
0Ω
R44
0Ω
C30 10nF
C22
10nF
TP12
GPIO7
C34
1μF
C109 0.1μF
R54 0Ω
TP13
GPIO0
C26 4.7μF
U17
74AVC4TD245BQ
VCCA
1
A1
3
A2
4
A3
5
A4
6
GND
8
OE
9
B4
11
B3
12
B2
13
B1
14
VCCB
16
TAB
17
DIR1
2
DIR2
15
DIR3
10
DIR4
7
R36
0Ω
J9
FCI98414G0616ULF
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
R38 0Ω
R42
DNP
TP21
GPIO1
C23
10nF
C107
0.1μF
C27 4.7μF
R39 0Ω
R34 5Ω
R55 0Ω
R9 30kΩ
R40
10kΩ
C24
10nF
C108
0.1μF
R8
75Ω
R59 10kΩ
U4
GS12181
VEE_DDI1
1
NC1
2
NC2
3
VCC_DDI
4
TERM
5
DDI
6
DDI
7
VEE_DDI2
8
NC3
9
CS
10
SDIN
11
SDOUT
12
SCLK
13
VSS1
14
VSS2
15
VDD
16
GPIO0
17
GPIO1
18
VEE_CORE1
19
VCCO1P8_1
20
VEEO2
21
SDO1
22
SDO1
23
VCCO_1
24
VCCO_0
25
SDO0
26
SDO0
27
VEEO1
28
VCCO1P8_0
29
NC4
30
VEE_CORE2
31
REF_CLK
32
GPIO2
33
VCO_FILT
34
VCC_CORE
35
GPIO3
36
VEE_CORE3
37
VEE_CORE4
38
LF+
39
LF-
40
TAB
TAB
C19
10nF
U5
TXB0304
VCCA
1
A1
2
A2
3
A3
4
A4
5
GND
6
B4
7
B3
8
B2
9
B1
10
VCCB
11
OE
12
J2
Cambridge C-SX-141 edge
1
3
2
C25
10nF
R35 0Ω
TP15GPIO0
R56 0Ω
C28 4.7μF
C31
0.1μF
TP9
GPIO4
R37
DNP
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
17 of 26
Semtech
Proprietary & Confidential
www.semtech.com
Figure 2-3: Clock Circuit, Genlock
3.3V_A
3.3V_PLL2
3.3V_PLL1
3.3V_A
3.3V_OUT1
3.3V_A
3.3V_A
3.3V_A
3.3V_PLL2
3.3V_A
3.3V_PLL1
3.3V_A
3.3V_OUT1
3.3V_A
3.3V_A
3.3V_A
3.3V_A
3.3V_A
FPGA_HSYNCn
FPGA_VSYNCn
FPGA_FLDn
LMH1983_INIT
I2C_SCL
I2C_SDA
FMC_AUDIO_CLK+
FMC_AUDIO_CLK-
LMH1983_NO_REF
LMH1983_NO_ALIGN
LMH1983_NO_LOCK
LMH1981_FLD2n
LMH1981_HSYNCn
LMH1981_VSYNCn
LMH1981_VIDEO_FMT
LMK03328_PDN
I2C_SDA
I2C_SCL
27MHz
CLK_297MHz+
CLK_297MHz-
CLK_RATE_SEL
L1
BLM15AG221SN1D
C80
0.1μF
C1010.1μF
C77
0.1μF
J4
CON3
1
2
3
C430.1μF
C51 33nF
U6
LMH1983
VDD1
1
VDD2
2
HIN
3
VIN
4
FIN
5
INIT
6
ADDR
7
SDA
8
SCL
9
VDD3
10
NO_LOCK
11
NO_ALIGN
12
NO_REF
13
CLKOUT4-
14
CLKOUT4+
15
VDD6
16
FOUT4(OSCin)
17
GND1
18
VDD4
19
VDD5
20
GND2
21
FOUT3
22
CLKOUT3+
23
CLKOUT3-
24
CBYP3
25
CBYP4
26
CBYP2
27
CLKOUT2+
28
CLKOUT2-
29
FOUT2
30
VDD7
31
VDD8
32
XOin-
33
XOin+
34
CLKOUT1-
35
CLKOUT1+
36
FOUT1
37
VDD9
38
GND3
39
VC_LPF
40
DAP
41
C56
0.1μF
C38
0.1uF
C60
1μF
L3
BLM15AG221SN1D
R11
3kΩ
U8
LMP7711MK
OUTPUT
1
V-
2
+IN
3
-IN
4
EN
5
V+
6
C440.1μF
C41 0.1μF
C52 33nF
C1020.1μF
R15
10kΩ
C57
1μF
C75
10μF
C53
47μF
C54
0.1μF
C50 10μF
C74
0.1μF
C36
10uF
R10 3kΩ
C68
0.1μF
C76
0.1μF
C61
0.1μF
C72
10μF
C70
1μF
C64
0.1μF
C45 0.1μF
C980.1μF
X2
357LB3C027M
1
1
EOH
2
GND
3
OUTPUT
4
NC
5
VCC
6
J5
Cambridge C-SX-141 edge
1
3
2
C400.1μF
C67
0.1μF
C55
1μF
C73
0.1μF
C49 10μF
C46 0.1μF
L2
BLM15AG221SN1D
C58
0.1μF
C78
10μF
U9
LMH1981
REXT
1
GND1
2
VCC1
3
VIN
4
GND2
5
VCC2
6
HSOUT
7
VSOUT
8
VFOUT
9
GND3
10
VCC3
11
CSOUT
12
BPOUT
13
OEOUT
14
C990.1μF
R12
17.4kΩ
C390.1μF
R60
10kΩ
R16
75Ω
C63
0.1μF
C65
0.1μF
C66
22μF
R13
10kΩ
U7
LMK03328
STATUS0
1
STATUS1
2
CAP_DIG
3
VDD_DIG
4
VDD_IN
5
PRIREF_P
6
PRIREF_N
7
REFSEL
8
HW_SW_CTRL
9
SECREF_P
10
SECREF_N
11
GPIO0
12
PDN
13
OUT0_P
14
OUT0_N
15
OUT1_N
16
OUT1_P
17
VDDO_01
18
VDDO_23
19
OUT2_P
20
OUT2_N
21
OUT3_N
22
OUT3_P
23
GPIO1
24
SDA
25
SCL
26
VDD_PLL2
27
CAP_PLL2
28
LF2
29
GPIO2
30
GPIO3
31
GPIO4
32
GPIO5
33
LF1
34
CAP_PLL1
35
VDD_PLL1
36
VDDO_4
37
OUT4_N
38
OUT4_P
39
VDDO_5
40
OUT5_N
41
OUT5_P
42
VDDO_6
43
OUT6_N
44
OUT6_P
45
VDDO_7
46
OUT7_N
47
OUT7_P
48
PAD
49
C59
1μF
C71
0.1μF
C1000.1μF
C79
0.1μF
C4222μF
C37
0.1uF
C48 10μF
C47 0.1μF
C62
22μF
R14 10kΩ
C69
0.1μF
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
18 of 26
Semtech
Proprietary & Confidential
www.semtech.com
Figure 2-4: Level Translators
I
2
C Level Shift
V_ADJ to 3.3V Translation
3.3V_A
V_ADJ
V_ADJ
3.3V_A
V_ADJ
3.3V_A
V_ADJ
3.3V_A
V_ADJ
3.3V_A
3.3V_A
FMC_FPGA_HSYNCn
FMC_FPGA_VSYNCn
FMC_FPGA_FLDn
FMC_LMH1983_INIT
FPGA_HSYNCn
FPGA_VSYNCn
FPGA_FLDn
LMH1983_INIT
FMC_I2C_SDA
FMC_I2C_SCL
FMC_LMH1981_HSYNCn
FMC_LMH1981_VSYNCn
FMC_LMH1981_VIDEO_FMT
FMC_LMH1981_FLD2n
I2C_SCL
I2C_SDA
LMH1981_HSYNCn
LMH1981_VSYNCn
LMH1981_VIDEO_FMT
LMH1981_FLDn
LMH1983_NO_REF
LMH1983_NO_ALIGN
LMH1983_NO_LOCK
FMC_LMH1983_NO_REF
FMC_LMH1983_NO_ALIGN
FMC_LMH1983_NO_LOCK
FPGA_STATUS1
FMC_FPGA_STATUS1
C81
0.1μF
R17 22Ω
R24
4.75kΩ
C84
0.1μF
R21
4.75kΩ
U14
PCA9306DCUR
GND
1
VREF1
2
SCL1
3
SDA1
4
SDA2
5
SCL2
6
VREF2
7
EN
8
U10
74AVC4TD245BQ
VCCA
1
A1
3
A2
4
A3
5
A4
6
GND
8
OE
9
B4
11
B3
12
B2
13
B1
14
VCCB
16
TAB
17
DIR1
2
DIR2
15
DIR3
10
DIR4
7
J3
CON3
1
1
2
2
3
3
vss1
4
vss2
5
U13
74AVC4TD245BQ
VCCA
1
A1
3
A2
4
A3
5
A4
6
GND
8
OE
9
B4
11
B3
12
B2
13
B1
14
VCCB
16
TAB
17
DIR1
2
DIR2
15
DIR3
10
DIR4
7
R18 22Ω
R22
4.75kΩ
C82
0.1μF
TP18
HSYNC
R19 22Ω
R47
10kΩ
R45
10kΩ
TP19
VSYNC
R23
4.75kΩ
R20 22Ω
U11
74AVC4TD245BQ
VCCA
1
A1
3
A2
4
A3
5
A4
6
GND
8
OE
9
B4
11
B3
12
B2
13
B1
14
VCCB
16
TAB
17
DIR1
2
DIR2
15
DIR3
10
DIR4
7
C86
0.1μF
C85
0.1μF
TP20
FLD2n
R46
10kΩ
3.3V to V_ADJ Translation
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
19 of 26
Semtech
Proprietary & Confidential
www.semtech.com
Figure 2-5: FMC Connector
RDK-12GSRD-ALTRA00
Evaluation Board User Guide Rev.0
PDS-061487 February 2017
20 of 26
Semtech
Proprietary & Confidential
www.semtech.com
Figure 2-6: Expansion Connector
3.3V
12V
12V
3.3V
12V
3.3V
3.3V
12V
FMC_120_GPIO14
FMC_120_GPIO3
FMC_120_GSPI_SDOUT
FMC_120_GPIO13
FMC_120_GPIO5
FMC_120_GSPI_SDIN
FMC_120_GPIO6
FMC_120_GPIO12
FMC_120_GSPI_CS3
FMC_120_GSPI_CS2
FMC_120_GSPI_CS4
FMC_120_GPIO7
FMC_120_GPIO4
FMC_120_GSPI_CS1
FMC_120_GPIO2
FMC_120_GPIO8
FMC_120_GPIO11
FMC_120_GPIO15
FMC_120_GPIO16
FMC_120_GPIO1
FMC_120_GSPI_CLK
FMC_120_GPIO10
FMC_120_GPIO9
FMC_12G_IN2-
FMC_12G_IN2+
FMC_12G_IN1-
FMC_12G_IN1+
FMC_12G_IN4-
FMC_12G_IN4+
FMC_12G_IN3-
FMC_12G_IN3+
FMC_12G_OUT1-
FMC_12G_OUT1+
FMC_12G_OUT2-
FMC_12G_OUT2+
FMC_12G_OUT3-
FMC_12G_OUT3+
FMC_12G_OUT4-
FMC_12G_OUT4+
J7B
SMTVHDR4X30SEAM8
C1
C1
C2
C2
C3
C3
C4
C4
C5
C5
C6
C6
C7
C7
C8
C8
C9
C9
C10
C10
C11
C11
C12
C12
C13
C13
C14
C14
C15
C15
C16
C16
C17
C17
C18
C18
C19
C19
C20
C20
D1
D1
D2
D2
D3
D3
D4
D4
D5
D5
D6
D6
D7
D7
D8
D8
D9
D9
D10
D10
D11
D11
D12
D12
D13
D13
D14
D14
D15
D15
D16
D16
D17
D17
D18
D18
D19
D19
D20
D20
J7A
SMTVHDR4X30SEAM8
A1
A1
A2
A2
A3
A3
A4
A4
A5
A5
A6
A6
A7
A7
A8
A8
A9
A9
A10
A10
A11
A11
A12
A12
A13
A13
A14
A14
A15
A15
A16
A16
A17
A17
A18
A18
A19
A19
A20
A20
B1
B1
B2
B2
B3
B3
B4
B4
B5
B5
B6
B6
B7
B7
B8
B8
B9
B9
B10
B10
B11
B11
B12
B12
B13
B13
B14
B14
B15
B15
B16
B16
B17
B17
B18
B18
B19
B19
B20
B20
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
Page is loading ...
  • Page 1 1
  • Page 2 2
  • Page 3 3
  • Page 4 4
  • Page 5 5
  • Page 6 6
  • Page 7 7
  • Page 8 8
  • Page 9 9
  • Page 10 10
  • Page 11 11
  • Page 12 12
  • Page 13 13
  • Page 14 14
  • Page 15 15
  • Page 16 16
  • Page 17 17
  • Page 18 18
  • Page 19 19
  • Page 20 20
  • Page 21 21
  • Page 22 22
  • Page 23 23
  • Page 24 24
  • Page 25 25
  • Page 26 26

Semtech Altera Arria 10 User guide

Altera Arria 10
Brand
Semtech
Model
Altera Arria 10
Type
User guide

Semtech Altera Arria 10 offers a full-featured evaluation platform for Semtech's GS12141 and GS12181 12G UHD-SDI devices. It enables signal re-timing, equalization, and cable driving for professional broadcast applications. With its comprehensive set of features, the board simplifies the integration of these devices into complex video systems, making it an ideal tool for engineers working with high-speed video and broadcast technologies.

Download PDF
report

Ask a question and I''ll find the answer in the document

Finding information in a document is now easier with AI

Related papers

Other documents