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MPC8641D

NXP MPC8641D, MPC8640 Reference guide

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MPC8641D
Integrated Host Processor
Family Reference Manual
Supports
MPC8640
MPC8640D
MPC8641
MPC8641D
MPC8641DRM
Rev. 2, 07/2008
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Document Number: MPC8641DRM
Rev. 2, 07/2008
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Part I—Overview I
MPC8641D Overview 1
Memory Map 2
Signal Descriptions 3
Reset, Clocking, and Initialization 4
Part II—e600 Core II
e600 Core Overview 5
e600 Core Registers and Instruction Set Summary 6
Part III—Memory, Peripherals, and I/O Interfaces III
MPX Coherency Module (MCM) Overview 7
DDR Memory Controllers 8
Programmable Interrupt Controller (PIC) 9
I2C Interfaces 10
DUART 11
Local Bus Controller 12
Enhanced Three-Speed Ethernet Controllers 13
DMA Controller 14
Serial RapidIO Interface 15
PCI Express Interface Controller 16
Part IV—Global Functions and Debug IV
Global Utilities 17
Device Performance Monitor 18
Debug Features and Watchpoint Facilities 19
Complete List of Configuration, Control, and Status Registers A
Revision History B
Glossary GLO
Index IND
I Part I—Overview
1
MPC8641D Overview
2
Memory Map
3
Signal Descriptions
4
Reset, Clocking, and Initialization
II Part II—e600 Core
5
e600 Core Overview
6
e600 Core Registers and Instruction Set Summary
III Part III—Memory, Peripherals, and I/O Interfaces
7
MPX Coherency Module (MCM) Overview
8
DDR Memory Controllers
9
Programmable Interrupt Controller (PIC)
10
I2C Interfaces
11
DUART
12
Local Bus Controller
13
Enhanced Three-Speed Ethernet Controllers
14
DMA Controller
15
Serial RapidIO Interface
16
PCI Express Interface Controller
IV Part IV—Global Functions and Debug
17
Global Utilities
18
Device Performance Monitor
19
Debug Features and Watchpoint Facilities
A Complete List of Configuration, Control, and Status Registers
B Revision History
GLO Glossary
IND
Index
MPC8641D Integrated Host Processor Family Reference Manual, Rev. 2
Freescale Semiconductor v
Contents
Paragraph
Number Title
Page
Number
Co nt ents
About This Book
Audience...........................................................................................................................xci
Organization......................................................................................................................xci
Suggested Reading......................................................................................................... xciii
General Information................................................................................................... xciii
Related Documentation...............................................................................................xciv
Conventions ....................................................................................................................xciv
Signal Conventions..........................................................................................................xcv
Acronyms and Abbreviations ..........................................................................................xcv
Diagrams.........................................................................................................................xcix
Part I
Overview
Chapter 1
MPC8641D Overview
1.1 Preface ............................................................................................................................. 1-3
1.2 MPC8641 Overview........................................................................................................1-4
1.2.1 Key Features ................................................................................................................1-6
1.3 MPC8641 Architecture Overview ................................................................................... 1-9
1.3.1 e600 Core..................................................................................................................... 1-9
1.3.2 DDR2 SDRAM Controllers....................................................................................... 1-14
1.3.3 High-Speed I/O Interfaces......................................................................................... 1-15
1.3.3.1 Serial RapidIO Interface........................................................................................ 1-15
1.3.3.1.1 Serial RapidIO Message Unit............................................................................ 1-16
1.3.3.2 PCI Express Interface ............................................................................................ 1-16
1.3.4 Enhanced Three-Speed Ethernet Controllers............................................................. 1-17
1.3.5 MPX Coherency Module (MCM)..............................................................................1-19
1.3.6 Low Memory Offset Mode (Core 1).......................................................................... 1-19
1.3.7 Address Translation and Mapping Units (ATMUs)...................................................1-20
1.3.8 Local Bus Controller (LBC) ...................................................................................... 1-20
1.3.9 Four-Channel DMA Controller ................................................................................. 1-21
1.3.10 Programmable Interrupt Controller (PIC).................................................................. 1-21
1.3.11 I
2
C Controller ............................................................................................................1-22
1.3.12 Boot Sequencer.......................................................................................................... 1-22
1.3.13 Dual Universal Asynchronous Receiver/Transmitter (DUART)...............................1-22
1.3.14 Power Management ................................................................................................... 1-23
1.3.15 Clocking..................................................................................................................... 1-23
1.3.16 Address Map..............................................................................................................1-24
MPC8641D Integrated Host Processor Family Reference Manual, Rev. 2
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Contents
Paragraph
Number Title
Page
Number
1.4 Navigating Transactions Between the eTSECs and I/O Ports....................................... 1-24
1.4.1 Data Traffic is Routed Between eTSEC and the PCI Express Port
for Transmission .................................................................................................... 1-24
1.4.1.1 eTSEC to PCI Express........................................................................................... 1-24
1.4.1.2 PCI Express to eTSEC........................................................................................... 1-25
1.5 MPC8641D Application Examples ............................................................................... 1-26
1.5.1 Dual-Core Device Considerations ............................................................................. 1-26
1.5.1.1 Symmetric Multiprocessing Configuration ...........................................................1-27
1.5.1.2 Cooperative Multiprocessing.................................................................................1-29
Chapter 2
Memory Map
2.1 Overview..........................................................................................................................2-1
2.1.1 Low Memory Offset Mode.......................................................................................... 2-2
2.2 Local Access Windows....................................................................................................2-2
2.2.1 Local Access Window Registers ................................................................................. 2-3
2.2.1.1 Local Access Window n Base Address Registers
(LAWBAR0–LAWBAR9)................................................................................... 2-4
2.2.1.2 Local Access Window n Attributes Registers (LAWAR0–LAWAR9).................... 2-4
2.2.2 Precedence of Local Access Windows ........................................................................2-6
2.2.3 Configuring Local Access Windows ........................................................................... 2-6
2.2.4 Distinguishing Local Access Windows from Other Mapping Functions.................... 2-6
2.2.5 Illegal Interaction Between Local Access Windows and DDR Chip Selects.............. 2-7
2.2.6 Local Address Map Example....................................................................................... 2-7
2.3 Address Translation and Mapping Units ......................................................................... 2-8
2.3.1 Address Translation ..................................................................................................... 2-9
2.3.2 Outbound ATMUs........................................................................................................2-9
2.3.3 Inbound ATMUs.......................................................................................................... 2-9
2.3.3.1 Illegal Interaction Between Inbound ATMUs and LAWs .....................................2-10
2.4 Configuration, Control, and Status Registers ................................................................ 2-10
2.4.1 Accessing CCSR Memory from the Local Processor................................................ 2-11
2.4.2 Accessing CCSR Memory from External Masters.................................................... 2-11
2.4.3 Organization of CCSR Space .................................................................................... 2-12
2.4.3.1 General Utilities Registers..................................................................................... 2-13
2.4.3.1.1 General Utilities Register Organization............................................................. 2-14
2.4.3.2 Programmable Interrupt Controller Registers ....................................................... 2-15
2.4.3.3 Serial RapidIO Registers ....................................................................................... 2-16
2.4.3.4 Device-Specific Utilities Registers........................................................................2-17
2.4.4 CCSR Address Map................................................................................................... 2-18
MPC8641D Integrated Host Processor Family Reference Manual, Rev. 2
Freescale Semiconductor vii
Contents
Paragraph
Number Title
Page
Number
Chapter 3
Signal Descriptions
3.1 Signals Overview.............................................................................................................3-1
3.2 Configuration Signals Sampled at Reset ....................................................................... 3-24
Chapter 4
Reset, Clocking, and Initialization
4.1 Overview..........................................................................................................................4-1
4.2 External Signal Descriptions ........................................................................................... 4-1
4.2.1 System Control Signals................................................................................................ 4-2
4.2.2 Clock Signals...............................................................................................................4-3
4.3 Memory Map/Register Definition ................................................................................... 4-3
4.3.1 Local Configuration Control........................................................................................ 4-3
4.3.1.1 Accessing Configuration, Control, and Status Registers.........................................4-3
4.3.1.1.1 POR I/O Impedance Control Register (PORIMPCR).........................................4-4
4.3.1.1.2 Updating CCSRBAR........................................................................................... 4-4
4.3.1.1.3 Configuration, Control, and Status Base Address Register (CCSRBAR)...........4-5
4.3.1.2 Accessing Alternate Configuration Space............................................................... 4-5
4.3.1.2.1 Alternate Configuration Base Address Register (ALTCBAR)............................ 4-6
4.3.1.2.2 Alternate Configuration Attribute Register (ALTCAR)...................................... 4-6
4.3.1.3 Boot Page Translation.............................................................................................. 4-7
4.3.1.3.1 Boot Page Translation Register (BPTR).............................................................. 4-8
4.3.2 Boot Sequencer............................................................................................................ 4-8
4.4 Functional Description..................................................................................................... 4-8
4.4.1 Reset Operations.......................................................................................................... 4-8
4.4.1.1 Soft Reset.................................................................................................................4-9
4.4.1.2 Hard Reset ...............................................................................................................4-9
4.4.2 Power-On Reset Sequence........................................................................................... 4-9
4.4.3 Power-On Reset Configuration.................................................................................. 4-11
4.4.3.1 System PLL Ratio.................................................................................................. 4-12
4.4.3.2 Platform Frequency ............................................................................................... 4-13
4.4.3.3 e600 Core PLL Ratio............................................................................................. 4-13
4.4.3.4 Core 1 Enable ........................................................................................................ 4-14
4.4.3.5 e600 Core 1 Low Memory Offset Mode ...............................................................4-14
4.4.3.6 Boot ROM Location .............................................................................................. 4-14
4.4.3.7 Alternate Boot Vector Location............................................................................. 4-15
4.4.3.8 SerDes Port Selection ............................................................................................ 4-16
4.4.3.9 SerDes Host/Agent Configuration......................................................................... 4-17
4.4.3.10 CPU Boot Configuration ....................................................................................... 4-17
MPC8641D Integrated Host Processor Family Reference Manual, Rev. 2
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Contents
Paragraph
Number Title
Page
Number
4.4.3.11 Boot Sequencer Configuration .............................................................................. 4-18
4.4.3.12 DDR SDRAM Type............................................................................................... 4-19
4.4.3.13 eTSECn Width....................................................................................................... 4-19
4.4.3.14 eTSECn Protocol ................................................................................................... 4-20
4.4.3.15 Serial RapidIO Device ID...................................................................................... 4-20
4.4.3.16 Serial RapidIO System Size................................................................................... 4-21
4.4.3.17 Memory Debug Configuration .............................................................................. 4-21
4.4.3.18 DDR Debug Configuration....................................................................................4-22
4.4.3.19 General-Purpose POR Configuration .................................................................... 4-22
4.4.4 Clocking.....................................................................................................................4-23
4.4.4.1 System Clock......................................................................................................... 4-23
4.4.4.2 RapidIO and PCI Express Clocks.......................................................................... 4-24
4.4.4.3 Ethernet Clocks...................................................................................................... 4-24
Part II
e600 Core
Chapter 5
e600 Core Overview
5.1 e600 Core Overview........................................................................................................5-1
5.2 e600 Core Features ..........................................................................................................5-5
5.2.1 Instruction Flow......................................................................................................... 5-10
5.2.1.1 Instruction Queue and Dispatch Unit .................................................................... 5-10
5.2.1.2 Branch Processing Unit (BPU).............................................................................. 5-10
5.2.1.3 Completion Unit .................................................................................................... 5-11
5.2.1.4 Independent Execution Units................................................................................. 5-12
5.2.1.4.1 AltiVec Vector Permute Unit (VPU) ................................................................. 5-12
5.2.1.4.2 AltiVec Vector Integer Unit 1 (VIU1) ............................................................... 5-12
5.2.1.4.3 AltiVec Vector Integer Unit 2 (VIU2) ............................................................... 5-12
5.2.1.4.4 AltiVec Vector Floating-Point Unit (VFPU) .....................................................5-12
5.2.1.4.5 Integer Units (IUs)............................................................................................. 5-12
5.2.1.4.6 Floating-Point Unit (FPU)................................................................................. 5-13
5.2.1.4.7 Load/Store Unit (LSU) ...................................................................................... 5-13
5.2.2 Memory Management Units (MMUs)....................................................................... 5-13
5.2.3 L1 Instruction and Data Caches Within the Core ...................................................... 5-14
5.2.4 L2 Cache Implementation.......................................................................................... 5-16
5.2.5 Core Interface ............................................................................................................ 5-18
5.2.6 Overview of Core Interface Accesses........................................................................ 5-18
5.2.6.1 Signal Groupings ...................................................................................................5-19
5.2.6.2 Clocking.................................................................................................................5-20
MPC8641D Integrated Host Processor Family Reference Manual, Rev. 2
Freescale Semiconductor ix
Contents
Paragraph
Number Title
Page
Number
5.2.7 Power and Thermal Management.............................................................................. 5-20
5.2.8 Core Performance Monitor........................................................................................ 5-21
5.3 e600 Core Architectural Implementation ...................................................................... 5-21
5.3.1 PowerPC ISA Registers and Programming Model....................................................5-23
5.3.2 Instruction Set............................................................................................................5-25
5.3.2.1 PowerPC Instruction Set........................................................................................ 5-25
5.3.2.2 AltiVec Instruction Set........................................................................................... 5-26
5.3.2.3 e600 Core Instruction Set ...................................................................................... 5-27
5.3.3 Cache Implementation within the Core ..................................................................... 5-27
5.3.3.1 PowerPC Cache Model.......................................................................................... 5-27
5.3.3.2 e600 Core Cache Implementation .........................................................................5-28
5.3.4 Interrupt Model.......................................................................................................... 5-28
5.3.4.1 PowerPC Interrupt Model...................................................................................... 5-28
5.3.4.2 e600 Core Interrupts.............................................................................................. 5-29
5.3.4.2.1 Sources of tea_ assertion ................................................................................... 5-31
5.3.5 Memory Management................................................................................................ 5-32
5.3.5.1 PowerPC Memory Management Model................................................................ 5-32
5.3.5.2 e600 Core Memory Management Implementation................................................ 5-33
5.3.6 Instruction Timing ..................................................................................................... 5-33
5.3.7 AltiVec Implementation............................................................................................. 5-38
5.4 MPC8641D Implementation Details .............................................................................5-39
Chapter 6
e600 Core Registers and Instruction Set Summary
6.1 e600 Core Register Set ....................................................................................................6-1
6.1.1 Register Set Overview ................................................................................................. 6-1
6.1.2 e600 Core Register Set ................................................................................................ 6-3
6.1.3 User-Level Registers (UISA)....................................................................................... 6-8
6.1.4 Supervisor-Level Registers (OEA).............................................................................. 6-8
6.1.4.1 Processor Version Register (PVR)........................................................................... 6-8
6.1.4.2 System Version Register (SVR)............................................................................... 6-9
6.1.4.3 Processor Identification Register (PIR)................................................................... 6-9
6.1.4.4 Machine State Register (MSR)................................................................................ 6-9
6.1.4.5 Machine Status Save/Restore Registers (SRR0, SRR1)........................................6-12
6.1.4.6 SDR1 Register ....................................................................................................... 6-12
6.1.5 User-Level Registers (VEA)...................................................................................... 6-13
6.1.5.1 Time Base Registers (TBL, TBU)......................................................................... 6-13
6.1.6 e600-Core-Specific Register Descriptions................................................................. 6-13
6.1.6.1 Hardware Implementation-Dependent Register 0 (HID0) .................................... 6-14
6.1.6.2 Hardware Implementation-Dependent Register 1 (HID1) .................................... 6-19
MPC8641D Integrated Host Processor Family Reference Manual, Rev. 2
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Contents
Paragraph
Number Title
Page
Number
6.1.6.3 Memory Subsystem Control Register (MSSCR0).................................................6-20
6.1.6.4 Memory Subsystem Status Register (MSSSR0)....................................................6-21
6.1.6.5 Instruction and Data Cache Registers.................................................................... 6-22
6.1.6.5.1 L2 Cache Control Register (L2CR)................................................................... 6-22
6.1.6.5.2 L2 Error Injection Mask High Register (L2ERRINJHI)...................................6-24
6.1.6.5.3 L2 Error Injection Mask High Register (L2ERRINJLO).................................. 6-24
6.1.6.5.4 L2 Error Injection Mask Control Register (L2ERRINJCTL) ........................... 6-25
6.1.6.5.5 L2 Error Capture Data High Register (L2CAPTDATAHI)............................... 6-25
6.1.6.5.6 L2 Error Capture Data Low Register (L2CAPTDATALO)...............................6-26
6.1.6.5.7 L2 Error Syndrome Register (L2CAPTECC)....................................................6-26
6.1.6.5.8 L2 Error Detect Register (L2ERRDET)............................................................ 6-27
6.1.6.5.9 L2 Error Disable Register (L2ERRDIS) ........................................................... 6-28
6.1.6.5.10 L2 Error Interrupt Enable Register (L2ERRINTEN)........................................ 6-29
6.1.6.5.11 L2 Error Attributes Capture Register (L2ERRATTR) ...................................... 6-29
6.1.6.5.12 L2 Error Address Error Capture Register (L2ERRADDR)...............................6-30
6.1.6.5.13 L2 Error Address Error Capture Register (L2ERREADDR)............................ 6-31
6.1.6.5.14 L2 Error Control Register (L2ERRCTL) ..........................................................6-31
6.1.6.5.15 Instruction Cache and Interrupt Control Register (ICTRL) .............................. 6-32
6.1.6.5.16 Load/Store Control Register (LDSTCR)...........................................................6-34
6.1.6.6 Instruction Address Breakpoint Register (IABR).................................................. 6-34
6.1.6.7 Memory Management Registers Used for Software Table Searching................... 6-35
6.1.6.7.1 TLB Miss Register (TLBMISS)........................................................................ 6-35
6.1.6.7.2 Page Table Entry Registers (PTEHI and PTELO).............................................6-35
6.1.6.8 Thermal Management Register.............................................................................. 6-37
6.1.6.8.1 Instruction Cache Throttling Control Register (ICTC) .....................................6-37
6.1.6.9 Performance Monitor Registers............................................................................. 6-38
6.1.6.9.1 Monitor Mode Control Register 0 (MMCR0)...................................................6-38
6.1.6.9.2 User Monitor Mode Control Register 0 (UMMCR0)........................................ 6-41
6.1.6.9.3 Monitor Mode Control Register 1 (MMCR1)...................................................6-41
6.1.6.9.4 User Monitor Mode Control Register 1 (UMMCR1)........................................ 6-41
6.1.6.9.5 Monitor Mode Control Register 2 (MMCR2)...................................................6-41
6.1.6.9.6 User Monitor Mode Control Register 2 (UMMCR2)........................................ 6-42
6.1.6.9.7 Breakpoint Address Mask Register (BAMR)....................................................6-42
6.1.6.9.8 Performance Monitor Counter Registers (PMC1–PMC6) ................................ 6-43
6.1.6.9.9 User Performance Monitor Counter Registers (UPMC1–UPMC6).................. 6-44
6.1.6.9.10 Sampled Instruction Address Register (SIAR).................................................. 6-44
6.1.6.9.11 User-Sampled Instruction Address Register (USIAR)......................................6-45
6.1.6.9.12 Sampled Data Address Register (SDAR) and User-Sampled Data
Address Register (USDAR) .......................................................................... 6-45
6.1.7 Reset Settings.............................................................................................................6-45
6.2 Operand Conventions .................................................................................................... 6-48
MPC8641D Integrated Host Processor Family Reference Manual, Rev. 2
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Number Title
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Number
6.2.1 Floating-Point Execution Models—UISA................................................................. 6-48
6.2.2 Data Organization in Memory and Data Transfers....................................................6-48
6.2.3 Alignment and Misaligned Accesses......................................................................... 6-49
6.2.4 Floating-Point Operands............................................................................................ 6-49
6.3 Instruction Set Summary ............................................................................................... 6-50
6.3.1 Classes of Instructions ............................................................................................... 6-51
6.3.1.1 Definition of Boundedly Undefined......................................................................6-51
6.3.1.2 Defined Instruction Class ...................................................................................... 6-51
6.3.1.3 Illegal Instruction Class......................................................................................... 6-52
6.3.1.4 Reserved Instruction Class .................................................................................... 6-53
6.3.2 Addressing Modes ..................................................................................................... 6-53
6.3.2.1 Memory Addressing .............................................................................................. 6-53
6.3.2.2 Memory Operands ................................................................................................. 6-53
6.3.2.3 Effective Address Calculation ............................................................................... 6-54
6.3.2.4 Synchronization..................................................................................................... 6-54
6.3.2.4.1 Context Synchronization ................................................................................... 6-54
6.3.2.4.2 Execution Synchronization................................................................................ 6-58
6.3.2.4.3 Instruction-Related Interrupts............................................................................ 6-58
6.3.3 Instruction Set Overview ........................................................................................... 6-58
6.3.4 PowerPC UISA Instructions...................................................................................... 6-59
6.3.4.1 Integer Instructions................................................................................................ 6-59
6.3.4.1.1 Integer Arithmetic Instructions.......................................................................... 6-59
6.3.4.1.2 Integer Compare Instructions ............................................................................ 6-60
6.3.4.1.3 Integer Logical Instructions............................................................................... 6-61
6.3.4.1.4 Integer Rotate and Shift Instructions................................................................. 6-61
6.3.4.2 Floating-Point Instructions .................................................................................... 6-62
6.3.4.2.1 Floating-Point Arithmetic Instructions.............................................................. 6-63
6.3.4.2.2 Floating-Point Multiply-Add Instructions.........................................................6-63
6.3.4.2.3 Floating-Point Rounding and Conversion Instructions .....................................6-64
6.3.4.2.4 Floating-Point Compare Instructions................................................................. 6-64
6.3.4.2.5 Floating-Point Status and Control Register Instructions...................................6-64
6.3.4.2.6 Floating-Point Move Instructions...................................................................... 6-65
6.3.4.3 Load and Store Instructions................................................................................... 6-65
6.3.4.3.1 Self-Modifying Code......................................................................................... 6-66
6.3.4.3.2 Integer Load and Store Address Generation...................................................... 6-66
6.3.4.3.3 Register Indirect Integer Load Instructions.......................................................6-66
6.3.4.3.4 Integer Store Instructions................................................................................... 6-68
6.3.4.3.5 Integer Store Gathering...................................................................................... 6-68
6.3.4.3.6 Integer Load and Store with Byte-Reverse Instructions.................................... 6-69
6.3.4.3.7 Integer Load and Store Multiple Instructions.................................................... 6-69
6.3.4.3.8 Integer Load and Store String Instructions........................................................ 6-69
MPC8641D Integrated Host Processor Family Reference Manual, Rev. 2
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Contents
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Number Title
Page
Number
6.3.4.3.9 Floating-Point Load and Store Address Generation.......................................... 6-70
6.3.4.3.10 Floating-Point Store Instructions....................................................................... 6-71
6.3.4.4 Branch and Flow Control Instructions................................................................... 6-73
6.3.4.4.1 Branch Instruction Address Calculation............................................................ 6-73
6.3.4.4.2 Branch Instructions............................................................................................ 6-73
6.3.4.4.3 Condition Register Logical Instructions............................................................ 6-74
6.3.4.4.4 Trap Instructions................................................................................................ 6-74
6.3.4.5 System Linkage Instruction—UISA...................................................................... 6-75
6.3.4.6 Processor Control Instructions—UISA ................................................................. 6-75
6.3.4.6.1 Move To/From Condition Register Instructions................................................ 6-75
6.3.4.6.2 Move To/From Special-Purpose Register Instructions—UISA ........................6-75
6.3.4.7 Memory Synchronization Instructions—UISA.....................................................6-77
6.3.5 PowerPC VEA Instructions ....................................................................................... 6-77
6.3.5.1 Processor Control Instructions—VEA .................................................................. 6-78
6.3.5.2 Memory Synchronization Instructions—VEA ...................................................... 6-78
6.3.5.3 Memory Control Instructions—VEA .................................................................... 6-79
6.3.5.3.1 User-Level Cache Instructions—VEA .............................................................. 6-79
6.3.5.4 Optional External Control Instructions.................................................................. 6-82
6.3.6 PowerPC OEA Instructions ....................................................................................... 6-82
6.3.6.1 System Linkage Instructions—OEA ..................................................................... 6-82
6.3.6.2 Processor Control Instructions—OEA .................................................................. 6-82
6.3.6.3 Memory Control Instructions—OEA .................................................................... 6-87
6.3.6.3.1 Supervisor-Level Cache Management Instruction—OEA................................ 6-87
6.3.6.3.2 Translation Lookaside Buffer Management Instructions—OEA......................6-87
6.3.7 Recommended Simplified Mnemonics...................................................................... 6-88
6.3.8 Implementation-Specific Instructions........................................................................ 6-88
6.4 AltiVec Instructions ....................................................................................................... 6-91
6.5 AltiVec UISA Instructions............................................................................................. 6-92
6.5.1 Vector Integer Instructions......................................................................................... 6-92
6.5.1.1 Vector Integer Arithmetic Instructions .................................................................. 6-92
6.5.1.2 Vector Integer Compare Instructions..................................................................... 6-94
6.5.1.3 Vector Integer Logical Instructions ....................................................................... 6-95
6.5.1.4 Vector Integer Rotate and Shift Instructions.......................................................... 6-95
6.5.2 Vector Floating-Point Instructions............................................................................. 6-95
6.5.2.1 Vector Floating-Point Arithmetic Instructions.......................................................6-96
6.5.2.2 Vector Floating-Point Multiply-Add Instructions..................................................6-96
6.5.2.3 Vector Floating-Point Rounding and Conversion Instructions..............................6-96
6.5.2.4 Vector Floating-Point Compare Instructions.........................................................6-97
6.5.2.5 Vector Floating-Point Estimate Instructions..........................................................6-97
6.5.3 Vector Load and Store Instructions............................................................................ 6-98
6.5.3.1 Vector Load Instructions........................................................................................ 6-98
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6.5.3.2 Vector Load Instructions Supporting Alignment...................................................6-98
6.5.3.3 Vector Store Instructions........................................................................................ 6-99
6.5.4 Control Flow..............................................................................................................6-99
6.5.5 Vector Permutation and Formatting Instructions.......................................................6-99
6.5.5.1 Vector Pack Instructions ........................................................................................ 6-99
6.5.5.2 Vector Unpack Instructions.................................................................................. 6-100
6.5.5.3 Vector Merge Instructions.................................................................................... 6-100
6.5.5.4 Vector Splat Instructions...................................................................................... 6-101
6.5.5.5 Vector Permute Instructions................................................................................. 6-101
6.5.5.6 Vector Select Instruction...................................................................................... 6-102
6.5.5.7 Vector Shift Instructions ...................................................................................... 6-102
6.5.5.8 Vector Status and Control Register Instructions.................................................. 6-102
6.6 AltiVec VEA Instructions............................................................................................ 6-103
6.6.1 AltiVec Vector Memory Control Instructions—VEA..............................................6-103
6.6.2 AltiVec Instructions with Specific Implementations for the e600 Core.................. 6-104
Part III
Memory, Peripherals, and I/O Interfaces
Chapter 7
MPX Coherency Module (MCM) Overview
7.1 Introduction...................................................................................................................... 7-1
7.1.1 Overview...................................................................................................................... 7-3
7.2 Features............................................................................................................................ 7-3
7.3 Modes of Operation ......................................................................................................... 7-4
7.4 Memory Map/Register Definition ................................................................................... 7-4
7.4.1 Register Descriptions................................................................................................... 7-5
7.4.1.1 Address Bus Configuration Register (ABCR).........................................................7-5
7.4.1.2 Data Bus Configuration Register (DBCR).............................................................. 7-6
7.4.1.3 Port Configuration Register (PCR).......................................................................... 7-6
7.4.1.4 Error Detect Register (EDR) ................................................................................... 7-7
7.4.1.5 Error Enable Register (EER) ................................................................................... 7-9
7.4.1.6 Error Attributes Capture Register (EATR) .............................................................. 7-9
7.4.1.7 Error Low Address Register (ELADR) ................................................................. 7-11
7.4.1.8 Error High Address Register (EHADR)................................................................ 7-11
7.5 Functional Description................................................................................................... 7-11
7.5.1 I/O Arbiter.................................................................................................................. 7-11
7.5.2 MPX Address Arbiter................................................................................................ 7-12
7.5.3 Transaction Queue ..................................................................................................... 7-12
7.5.4 Memory Controller Interleaving................................................................................ 7-12
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7.5.5 Global Data Multiplexor............................................................................................ 7-13
7.5.5.1 Direct Data Bus...................................................................................................... 7-13
7.5.6 MPX Interface............................................................................................................7-13
7.6 Initialization/Application Information...........................................................................7-13
Chapter 8
DDR Memory Controllers
8.1 Introduction...................................................................................................................... 8-1
8.2 Features............................................................................................................................ 8-2
8.2.1 Modes of Operation ..................................................................................................... 8-3
8.3 External Signal Descriptions ........................................................................................... 8-3
8.3.1 Signals Overview......................................................................................................... 8-3
8.3.2 Detailed Signal Descriptions ....................................................................................... 8-6
8.3.2.1 Memory Interface Signals........................................................................................ 8-6
8.3.2.2 Clock Interface Signals.......................................................................................... 8-10
8.3.2.3 Debug Signals........................................................................................................ 8-10
8.4 Memory Map/Register Definition ................................................................................. 8-10
8.4.1 Register Descriptions................................................................................................. 8-12
8.4.1.1 Chip Select Memory Bounds (CSn_BNDS)..........................................................8-12
8.4.1.2 Chip Select Configuration (CSn_CONFIG).......................................................... 8-13
8.4.1.3 DDR SDRAM Timing Configuration 3 (TIMING_CFG_3).................................8-15
8.4.1.4 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0).................................8-16
8.4.1.5 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1).................................8-18
8.4.1.6 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2).................................8-20
8.4.1.7 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 8-22
8.4.1.8 DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)......................8-24
8.4.1.9 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................8-26
8.4.1.10 DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)..................... 8-27
8.4.1.11 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL).................8-27
8.4.1.12 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 8-30
8.4.1.13 DDR SDRAM Data Initialization (DDR_DATA_INIT) .......................................8-30
8.4.1.14 DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)............................. 8-31
8.4.1.15 DDR Initialization Address (DDR_INIT_ADDR)................................................ 8-31
8.4.1.16 DDR Initialization Enable Extended Address (DDR_INIT_EXT_ADDR).......... 8-32
8.4.1.17 DDR Debug Status Register 1 (DDRDSR_1) .......................................................8-33
8.4.1.18 DDR Debug Status Register 2 (DDRDSR_2) .......................................................8-33
8.4.1.19 DDR Control Driver Register 1 (DDRCDR_1).....................................................8-34
8.4.1.20 DDR Control Driver Register 2 (DDRCDR_2).....................................................8-35
8.4.1.21 DDR IP Block Revision 1 (DDR_IP_REV1)........................................................ 8-36
8.4.1.22 DDR IP Block Revision 2 (DDR_IP_REV2)........................................................ 8-37
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8.4.1.23 Memory Data Path Error Injection Mask High
(DATA_ERR_INJECT_HI)............................................................................... 8-37
8.4.1.24 Memory Data Path Error Injection Mask Low
(DATA_ERR_INJECT_LO).............................................................................. 8-38
8.4.1.25 Memory Data Path Error Injection Mask ECC (ERR_INJECT)...........................8-38
8.4.1.26 Memory Data Path Read Capture High (CAPTURE_DATA_HI)......................... 8-39
8.4.1.27 Memory Data Path Read Capture Low (CAPTURE_DATA_LO) ........................ 8-39
8.4.1.28 Memory Data Path Read Capture ECC (CAPTURE_ECC)..................................8-40
8.4.1.29 Memory Error Detect (ERR_DETECT)................................................................ 8-40
8.4.1.30 Memory Error Disable (ERR_DISABLE)............................................................. 8-41
8.4.1.31 Memory Error Interrupt Enable (ERR_INT_EN).................................................. 8-42
8.4.1.32 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES).......................... 8-43
8.4.1.33 Memory Error Address Capture (CAPTURE_ADDRESS) ..................................8-44
8.4.1.34 Memory Error Extended Address Capture
(CAPTURE_EXT_ADDRESS).........................................................................8-44
8.4.1.35 Single-Bit ECC Memory Error Management (ERR_SBE) ...................................8-45
8.5 Functional Description................................................................................................... 8-45
8.5.1 DDR SDRAM Interface Operation............................................................................ 8-50
8.5.1.1 Supported DDR SDRAM Organizations............................................................... 8-50
8.5.2 DDR SDRAM Address Multiplexing........................................................................ 8-52
8.5.3 JEDEC Standard DDR SDRAM Interface Commands.............................................8-57
8.5.4 DDR SDRAM Interface Timing................................................................................ 8-59
8.5.4.1 Clock Distribution ................................................................................................. 8-62
8.5.5 DDR SDRAM Mode-Set Command Timing.............................................................8-63
8.5.6 DDR SDRAM Registered DIMM Mode................................................................... 8-64
8.5.7 DDR SDRAM Write Timing Adjustments................................................................ 8-64
8.5.8 DDR SDRAM Refresh .............................................................................................. 8-65
8.5.8.1 DDR SDRAM Refresh Timing.............................................................................. 8-66
8.5.8.2 DDR SDRAM Refresh and Power-Saving Modes................................................ 8-67
8.5.8.2.1 Self-Refresh in Sleep Mode............................................................................... 8-68
8.5.9 DDR Data Beat Ordering........................................................................................... 8-69
8.5.10 Page Mode and Logical Bank Retention ................................................................... 8-69
8.5.11 Error Checking and Correcting (ECC) ...................................................................... 8-70
8.5.12 Error Management..................................................................................................... 8-72
8.6 Initialization/Application Information...........................................................................8-73
8.6.1 Programming Differences between Memory Types.................................................. 8-74
8.6.2 DDR SDRAM Initialization Sequence...................................................................... 8-77
Chapter 9
Programmable Interrupt Controller (PIC)
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9.1 Introduction...................................................................................................................... 9-1
9.1.1 Overview...................................................................................................................... 9-1
9.1.2 The PIC in Multiple-Processor Implementations........................................................ 9-4
9.1.3 Interrupts to the Processor Core................................................................................... 9-4
9.1.4 Modes of Operation ..................................................................................................... 9-5
9.1.4.1 Mixed Mode (GCR[M] = 1).................................................................................... 9-5
9.1.4.2 Pass-Through Mode (GCR[M] = 0) ........................................................................9-5
9.1.5 Interrupt Sources..........................................................................................................9-6
9.1.5.1 Interrupt Routing—Mixed Mode.............................................................................9-6
9.1.5.2 Interrupt Destinations .............................................................................................. 9-7
9.1.5.3 Internal Interrupt Sources ........................................................................................ 9-7
9.2 External Signal Descriptions ........................................................................................... 9-8
9.2.1 Signal Overview .......................................................................................................... 9-8
9.2.2 Detailed Signal Descriptions ....................................................................................... 9-9
9.3 Memory Map/Register Definition ................................................................................... 9-9
9.3.1 Global Registers......................................................................................................... 9-18
9.3.1.1 Block Revision Register 1 (BRR1)........................................................................ 9-18
9.3.1.2 Block Revision Register 2 (BRR2)........................................................................ 9-19
9.3.1.3 Feature Reporting Register (FRR)......................................................................... 9-19
9.3.1.4 Global Configuration Register (GCR)................................................................... 9-20
9.3.1.5 Vendor Identification Register (VIR) ....................................................................9-21
9.3.1.6 Processor Core Initialization Register (PIR) .........................................................9-21
9.3.1.7 Processor Reset Register (PRR) ............................................................................ 9-22
9.3.1.8 Interprocessor Interrupt Vector/Priority Registers (IPIVPR0–IPIVPR3).............. 9-23
9.3.1.9 Spurious Vector Register (SVR)............................................................................ 9-23
9.3.2 Global Timer Registers.............................................................................................. 9-24
9.3.2.1 Timer Frequency Reporting Register (TFRRA–TFRRB) ..................................... 9-24
9.3.2.2 Global Timer Current Count Registers (GTCCRA0–GTCCRA3,
GTCCRB0–GTCCRB3)..................................................................................... 9-25
9.3.2.3 Global Timer Base Count Registers (GTBCRA0–GTBCRA3,
GTBCRB0–GTBCRB3)..................................................................................... 9-25
9.3.2.4 Global Timer Vector/Priority Registers (GTVPRA0–GTVPRA3,
GTVPRB0–GTVPRB3)..................................................................................... 9-26
9.3.2.5 Global Timer Destination Registers (GTDRA0–GTDRA3,
GTDRB0–GTDRB3).......................................................................................... 9-27
9.3.2.6 Timer Control Registers (TCRA–TCRB).............................................................. 9-27
9.3.3 IRQ_OUT and Critical Interrupt Summary Registers............................................... 9-29
9.3.3.1 External Interrupt Summary Register (ERQSR) ................................................... 9-29
9.3.3.2 IRQ_OUT Summary Register 0 (IRQSR0)........................................................... 9-30
9.3.3.3 IRQ_OUT Summary Register 1 (IRQSR1)........................................................... 9-31
9.3.3.4 IRQ_OUT Summary Register 2 (IRQSR2)........................................................... 9-31
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9.3.3.5 Critical Interrupt Summary Register 0 (CISR0)....................................................9-32
9.3.3.6 Critical Interrupt Summary Register 1 (CISR1)....................................................9-32
9.3.3.7 Critical Interrupt Summary Register 2 (CISR2)....................................................9-33
9.3.4 Performance Monitor Mask Registers (PMMRs)......................................................9-33
9.3.4.1 Performance Monitor Mask Registers 0 (PM0MR0–PM3MR0) .......................... 9-33
9.3.4.2 Performance Monitor Mask Registers 1 (PM0MR1–PM3MR1) .......................... 9-34
9.3.4.3 Performance Monitor Mask Registers 2 (PM0MR2–PM3MR2) .......................... 9-35
9.3.5 Message Registers...................................................................................................... 9-35
9.3.5.1 Message Registers (MSGR0–MSGR3)................................................................. 9-35
9.3.5.2 Message Enable Register (MER)........................................................................... 9-36
9.3.5.3 Message Status Register (MSR) ............................................................................ 9-36
9.3.6 Shared Message Signaled Registers .......................................................................... 9-37
9.3.6.1 Shared Message Signaled Interrupt Registers (MSIR0–MSIR7)..........................9-37
9.3.6.2 Shared Message Signaled Interrupt Status Register (MSISR)...............................9-38
9.3.6.3 Shared Message Signaled Interrupt Index Register (MSIIR)................................9-38
9.3.6.4 Shared Message Signaled Interrupt Vector/Priority Register (MSIVPRs)............ 9-39
9.3.6.5 Shared Message Signaled Interrupt Destination Registers 0–7 (MSIDRn)........... 9-40
9.3.7 Interrupt Source Configuration Registers.................................................................. 9-40
9.3.7.1 External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) .......................9-42
9.3.7.2 External Interrupt Destination Registers (EIDR0–EIDR11) .................................9-43
9.3.7.3 Internal Interrupt Vector/Priority Registers (IIVPRn)...........................................9-44
9.3.7.4 Internal Interrupt Destination Registers (IIDRn)...................................................9-45
9.3.7.5 Messaging Interrupt Vector/Priority Registers (MIVPRn).................................... 9-46
9.3.7.6 Messaging Interrupt Destination Registers (MIDR0–MIDR3)............................. 9-46
9.3.8 Per-CPU (Private Access) Registers.......................................................................... 9-47
9.3.8.1 Interprocessor Interrupt Dispatch Register (IPIDR0–IPIDR3).............................9-49
9.3.8.2 Processor Core Current Task Priority Registers 0–1 (CTPR0–CTPR1) ...............9-49
9.3.8.3 Who Am I Registers 0–1 (WHOAMI0–WHOAMI1)...........................................9-50
9.3.8.4 Processor Core Interrupt Acknowledge Registers 0–1 (IACK0–IACK1).............9-51
9.3.8.5 Processor Core End of Interrupt Registers (EOI0–EOI1) .....................................9-51
9.4 Functional Description................................................................................................... 9-52
9.4.1 Flow of Interrupt Control........................................................................................... 9-52
9.4.1.1 Interrupts Routed to cint
or IRQ_OUT.................................................................. 9-52
9.4.1.2 Interrupts Routed to int.......................................................................................... 9-53
9.4.1.2.1 Nesting of Interrupts.......................................................................................... 9-55
9.4.1.2.2 Interrupt Source Priority.................................................................................... 9-55
9.4.1.2.3 Interrupt Acknowledge...................................................................................... 9-56
9.4.1.2.4 Spurious Vector Generation............................................................................... 9-56
9.4.2 Interprocessor Interrupts............................................................................................ 9-56
9.4.3 Message Interrupts..................................................................................................... 9-57
9.4.4 Shared Message Signaled Interrupts.......................................................................... 9-57
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9.4.5 PCI Express INTx...................................................................................................... 9-57
9.4.6 Global Timers ............................................................................................................9-58
9.4.7 Resets.........................................................................................................................9-58
9.4.8 Resetting the PIC ....................................................................................................... 9-59
9.4.8.1 Processor Core Resetting....................................................................................... 9-59
9.4.8.2 Processor Core Initialization..................................................................................9-59
9.5 Initialization/Application Information...........................................................................9-59
9.5.1 Programming Guidelines........................................................................................... 9-59
9.5.1.1 PIC Registers ......................................................................................................... 9-59
9.5.1.2 Changing Interrupt Source Configuration ............................................................. 9-61
Chapter 10
I
2
C Interfaces
10.1 Introduction....................................................................................................................10-1
10.1.1 Overview....................................................................................................................10-2
10.1.2 Features......................................................................................................................10-2
10.1.3 Modes of Operation ................................................................................................... 10-2
10.2 External Signal Descriptions ......................................................................................... 10-3
10.2.1 Signal Overview ........................................................................................................ 10-3
10.2.2 Detailed Signal Descriptions ..................................................................................... 10-3
10.3 Memory Map/Register Definition ................................................................................. 10-4
10.3.1 Register Descriptions................................................................................................. 10-5
10.3.1.1 I
2
C Address Register (I2CADR)........................................................................... 10-5
10.3.1.2 I
2
C Frequency Divider Register (I2CFDR)...........................................................10-6
10.3.1.3 I
2
C Control Register (I2CCR)............................................................................... 10-7
10.3.1.4 I
2
C Status Register (I2CSR).................................................................................. 10-9
10.3.1.5 I
2
C Data Register (I2CDR).................................................................................. 10-10
10.3.1.6 Digital Filter Sampling Rate Register (I2CDFSRR) ........................................... 10-11
10.4 Functional Description................................................................................................. 10-11
10.4.1 Transaction Protocol................................................................................................ 10-11
10.4.1.1 START Condition................................................................................................10-12
10.4.1.2 Slave Address Transmission................................................................................ 10-12
10.4.1.3 Repeated START Condition ................................................................................10-13
10.4.1.4 STOP Condition................................................................................................... 10-13
10.4.1.5 Protocol Implementation Details......................................................................... 10-13
10.4.1.5.1 Transaction Monitoring—Implementation Details.......................................... 10-14
10.4.1.5.2 Control Transfer—Implementation Details.....................................................10-14
10.4.1.6 Address Compare—Implementation Details....................................................... 10-15
10.4.2 Arbitration Procedure .............................................................................................. 10-15
10.4.2.1 Arbitration Control .............................................................................................. 10-15
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10.4.3 Handshaking ............................................................................................................ 10-16
10.4.4 Clock Control........................................................................................................... 10-16
10.4.4.1 Clock Synchronization......................................................................................... 10-16
10.4.4.2 Input Synchronization and Digital Filter............................................................. 10-16
10.4.4.2.1 Input Signal Synchronization ..........................................................................10-16
10.4.4.2.2 Filtering of SCL and SDA Lines ..................................................................... 10-17
10.4.4.3 Clock Stretching .................................................................................................. 10-17
10.4.5 Boot Sequencer Mode.............................................................................................. 10-17
10.4.5.1 EEPROM Calling Address .................................................................................. 10-18
10.4.5.2 EEPROM Data Format........................................................................................ 10-19
10.5 Initialization/Application Information.........................................................................10-21
10.5.1 Initialization Sequence.............................................................................................10-21
10.5.2 Generation of START.............................................................................................. 10-21
10.5.3 Post-Transfer Software Response............................................................................ 10-22
10.5.4 Generation of STOP................................................................................................. 10-22
10.5.5 Generation of Repeated START .............................................................................. 10-23
10.5.6 Generation of SCL When SDA Low....................................................................... 10-23
10.5.7 Slave Mode Interrupt Service Routine..................................................................... 10-23
10.5.7.1 Slave Transmitter and Received Acknowledge...................................................10-23
10.5.7.2 Loss of Arbitration and Forcing of Slave Mode.................................................. 10-24
10.5.8 Interrupt Service Routine Flowchart........................................................................ 10-24
Chapter 11
DUART
11.1 Overview........................................................................................................................ 11-1
11.1.1 Features...................................................................................................................... 11-1
11.1.2 Modes of Operation ................................................................................................... 11-2
11.1.2.1 DUART Signal Mode Selection ............................................................................ 11-3
11.2 External Signal Descriptions ......................................................................................... 11-3
11.2.1 Signal Overview ........................................................................................................ 11-3
11.2.2 Detailed Signal Descriptions ..................................................................................... 11-3
11.3 Memory Map/Register Definition ................................................................................. 11-4
11.3.1 Register Descriptions................................................................................................. 11-5
11.3.1.1 Receiver Buffer Registers (URBRn) (ULCR[DLAB] = 0)................................... 11-5
11.3.1.2 Transmitter Holding Registers (UTHRn) (ULCR[DLAB] = 0)............................ 11-5
11.3.1.3 Divisor Most and Least Significant Byte Registers (UDMB and UDLB)
(ULCR[DLAB] = 1).......................................................................................... 11-6
11.3.1.4 Interrupt Enable Register (UIER) (ULCR[DLAB] = 0)........................................ 11-8
11.3.1.5 Interrupt ID Registers (UIIRn) (ULCR[DLAB] = 0)............................................ 11-8
11.3.1.6 FIFO Control Registers (UFCRn) (ULCR[DLAB] = 0)..................................... 11-10
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11.3.1.7 Line Control Registers (ULCRn)..........................................................................11-11
11.3.1.8 Modem Control Registers (UMCRn) .................................................................. 11-13
11.3.1.9 Line Status Registers (ULSRn) ........................................................................... 11-14
11.3.1.10 Modem Status Registers (UMSRn) ..................................................................... 11-15
11.3.1.11 Scratch Registers (USCRn) ................................................................................. 11-16
11.3.1.12 Alternate Function Registers (UAFRn) (ULCR[DLAB] = 1)............................. 11-16
11.3.1.13 DMA Status Registers (UDSRn)......................................................................... 11-17
11.4 Functional Description................................................................................................. 11-18
11.4.1 Serial Interface......................................................................................................... 11-19
11.4.1.1 START Bit ........................................................................................................... 11-19
11.4.1.2 Data Transfer ....................................................................................................... 11-20
11.4.1.3 Parity Bit.............................................................................................................. 11-20
11.4.1.4 STOP Bit.............................................................................................................. 11-20
11.4.2 Baud-Rate Generator Logic..................................................................................... 11-20
11.4.3 Local Loopback Mode............................................................................................. 11-21
11.4.4 Errors ....................................................................................................................... 11-21
11.4.4.1 Framing Error ...................................................................................................... 11-21
11.4.4.2 Parity Error .......................................................................................................... 11-21
11.4.4.3 Overrun Error....................................................................................................... 11-21
11.4.5 FIFO Mode .............................................................................................................. 11-21
11.4.5.1 FIFO Interrupts.................................................................................................... 11-22
11.4.5.2 DMA Mode Select............................................................................................... 11-22
11.4.5.3 Interrupt Control Logic........................................................................................ 11-22
11.5 DUART Initialization/Application Information .......................................................... 11-23
Chapter 12
Local Bus Controller
12.1 Introduction....................................................................................................................12-1
12.1.1 Overview....................................................................................................................12-2
12.1.2 Features......................................................................................................................12-2
12.1.3 Modes of Operation ................................................................................................... 12-3
12.1.3.1 LBC Bus Clock and Clock Ratios ......................................................................... 12-3
12.1.3.2 Source ID Debug Mode......................................................................................... 12-4
12.1.4 Power-Down Mode.................................................................................................... 12-4
12.2 External Signal Descriptions ......................................................................................... 12-4
12.3 Memory Map/Register Definition ................................................................................. 12-8
12.3.1 Register Descriptions............................................................................................... 12-10
12.3.1.1 Base Registers (BR0–BR7) ................................................................................. 12-10
12.3.1.2 Option Registers (OR0–OR7).............................................................................. 12-12
12.3.1.2.1 Address Mask .................................................................................................. 12-12
/