NXP MPC8378E Reference guide

MPC8379E PowerQUICC™ II Pro

Integrated Host Processor

Family Reference Manual

Supports

MPC8379E

MPC8379

MPC8378E

MPC8378

MPC8377E

MPC8377

MPC8379ERM

Rev. 1

2/2009

Document Number: MPC8379ERM

Rev. 1, 2/2009

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MPC8379E PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1

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Contents

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Number Title

Page

Number

Co nt ents

About This Book

Audience.......................................................................................................................... ciii

Organization..................................................................................................................... ciii

Suggested Reading............................................................................................................cvi

General Information......................................................................................................cvi

Related Documentation.................................................................................................cvi

Conventions ......................................................................................................................cvi

Signal Conventions..........................................................................................................cvii

Acronyms and Abbreviations ........................................................................................ cviii

Chapter 1

Overview

1.1 MPC8379E Family Product Distinctions ........................................................................1-1

1.2 MPC8379E PowerQUICC II Pro Processor Overview ...................................................1-1

1.3 MPC8379E Architecture Overview................................................................................. 1-9

1.3.1 Power Architecture Core ............................................................................................. 1-9

1.3.2 Security Engine......................................................................................................... 1-12

1.3.3 Dual DDR Memory Controllers ................................................................................ 1-12

1.3.4 Dual Enhanced Three-Speed Ethernet Controllers.................................................... 1-13

1.3.5 Enhanced Secure Digital Host Controller (eSDHC).................................................. 1-14

1.3.6 SerDes PHY............................................................................................................... 1-14

1.3.7 PCI Controller............................................................................................................ 1-15

1.3.7.1 PCI Bus Arbitration Unit...................................................................................... 1-15

1.3.8 Universal Serial Bus (USB) 2.0................................................................................. 1-16

1.3.8.1 USB Dual-Role Controller .................................................................................... 1-17

1.3.9 Enhanced Local Bus Controller (eLBC).................................................................... 1-17

1.3.10 Integrated Programmable Interrupt Controller (IPIC)...............................................1-19

1.3.11 Dual I

2

C Interfaces .................................................................................................... 1-19

1.3.12 DMA Controller......................................................................................................... 1-20

1.3.13 Dual Universal Asynchronous Receiver/Transmitter (DUART)...............................1-21

1.3.14 Serial Peripheral Interface (SPI)................................................................................ 1-21

1.3.15 System Timers ........................................................................................................... 1-22

1.4 Applications...................................................................................................................1-22

Chapter 2

Memory Map

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2.1 Internal Memory Mapped Registers ................................................................................ 2-1

2.2 Accessing IMMR Memory From the Local Processor.................................................... 2-1

2.3 IMMR Address Map........................................................................................................ 2-1

Chapter 3

Signal Descriptions

3.1 Signals Overview.............................................................................................................3-1

3.2 Configuration Signals Sampled at Reset ....................................................................... 3-30

3.3 Output Signal States During Reset ................................................................................ 3-30

Chapter 4

Reset, Clocking, and Initialization

4.1 External Signals ...............................................................................................................4-1

4.1.1 Reset Signals................................................................................................................4-1

4.1.2 Clock Signals............................................................................................................... 4-3

4.2 Functional Description..................................................................................................... 4-4

4.2.1 Reset Operations.......................................................................................................... 4-4

4.2.1.1 Reset Causes............................................................................................................ 4-4

4.2.1.2 Reset Actions........................................................................................................... 4-5

4.2.2 Power-On Reset Flow.................................................................................................. 4-6

4.2.3 Hard Reset Flow .......................................................................................................... 4-8

4.2.4 Soft Reset Flow............................................................................................................4-9

4.3 Reset Configuration......................................................................................................... 4-9

4.3.1 Reset Configuration Signals ...................................................................................... 4-10

4.3.1.1 Reset Configuration Word Source......................................................................... 4-10

4.3.1.2 CLKIN Division .................................................................................................... 4-11

4.3.1.3 LBMUX Configuration ......................................................................................... 4-11

4.3.1.4 Selecting Reset Configuration Input Signals......................................................... 4-11

4.3.2 Reset Configuration Words........................................................................................ 4-12

4.3.2.1 Reset Configuration Word Low Register (RCWLR)............................................. 4-13

4.3.2.1.1 System PLL VCO Division............................................................................... 4-14

4.3.2.1.2 System PLL Configuration................................................................................ 4-15

4.3.2.2 Reset Configuration Word High Register (RCWHR)............................................ 4-16

4.3.2.2.1 PCI Host/Agent Configuration.......................................................................... 4-18

4.3.2.2.2 Boot Memory Space (BMS).............................................................................. 4-18

4.3.2.2.3 Boot Sequencer Configuration .......................................................................... 4-19

4.3.2.2.4 Boot ROM Location .......................................................................................... 4-19

4.3.2.2.5 Boot from SPI.................................................................................................... 4-20

4.3.2.2.6 eTSEC1 Mode ................................................................................................... 4-21

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4.3.2.2.7 eTSEC2 Mode ................................................................................................... 4-22

4.3.2.2.8 e300 Core True Little-Endian............................................................................ 4-22

4.3.2.2.9 LDP Configuration ............................................................................................ 4-23

4.3.3 Loading the Reset Configuration Words ................................................................... 4-23

4.3.3.1 Loading from Local Bus........................................................................................ 4-23

4.3.3.1.1 Local Bus Controller Setting.............................................................................4-24

4.3.3.2 Loading from I2C EEPROM................................................................................. 4-25

4.3.3.2.1 Using the Boot Sequencer Reset Configuration................................................4-26

4.3.3.2.2 EEPROM Calling Address................................................................................ 4-26

4.3.3.2.3 EEPROM Data Format in Reset Configuration Mode...................................... 4-26

4.3.3.2.4 Reset Configuration Load Fail .......................................................................... 4-29

4.3.3.3 Default Reset Configuration Words....................................................................... 4-29

4.3.3.3.1 Examples for Hard-Coded Reset Configuration Words Usage .........................4-31

4.4 Clocking ........................................................................................................................4-32

4.4.1 Clocking in PCI Host Mode....................................................................................... 4-32

4.4.1.1 PCI Clock Outputs (PCI_CLK_OUT[0:4])...........................................................4-33

4.4.2 Clocking In PCI Agent Mode.................................................................................... 4-33

4.4.3 System Clock Domains.............................................................................................. 4-33

4.5 Memory Map/Register Definitions................................................................................ 4-34

4.5.1 Reset Configuration Register Descriptions................................................................ 4-34

4.5.1.1 Reset Configuration Word Low Register (RCWLR)............................................. 4-35

4.5.1.2 Reset Configuration Word High Register (RCWHR)............................................ 4-35

4.5.1.3 Reset Status Register (RSR) .................................................................................. 4-35

4.5.1.4 Reset Mode Register (RMR) ................................................................................. 4-37

4.5.1.5 Reset Protection Register (RPR) ........................................................................... 4-37

4.5.1.6 Reset Control Register (RCR) ............................................................................... 4-38

4.5.1.7 Reset Control Enable Register (RCER)................................................................. 4-39

4.5.2 Clock Configuration Registers................................................................................... 4-39

4.5.2.1 System PLL Mode Register (SPMR) .................................................................... 4-39

4.5.2.2 Output Clock Control Register (OCCR)................................................................ 4-41

4.5.2.3 System Clock Control Register (SCCR)................................................................ 4-42

Chapter 5

System Configuration

5.1 Introduction...................................................................................................................... 5-1

5.2 Local Memory Map Overview and Example .................................................................. 5-1

5.2.1 Address Translation and Mapping............................................................................... 5-3

5.2.2 Window into Configuration Space............................................................................... 5-4

5.2.3 Local Access Windows................................................................................................ 5-4

5.2.3.1 Local Access Register Memory Map ...................................................................... 5-5

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5.2.4 Local Access Register Descriptions ............................................................................ 5-6

5.2.4.1 Internal Memory Map Registers Base Address Register (IMMRBAR).................. 5-6

5.2.4.1.1 Updating IMMRBAR.......................................................................................... 5-6

5.2.4.1.2 IMMRBAR[BASE_ADDR] Reset Value............................................................ 5-7

5.2.4.2 Alternate Configuration Base Address Register (ALTCBAR)................................5-8

5.2.4.3 LBC Local Access Window n Base Address Registers

(LBLAWBAR0–LBLAWBAR3) ........................................................................ 5-9

5.2.4.3.1 LBLAWBAR0[BASE_ADDR] Reset Value.......................................................5-9

5.2.4.4 LBC Local Access Window n Attributes Registers (LBLAWAR0–LBLAWAR3)5-10

5.2.4.4.1 LBLAWAR0[EN] and LBLAWAR0[SIZE] Reset Value ..................................5-10

5.2.4.5 PCI Local Access Window n Base Address Register

(PCILAWBAR0–PCILAWBAR1).................................................................... 5-11

5.2.4.5.1 PCILAWBAR0[BASE_ADDR] Reset Value.................................................... 5-11

5.2.4.6 PCI Local Access Window n Attributes Registers

(PCILAWAR0–PCILAWAR1) .......................................................................... 5-12

5.2.4.6.1 PCILAWAR0[EN] and PCILAWAR0[SIZE] Reset Value................................5-12

5.2.4.7 PCI Express 1 Local Access Window Base Address Register

(PCIEXP1LAWBAR)........................................................................................ 5-13

5.2.4.8 PCI Express 1 Local Access Window Attributes Registers (PCIEXP1LAWAR). 5-13

5.2.4.9 PCI Express 2 Local Access Window Base Address Register (PCIEXP2LAWBAR)..

5-14

5.2.4.10 PCI Express 2 Local Access Window Attributes Registers (PCIEXP2LAWAR). 5-15

5.2.4.11 DDR Local Access Window n Base Address Registers

(DDRLAWBAR0–DDRLAWBAR1)................................................................ 5-15

5.2.4.11.1 DDRLAWBAR0[BASE_ADDR] Reset Value.................................................. 5-16

5.2.4.12 DDR Local Access Window n Attributes Registers (DDRLAWAR0–DDRLAWAR1)

5-16

5.2.4.12.1 DDRLAWAR0[EN] and DDRLAWAR0[SIZE] Reset Value............................5-17

5.2.5 Precedence of Local Access Windows...................................................................... 5-17

5.2.6 Configuring Local Access Windows ......................................................................... 5-18

5.2.7 Distinguishing Local Access Windows from Other Mapping Functions.................. 5-18

5.2.8 Outbound Address Translation and Mapping Windows............................................ 5-18

5.2.9 Inbound Address Translation and Mapping Windows .............................................. 5-18

5.2.9.1 PCI Inbound Windows........................................................................................... 5-19

5.2.10 Internal Memory Map................................................................................................ 5-19

5.2.11 Accessing Internal Memory from External Masters.................................................. 5-19

5.3 System Configuration .................................................................................................... 5-19

5.3.1 System Configuration Register Memory Map...........................................................5-20

5.3.2 System Configuration Registers ................................................................................ 5-20

5.3.2.1 System General Purpose Register Low (SGPRL) ................................................. 5-20

5.3.2.2 System General Purpose Register High (SGPRH)................................................5-21

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5.3.2.3 System Part and Revision ID Register (SPRIDR).................................................5-21

5.3.2.3.1 SPRIDR[PARTID] Coding................................................................................ 5-22

5.3.2.4 System Priority and Configuration Register (SPCR) ............................................ 5-22

5.3.2.5 System I/O Configuration Register Low (SICRL)................................................5-24

5.3.2.6 System I/O Configuration Register High (SICRH)............................................... 5-28

5.3.2.7 Debug Configuration .............................................................................................5-30

5.3.2.7.1 DDR Debug Configuration................................................................................5-30

5.3.2.7.2 Local Bus Debug Configuration........................................................................5-30

5.3.2.8 DDR Control Driver Register (DDRCDR)............................................................ 5-31

5.3.2.9 DDR Debug Status Register (DDRDSR) .............................................................. 5-33

5.3.2.10 Output Buffer Impedance Register (OBIR)...........................................................5-34

5.3.2.11 PCI Express Control Registers (PECR1 and PECR2)........................................... 5-34

5.4 Software Watchdog Timer (WDT)................................................................................. 5-36

5.4.1 WDT Overview.......................................................................................................... 5-36

5.4.2 WDT Features............................................................................................................ 5-37

5.4.3 WDT Modes of Operation......................................................................................... 5-37

5.4.4 WDT Memory Map/Register Definition ................................................................... 5-37

5.4.4.1 System Watchdog Control Register (SWCRR) .....................................................5-38

5.4.4.2 System Watchdog Count Register (SWCNR) .......................................................5-39

5.4.4.3 System Watchdog Service Register (SWSRR)...................................................... 5-39

5.4.5 Functional Description............................................................................................... 5-40

5.4.5.1 Software Watchdog Timer Unit............................................................................. 5-40

5.4.5.2 Modes of Operation............................................................................................... 5-42

5.4.6 Initialization/Application Information.......................................................................5-42

5.4.6.1 WDT Programming Guidelines............................................................................. 5-42

5.5 Real Time Clock Module (RTC).................................................................................... 5-43

5.5.1 RTC Overview........................................................................................................... 5-43

5.5.2 RTC Features ............................................................................................................. 5-43

5.5.3 RTC Modes of Operation........................................................................................... 5-44

5.5.4 RTC External Signal Description .............................................................................. 5-44

5.5.5 RTC Memory Map/Register Definition.....................................................................5-44

5.5.5.1 Real Time Counter Control Register (RTCNR) .................................................... 5-45

5.5.5.2 Real Time Counter Load Register (RTLDR).........................................................5-46

5.5.5.3 Real Time Counter Prescale Register (RTPSR) .................................................... 5-46

5.5.5.4 Real Time Counter Register (RTCTR).................................................................. 5-47

5.5.5.5 Real Time Counter Event Register (RTEVR)........................................................ 5-47

5.5.5.6 Real Time Counter Alarm Register (RTALR).......................................................5-48

5.5.6 Functional Description............................................................................................... 5-48

5.5.6.1 Real Time Counter Unit......................................................................................... 5-48

5.5.6.2 RTC Operational Modes........................................................................................ 5-49

5.5.7 RTC Programming Guidelines................................................................................... 5-50

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5.6 Periodic Interval Timer (PIT) ........................................................................................ 5-50

5.6.1 PIT Overview............................................................................................................. 5-50

5.6.2 PIT Features...............................................................................................................5-51

5.6.3 PIT Modes of Operation ............................................................................................ 5-51

5.6.4 PIT External Signal Description................................................................................ 5-51

5.6.5 PIT Memory Map/Register Definition ......................................................................5-52

5.6.5.1 Periodic Interval Timer Control Register (PTCNR)..............................................5-52

5.6.5.2 Periodic Interval Timer Load Register (PTLDR) ..................................................5-53

5.6.5.3 Periodic Interval Timer Prescale Register (PTPSR).............................................. 5-54

5.6.5.4 Periodic Interval Timer Counter Register (PTCTR).............................................. 5-54

5.6.5.5 Periodic Interval Timer Event Register (PTEVR) ................................................. 5-55

5.6.6 Functional Description............................................................................................... 5-55

5.6.6.1 Periodic Interval Timer Unit.................................................................................. 5-55

5.6.6.2 PIT Operational Modes.......................................................................................... 5-56

5.6.7 PIT Programming Guidelines.................................................................................... 5-56

5.7 General-Purpose Timers (GTMs)................................................................................... 5-57

5.7.1 GTM Overview.......................................................................................................... 5-57

5.7.2 GTM Features ............................................................................................................ 5-58

5.7.3 GTM Modes of Operation.......................................................................................... 5-58

5.7.3.1 Cascaded Modes.................................................................................................... 5-58

5.7.3.2 Clock Source Modes.............................................................................................. 5-59

5.7.3.3 Reference Modes ................................................................................................... 5-59

5.7.3.4 Capture Modes....................................................................................................... 5-59

5.7.4 GTM External Signal Description ............................................................................. 5-59

5.7.5 GTM Memory Map/Register Definition.................................................................... 5-61

5.7.5.1 Global Timers Configuration Registers (GTCFRn)............................................... 5-62

5.7.5.2 Global Timers Mode Registers (GTMDR1–GTMDR4)........................................ 5-66

5.7.5.3 Global Timers Reference Registers (GTRFR1–GTRFR4) .................................... 5-67

5.7.5.4 Global Timers Capture Registers (GTCPR1–GTCPR4)........................................ 5-67

5.7.5.5 Global Timers Counter Registers (GTCNR1–GTCNR4) ...................................... 5-68

5.7.5.6 Global Timers Event Registers (GTEVR1–GTEVR4) .......................................... 5-68

5.7.5.7 Global Timers Prescale Registers (GTPSR1–GTPSR4)........................................ 5-69

5.7.6 Functional Description............................................................................................... 5-70

5.7.6.1 General-Purpose Timer Units................................................................................ 5-70

5.7.6.2 Reference Modes ................................................................................................... 5-70

5.7.6.3 Capture Modes....................................................................................................... 5-70

5.7.6.4 Cascaded Modes.................................................................................................... 5-71

5.7.7 Initialization/Application Information.......................................................................5-73

5.7.7.1 GTM Register Programming Guidelines ............................................................... 5-73

5.8 Power Management Control (PMC).............................................................................. 5-73

5.8.1 External Signal Description....................................................................................... 5-74

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5.8.2 PMC Memory Map/Register Definition.................................................................... 5-74

5.8.2.1 Power Management Controller Configuration Register (PMCCR)....................... 5-74

5.8.2.2 Power Management Controller Event Register (PMCER)....................................5-75

5.8.2.3 Power Management Controller Mask Register (PMCMR) ................................... 5-77

5.8.2.4 Power Management Controller Configuration Register 1 (PMCCR1)..................5-78

5.8.3 Functional Description............................................................................................... 5-79

5.8.3.1 Dynamic Power Management................................................................................ 5-80

5.8.3.2 Shutting Down Unused Blocks.............................................................................. 5-80

5.8.3.3 Software-Controlled Power-Down States.............................................................. 5-80

5.8.3.4 Support of PCI Power Management Interface Specification.................................5-80

5.8.3.4.1 Entering Low Power States—Core-Only Mode................................................ 5-81

5.8.3.4.2 Entering Low Power States—Core and System Mode...................................... 5-82

5.8.3.5 Exiting Core and System Low Power States.........................................................5-82

5.8.3.5.1 Exiting Low Power States—Core-Only Mode.................................................. 5-82

5.8.3.5.2 Exiting Low Power States—Core and System Mode........................................ 5-82

5.8.4 Initialization/Application Information.......................................................................5-83

5.8.4.1 Core Disable in Low Power Mode ........................................................................ 5-83

Chapter 6

Arbiter and Bus Monitor

6.1 Overview.......................................................................................................................... 6-1

6.1.1 Coherent System Bus Overview.................................................................................. 6-1

6.2 Arbiter Memory Map/Register Definition....................................................................... 6-2

6.2.1 Arbiter Configuration Register (ACR)........................................................................ 6-2

6.2.2 Arbiter Timers Register (ATR).................................................................................... 6-4

6.2.3 Arbiter Event Register (AER)...................................................................................... 6-5

6.2.4 Arbiter Interrupt Definition Register (AIDR).............................................................. 6-6

6.2.5 Arbiter Mask Register (AMR)..................................................................................... 6-7

6.2.6 Arbiter Event Attributes Register (AEATR)................................................................ 6-8

6.2.7 Arbiter Event Address Register (AEADR).................................................................. 6-9

6.2.8 Arbiter Event Response Register (AERR)................................................................. 6-10

6.3 Functional Description................................................................................................... 6-11

6.3.1 Arbitration Policy ...................................................................................................... 6-11

6.3.1.1 Address Bus Arbitration with PRIORITY[0:1]..................................................... 6-12

6.3.1.2 Address Bus Arbitration with REPEAT

................................................................ 6-13

6.3.1.3 Address Bus Arbitration after ARTRY

.................................................................. 6-14

6.3.1.4 Address Bus Parking.............................................................................................. 6-14

6.3.1.5 Data Bus Arbitration.............................................................................................. 6-14

6.3.2 Bus Error Detection ................................................................................................... 6-14

6.3.2.1 Address Time Out.................................................................................................. 6-14

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6.3.2.2 Data Time Out ....................................................................................................... 6-15

6.3.2.3 Transfer Error ........................................................................................................ 6-15

6.3.2.4 Address Only Transaction Type............................................................................. 6-15

6.3.2.5 Reserved Transaction Type.................................................................................... 6-16

6.3.2.6 Illegal (eciwx/ecowx) Transaction Type................................................................ 6-16

6.4 Initialization/Applications Information ......................................................................... 6-17

6.4.1 Initialization Sequence...............................................................................................6-17

6.4.2 Error Handling Sequence........................................................................................... 6-17

Chapter 7

e300 Processor Core Overview

7.1 Overview.......................................................................................................................... 7-1

7.1.1 Features........................................................................................................................ 7-3

7.1.2 Instruction Unit............................................................................................................ 7-6

7.1.2.1 Instruction Queue and Dispatch Unit ...................................................................... 7-6

7.1.2.2 Branch Processing Unit (BPU)................................................................................ 7-7

7.1.3 Independent Execution Units....................................................................................... 7-7

7.1.3.1 Integer Unit (IU)...................................................................................................... 7-7

7.1.3.2 Floating-Point Unit (FPU)....................................................................................... 7-7

7.1.3.3 Load/Store Unit (LSU) ............................................................................................ 7-8

7.1.3.4 System Register Unit (SRU).................................................................................... 7-8

7.1.4 Completion Unit .......................................................................................................... 7-8

7.1.5 Memory Subsystem Support........................................................................................ 7-9

7.1.5.1 Memory Management Units (MMUs)..................................................................... 7-9

7.1.5.2 Cache Units............................................................................................................ 7-10

7.1.6 Bus Interface Unit (BIU) ........................................................................................... 7-10

7.1.7 System Support Functions......................................................................................... 7-11

7.1.7.1 Power Management ............................................................................................... 7-11

7.1.7.2 Time Base/Decrementer ........................................................................................ 7-12

7.1.7.3 JTAG Test and Debug Interface............................................................................. 7-12

7.1.7.4 Clock Multiplier.................................................................................................... 7-12

7.1.7.5 Core Performance Monitor.................................................................................... 7-12

7.2 e300 Processor and System Version Numbers............................................................... 7-13

7.3 PowerPC Architecture Implementation......................................................................... 7-13

7.4 Implementation-Specific Information............................................................................ 7-14

7.4.1 Register Model........................................................................................................... 7-14

7.4.1.1 UISA Registers...................................................................................................... 7-17

7.4.1.1.1 General-Purpose Registers (GPRs) ................................................................... 7-17

7.4.1.1.2 Floating-Point Registers (FPRs)........................................................................ 7-17

7.4.1.1.3 Condition Register (CR).................................................................................... 7-17

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7.4.1.1.4 Floating-Point Status and Control Register (FPSCR) .......................................7-17

7.4.1.1.5 User-Level SPRs................................................................................................ 7-17

7.4.1.2 VEA Registers ....................................................................................................... 7-18

7.4.1.3 OEA Registers ....................................................................................................... 7-18

7.4.1.3.1 Machine State Register (MSR).......................................................................... 7-18

7.4.1.3.2 Segment Registers (SRs) ................................................................................... 7-20

7.4.1.3.3 Supervisor-Level SPRs...................................................................................... 7-20

7.4.2 Instruction Set and Addressing Modes...................................................................... 7-27

7.4.2.1 PowerPC Instruction Set and Addressing Modes.................................................. 7-27

7.4.2.2 Implementation-Specific Instruction Set ............................................................... 7-28

7.4.3 Cache Implementation............................................................................................... 7-29

7.4.3.1 PowerPC Cache Characteristics ............................................................................ 7-29

7.4.3.2 Implementation-Specific Cache Organization....................................................... 7-29

7.4.3.3 Instruction and Data Cache Way-Locking............................................................. 7-31

7.4.4 Interrupt Model.......................................................................................................... 7-31

7.4.4.1 PowerPC Interrupt Model...................................................................................... 7-31

7.4.4.2 Implementation-Specific Interrupt Model ............................................................. 7-32

7.4.5 Memory Management................................................................................................ 7-35

7.4.5.1 PowerPC Memory Management............................................................................ 7-35

7.4.5.2 Implementation-Specific Memory Management...................................................7-35

7.4.6 Instruction Timing ..................................................................................................... 7-36

7.4.7 Core Interface ............................................................................................................ 7-37

7.4.7.1 Memory Accesses................................................................................................. 7-38

7.4.7.2 Signals....................................................................................................................7-38

7.4.8 Debug Features ......................................................................................................... 7-39

7.4.8.1 Breakpoint Signaling.............................................................................................7-39

7.5 Differences Between Cores........................................................................................... 7-40

Chapter 8

Integrated Programmable Interrupt Controller (IPIC)

8.1 Introduction...................................................................................................................... 8-1

8.2 Features............................................................................................................................ 8-4

8.3 Modes of Operation ......................................................................................................... 8-4

8.3.1 Core Enable Mode ....................................................................................................... 8-4

8.3.2 Core Disable Mode...................................................................................................... 8-5

8.4 External Signal Description............................................................................................. 8-5

8.4.1 Overview......................................................................................................................8-5

8.4.2 Detailed Signal Descriptions ....................................................................................... 8-5

8.5 Memory Map/Register Definition ................................................................................... 8-6

8.5.1 System Global Interrupt Configuration Register (SICFR).......................................... 8-7

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8.5.2 System Global Interrupt Vector Register (SIVCR)......................................................8-9

8.5.3 System Internal Interrupt Pending Registers (SIPNR_H and SIPNR_L).................. 8-11

8.5.4 System Internal Interrupt Group A Priority Register (SIPRR_A).............................8-14

8.5.5 System Internal Interrupt Group B Priority Register (SIPRR_B) ............................. 8-15

8.5.6 System Internal Interrupt Group C Priority Register (SIPRR_C) ............................. 8-16

8.5.7 System Internal Interrupt Group D Priority Register (SIPRR_D).............................8-17

8.5.8 System Internal Interrupt Mask Register (SIMSR_H and SIMSR_L) ...................... 8-18

8.5.9 System Internal Interrupt Control Register (SICNR)................................................8-19

8.5.10 System External Interrupt Pending Register (SEPNR)..............................................8-21

8.5.11 System Mixed Interrupt Group A Priority Register (SMPRR_A)............................. 8-21

8.5.12 System Mixed Interrupt Group B Priority Register (SMPRR_B)............................. 8-22

8.5.13 System External Interrupt Mask Register (SEMSR)................................................. 8-23

8.5.14 System External Interrupt Control Register (SECNR)..............................................8-24

8.5.15 System Error Status Register (SERSR) ..................................................................... 8-25

8.5.16 System Error Mask Register (SERMR)..................................................................... 8-26

8.5.17 System Error Control Register (SERCR) .................................................................. 8-27

8.5.18 System External interrupt Polarity Control Register (SEPCR).................................8-28

8.5.19 System Internal Interrupt Force Registers (SIFCR_H and SIFCR_L) ...................... 8-29

8.5.20 System External Interrupt Force Register (SEFCR).................................................. 8-30

8.5.21 System Error Force Register (SERFR)...................................................................... 8-30

8.5.22 System Critical Interrupt Vector Register (SCVCR)................................................. 8-31

8.5.23 System Management Interrupt Vector Register (SMVCR) ....................................... 8-31

8.6 Functional Description................................................................................................... 8-32

8.6.1 Interrupt Types........................................................................................................... 8-32

8.6.2 Interrupt Configuration.............................................................................................. 8-33

8.6.3 Internal Interrupts Group Relative Priority................................................................ 8-34

8.6.4 Mixed Interrupts Group Relative Priority..................................................................8-34

8.6.5 Highest Priority Interrupt........................................................................................... 8-35

8.6.6 Interrupt Source Priorities.......................................................................................... 8-35

8.6.7 Masking Interrupt Sources......................................................................................... 8-39

8.6.8 Interrupt Vector Generation and Calculation............................................................. 8-40

8.6.9 Machine Check Interrupts.......................................................................................... 8-40

8.7 Message Shared Interrupts............................................................................................. 8-41

8.7.1 Memory Map/Register Definition ............................................................................. 8-41

8.7.2 Message Shared Registers ......................................................................................... 8-42

8.7.2.1 Message Shared Interrupt Register (MSIRs)......................................................... 8-42

8.7.2.2 Message Shared Interrupt Mask Register (MSIMR).............................................8-42

8.7.2.3 Message Shared Interrupt Status Register (MSISR)..............................................8-43

8.7.2.4 Message Shared Interrupt Index Register (MSIIR)...............................................8-44

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Chapter 9

DDR Memory Controller

9.1 Introduction...................................................................................................................... 9-1

9.2 Features............................................................................................................................ 9-2

9.2.1 Modes of Operation ..................................................................................................... 9-3

9.3 External Signal Descriptions ........................................................................................... 9-3

9.3.1 Signals Overview......................................................................................................... 9-3

9.3.2 Detailed Signal Descriptions ....................................................................................... 9-5

9.3.2.1 Memory Interface Signals........................................................................................ 9-5

9.3.2.2 Clock Interface Signals............................................................................................ 9-8

9.3.2.3 Debug Signals.......................................................................................................... 9-8

9.4 Memory Map/Register Definition ................................................................................... 9-8

9.4.1 Register Descriptions................................................................................................. 9-10

9.4.1.1 Chip Select Memory Bounds (CSn_BNDS)..........................................................9-10

9.4.1.2 Chip Select Configuration (CSn_CONFIG)..........................................................9-10

9.4.1.3 DDR SDRAM Timing Configuration 3 (TIMING_CFG_3).................................9-12

9.4.1.4 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0).................................9-13

9.4.1.5 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1).................................9-15

9.4.1.6 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2).................................9-17

9.4.1.7 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-19

9.4.1.8 DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)...................... 9-22

9.4.1.9 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................9-24

9.4.1.10 DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)..................... 9-25

9.4.1.11 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL).................9-25

9.4.1.12 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 9-28

9.4.1.13 DDR SDRAM Data Initialization (DDR_DATA_INIT).......................................9-28

9.4.1.14 DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL).............................9-29

9.4.1.15 DDR Initialization Address (DDR_INIT_ADDR)................................................ 9-29

9.4.1.16 DDR IP Block Revision 1 (DDR_IP_REV1)........................................................9-30

9.4.1.17 DDR IP Block Revision 2 (DDR_IP_REV2)........................................................9-30

9.4.1.18 Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI)........ 9-31

9.4.1.19 Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)........ 9-31

9.4.1.20 Memory Data Path Error Injection Mask ECC (ERR_INJECT)...........................9-32

9.4.1.21 Memory Data Path Read Capture High (CAPTURE_DATA_HI)......................... 9-32

9.4.1.22 Memory Data Path Read Capture Low (CAPTURE_DATA_LO) ........................9-33

9.4.1.23 Memory Data Path Read Capture ECC (CAPTURE_ECC)..................................9-33

9.4.1.24 Memory Error Detect (ERR_DETECT)................................................................ 9-33

9.4.1.25 Memory Error Disable (ERR_DISABLE)............................................................. 9-34

9.4.1.26 Memory Error Interrupt Enable (ERR_INT_EN).................................................. 9-35

9.4.1.27 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES).......................... 9-36

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9.4.1.28 Memory Error Address Capture (CAPTURE_ADDRESS) .................................. 9-37

9.4.1.29 Single-Bit ECC Memory Error Management (ERR_SBE)...................................9-37

9.5 Functional Description................................................................................................... 9-38

9.5.1 DDR SDRAM Interface Operation............................................................................ 9-43

9.5.1.1 Supported DDR SDRAM Organizations............................................................... 9-43

9.5.2 DDR SDRAM Address Multiplexing........................................................................ 9-45

9.5.3 JEDEC Standard DDR SDRAM Interface Commands .............................................9-50

9.5.4 DDR SDRAM Interface Timing................................................................................ 9-51

9.5.4.1 Clock Distribution ................................................................................................. 9-55

9.5.5 DDR SDRAM Mode-Set Command Timing.............................................................9-55

9.5.6 DDR SDRAM Registered DIMM Mode................................................................... 9-56

9.5.7 DDR SDRAM Write Timing Adjustments................................................................ 9-57

9.5.8 DDR SDRAM Refresh .............................................................................................. 9-58

9.5.8.1 DDR SDRAM Refresh Timing.............................................................................. 9-59

9.5.8.2 DDR SDRAM Refresh and Power-Saving Modes................................................ 9-59

9.5.8.2.1 Self-Refresh in Sleep Mode............................................................................... 9-60

9.5.9 DDR Data Beat Ordering........................................................................................... 9-62

9.5.10 Page Mode and Logical Bank Retention ................................................................... 9-62

9.5.11 Error Checking and Correcting (ECC) ...................................................................... 9-63

9.5.12 Error Management..................................................................................................... 9-65

9.6 Initialization/Application Information...........................................................................9-66

9.6.1 Programming Differences Between Memory Types.................................................. 9-67

9.6.2 DDR SDRAM Initialization Sequence...................................................................... 9-70

9.6.3 Using Forced Self-Refresh Mode to Implement a Battery-Backed

RAM System ......................................................................................................... 9-70

9.6.3.1 Hardware Based Self-Refresh................................................................................ 9-70

9.6.3.2 Software Based Self-Refresh................................................................................. 9-71

9.6.3.3 Bypassing Re-initialization During Battery-Backed Operation............................9-71

Chapter 10

Enhanced Local Bus Controller

10.1 Introduction....................................................................................................................10-1

10.1.1 Overview....................................................................................................................10-2

10.1.2 Features......................................................................................................................10-2

10.1.3 Modes of Operation ................................................................................................... 10-3

10.1.3.1 eLBC Bus Clock and Clock Ratios ....................................................................... 10-3

10.1.3.2 Source ID Debug Mode......................................................................................... 10-4

10.2 External Signal Descriptions ......................................................................................... 10-4

10.3 Memory Map/Register Definition ................................................................................. 10-9

10.3.1 Register Descriptions............................................................................................... 10-10

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10.3.1.1 Base Registers (BR0–BR7) ................................................................................. 10-11

10.3.1.2 Option Registers (OR0–OR7).............................................................................. 10-12

10.3.1.2.1 Address Mask .................................................................................................. 10-13

10.3.1.2.2 Option Registers (ORn)—GPCM Mode .........................................................10-14

10.3.1.2.3 Option Registers (ORn)—FCM Mode ............................................................ 10-16

10.3.1.2.4 Option Registers (ORn)—UPM Mode............................................................ 10-19

10.3.1.3 UPM Memory Address Register (MAR)............................................................. 10-20

10.3.1.4 UPM Mode Registers (MxMR)........................................................................... 10-21

10.3.1.5 Memory Refresh Timer Prescaler Register (MRTPR) ........................................10-23

10.3.1.6 UPM/FCM Data Register (MDR) ....................................................................... 10-23

10.3.1.7 Special Operation Initiation Register (LSOR).....................................................10-24

10.3.1.8 UPM Refresh Timer (LURT)............................................................................... 10-25

10.3.1.9 Transfer Error Status Register (LTESR).............................................................. 10-26

10.3.1.10 Transfer Error Check Disable Register (LTEDR)................................................10-28

10.3.1.11 Transfer Error Interrupt Enable Register (LTEIR) .............................................. 10-29

10.3.1.12 Transfer Error Attributes Register (LTEATR).....................................................10-30

10.3.1.13 Transfer Error Address Register (LTEAR)..........................................................10-31

10.3.1.14 Local Bus Configuration Register (LBCR).........................................................10-31

10.3.1.15 Clock Ratio Register (LCRR).............................................................................. 10-33

10.3.1.16 Flash Mode Register (FMR)................................................................................ 10-34

10.3.1.17 Flash Instruction Register (FIR).......................................................................... 10-36

10.3.1.18 Flash Command Register (FCR) ......................................................................... 10-37

10.3.1.19 Flash Block Address Register (FBAR)................................................................ 10-38

10.3.1.20 Flash Page Address Register (FPAR).................................................................. 10-38

10.3.1.21 Flash Byte Count Register (FBCR).....................................................................10-40

10.4 Functional Description................................................................................................. 10-40

10.4.1 Basic Architecture.................................................................................................... 10-41

10.4.1.1 Address and Address Space Checking ................................................................ 10-41

10.4.1.2 External Address Latch Enable Signal (LALE) .................................................. 10-42

10.4.1.3 Data Transfer Acknowledge (TA) ....................................................................... 10-43

10.4.1.4 Data Buffer Control (LBCTL)............................................................................. 10-44

10.4.1.5 Parity Generation and Checking (LDP)............................................................... 10-44

10.4.1.6 Bus Monitor......................................................................................................... 10-44

10.4.1.7 PLL Bypass Mode ............................................................................................... 10-45

10.4.2 General-Purpose Chip-Select Machine (GPCM).....................................................10-46

10.4.2.1 GPCM Read Signal Timing................................................................................. 10-47

10.4.2.2 GPCM Write Signal Timing................................................................................10-49

10.4.2.3 Chip-Select Assertion Timing .............................................................................10-50

10.4.2.3.1 Programmable Wait State Configuration......................................................... 10-51

10.4.2.3.2 Chip-Select and Write Enable Negation Timing.............................................10-51

10.4.2.3.3 Relaxed Timing ............................................................................................... 10-52

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10.4.2.3.4 Output Enable (LOE) Timing..........................................................................10-55

10.4.2.3.5 Extended Hold Time on Read Accesses..........................................................10-55

10.4.2.4 External Access Termination (LGTA) ................................................................. 10-56

10.4.2.5 GPCM Boot Chip-Select Operation .................................................................... 10-57

10.4.3 Flash Control Machine (FCM) ................................................................................ 10-58

10.4.3.1 FCM Buffer RAM ............................................................................................... 10-60

10.4.3.1.1 Buffer Layout and Page Mapping for Small-Page NAND Flash Devices ...... 10-61

10.4.3.1.2 Buffer Layout and Page Mapping for Large-Page NAND Flash Devices ...... 10-62

10.4.3.1.3 Error Correcting Codes and the Spare Region ................................................ 10-63

10.4.3.2 Programming FCM.............................................................................................. 10-65

10.4.3.2.1 FCM Command Instructions ........................................................................... 10-66

10.4.3.2.2 FCM No-Operation Instruction ....................................................................... 10-66

10.4.3.2.3 FCM Address Instructions............................................................................... 10-66

10.4.3.2.4 FCM Data Read Instructions ........................................................................... 10-67

10.4.3.2.5 FCM Data Write Instructions .......................................................................... 10-67

10.4.3.3 FCM Signal Timing............................................................................................. 10-68

10.4.3.3.1 FCM Chip-Select Timing................................................................................ 10-68

10.4.3.3.2 FCM Command, Address, and Write Data Timing.........................................10-68

10.4.3.3.3 FCM Ready/Busy Timing................................................................................ 10-70

10.4.3.3.4 FCM Read Data Timing .................................................................................. 10-70

10.4.3.3.5 FCM Extended Read Hold Timing.................................................................. 10-71

10.4.3.4 FCM Boot Chip-Select Operation ....................................................................... 10-72

10.4.3.4.1 FCM Bank 0 Reset Initialization.....................................................................10-72

10.4.3.4.2 Boot Block Loading into the FCM Buffer RAM............................................. 10-73

10.4.4 User-Programmable Machines (UPMs)................................................................... 10-74

10.4.4.1 UPM Requests ..................................................................................................... 10-75

10.4.4.1.1 Memory Access Requests................................................................................ 10-76

10.4.4.1.2 UPM Refresh Timer Requests......................................................................... 10-77

10.4.4.1.3 Software Requests—RUN Command ............................................................. 10-77

10.4.4.1.4 Exception Requests.......................................................................................... 10-77

10.4.4.2 Programming the UPMs ...................................................................................... 10-78

10.4.4.2.1 UPM Programming Example (Two Sequential Writes to the RAM Array)....10-79

10.4.4.2.2 UPM Programming Example (Two Sequential Reads from the RAM Array) 10-79

10.4.4.3 UPM Signal Timing............................................................................................. 10-80

10.4.4.4 RAM Array.......................................................................................................... 10-80

10.4.4.4.1 RAM Words..................................................................................................... 10-81

10.4.4.4.2 Chip-Select Signal Timing (CSTn) ................................................................. 10-84

10.4.4.4.3 Byte Select Signal Timing (BSTn).................................................................. 10-85

10.4.4.4.4 General-Purpose Signals (GnTn, GOn)........................................................... 10-86

10.4.4.4.5 Loop Control (LOOP) .....................................................................................10-86

10.4.4.4.6 Repeat Execution of Current RAM Word (REDO).........................................10-86

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10.4.4.4.7 Address Multiplexing (AMX) ......................................................................... 10-87

10.4.4.4.8 Data Valid and Data Sample Control (UTA)................................................... 10-88

10.4.4.4.9 LGPL[0–5] Signal Negation (LAST).............................................................. 10-89

10.4.4.4.10 Wait Mechanism (WAEN)............................................................................... 10-89

10.4.4.5 Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge ............10-90

10.4.4.6 Extended Hold Time on Read Accesses.............................................................. 10-91

10.5 Initialization/Application Information......................................................................... 10-91

10.5.1 Interfacing to Peripherals in Different Address Modes........................................... 10-91

10.5.1.1 Multiplexed Address/Data Bus for 32-Bit Addressing........................................ 10-91

10.5.1.2 Non-Multiplexed Address and Data Buses..........................................................10-92

10.5.1.3 Multiplexed Address and Data To Save Maximum Pins In 8- to 16-Bit Addressing....

10-92

10.5.1.4 Peripheral Hierarchy on the Local Bus for High Bus Speeds ............................. 10-92

10.5.1.5 GPCM Timings.................................................................................................... 10-93

10.5.2 Bus Turnaround ....................................................................................................... 10-94

10.5.2.1 Address Phase after Previous Read ..................................................................... 10-94

10.5.2.2 Read Data Phase after Address Phase ................................................................. 10-94

10.5.2.3 Read-Modify-Write Cycle for Parity Protected Memory Banks.........................10-95

10.5.2.4 UPM Cycles with Additional Address Phases.....................................................10-95

10.5.3 Interface to Different Port-Size Devices.................................................................. 10-95

10.5.4 Command Sequence Examples for NAND Flash EEPROM...................................10-97

10.5.4.1 NAND Flash Soft Reset Command Sequence Example .....................................10-97

10.5.4.2 NAND Flash Read Status Command Sequence Example...................................10-98

10.5.4.3 NAND Flash Read Identification Command Sequence Example....................... 10-98

10.5.4.4 NAND Flash Page Read Command Sequence Example.....................................10-99

10.5.4.5 NAND Flash Block Erase Command Sequence Example .................................. 10-99

10.5.4.6 NAND Flash Program Command Sequence Example...................................... 10-100

10.5.5 Interfacing to Fast-Page Mode DRAM Using UPM ............................................. 10-101

10.5.6 Interfacing to ZBT SRAM Using UPM................................................................. 10-106

Chapter 11

Enhanced Secure Digital Host Controller

11.1 Overview........................................................................................................................ 11-1

11.2 Features.......................................................................................................................... 11-2

11.2.1 Data Transfer Modes.................................................................................................. 11-3

11.3 External Signal Description........................................................................................... 11-3

11.4 Memory Map/Register Definition ................................................................................. 11-4

11.4.1 DMA System Address Register (DSADDR)............................................................. 11-5

11.4.2 Block Attributes Register (BLKATTR)..................................................................... 11-6

11.4.3 Command Argument Register (CMDARG).............................................................. 11-7

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11.4.4 Transfer Type Register (XFERTYP).......................................................................... 11-7

11.4.5 Command Response 0–3 (CMDRSP0–3)................................................................ 11-10

11.4.6 Buffer Data Port Register (DATPORT)....................................................................11-11

11.4.7 Present State Register (PRSSTAT) .......................................................................... 11-12

11.4.8 Protocol Control Register (PROCTL) ..................................................................... 11-16

11.4.9 System Control Register (SYSCTL)........................................................................ 11-18

11.4.10 Interrupt Status Register (IRQSTAT)....................................................................... 11-21

11.4.11 Interrupt Status Enable Register (IRQSTATEN)..................................................... 11-25

11.4.12 Interrupt Signal Enable Register (IRQSIGEN) ....................................................... 11-27

11.4.13 Auto CMD12 Error Status Register (AUTOC12ERR)............................................ 11-29

11.4.14 Host Controller Capabilities (HOSTCAPBLT) ....................................................... 11-31

11.4.15 Watermark Level Register (WML).......................................................................... 11-32

11.4.16 Force Event Register (FEVT).................................................................................. 11-32

11.4.17 Host Controller Version Register (HOSTVER)....................................................... 11-34

11.4.18 DMA Control Register (DCR)................................................................................. 11-35

11.5 Functional Description................................................................................................. 11-36

11.5.1 Data Buffer .............................................................................................................. 11-36

11.5.1.1 Write Operation Sequence................................................................................... 11-37

11.5.1.2 Read Operation Sequence.................................................................................... 11-38

11.5.1.3 Data Buffer Size................................................................................................... 11-38

11.5.2 DMA CSB Interface ................................................................................................ 11-38

11.5.2.1 Internal DMA Request......................................................................................... 11-39

11.5.2.2 DMA Burst Length.............................................................................................. 11-39

11.5.2.3 CSB Master Interface .......................................................................................... 11-40

11.5.3 SD Protocol Unit...................................................................................................... 11-40

11.5.3.1 SD Transceiver .................................................................................................... 11-40

11.5.3.2 SD Clock and Monitor......................................................................................... 11-40

11.5.3.3 Command Agent.................................................................................................. 11-41

11.5.3.4 Data Agent........................................................................................................... 11-41

11.5.4 Clock & Reset Manager........................................................................................... 11-41

11.5.5 Clock Generator....................................................................................................... 11-41

11.5.6 Card Insertion and Removal Detection.................................................................... 11-42

11.5.7 Power Management and Wake-Up Events .............................................................. 11-42

11.5.7.1 Setting Wake Up Events ...................................................................................... 11-43

11.6 Initialization/Application Information......................................................................... 11-43

11.6.1 Command Send and Response Receive Basic Operation........................................ 11-43

11.6.2 Card Identification Mode......................................................................................... 11-44

11.6.2.1 Card Detect .......................................................................................................... 11-44

11.6.2.2 Reset .................................................................................................................... 11-45

11.6.2.3 Voltage Validation................................................................................................ 11-45

11.6.2.4 Card Registry....................................................................................................... 11-46

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11.6.3 Card Access ............................................................................................................. 11-47

11.6.3.1 Block Write.......................................................................................................... 11-47

11.6.3.1.1 Normal Write................................................................................................... 11-47

11.6.3.1.2 Write with Pause.............................................................................................. 11-48

11.6.3.2 Block Read........................................................................................................... 11-49

11.6.3.2.1 Normal Read.................................................................................................... 11-49

11.6.3.2.2 Read with Pause............................................................................................... 11-49

11.6.3.3 Transfer Error ...................................................................................................... 11-50

11.6.3.3.1 CRC Error........................................................................................................ 11-50

11.6.3.3.2 Internal DMA Error......................................................................................... 11-51

11.6.3.3.3 Auto CMD12 Error.......................................................................................... 11-51

11.6.3.4 Card Interrupt....................................................................................................... 11-51

11.6.4 Switch Function....................................................................................................... 11-51

11.6.4.1 Query, Enable and Disable SD High Speed Mode .............................................. 11-52

11.6.4.2 Query, Enable and Disable MMC High Speed Mode.......................................... 11-52

11.6.4.3 Set MMC Bus Width ........................................................................................... 11-53

11.6.5 Commands for MMC/SD......................................................................................... 11-53

11.6.6 Software Restrictions............................................................................................... 11-58

Chapter 12

Sequencer

12.1 Overview........................................................................................................................12-1

12.1.1 Features......................................................................................................................12-2

12.2 External Signal Description........................................................................................... 12-2

12.3 Memory Map/Register Definition ................................................................................. 12-2

12.4 Register Descriptions..................................................................................................... 12-3

12.4.1 PCI Outbound Translation Address Registers (POTARn)......................................... 12-3

12.4.2 PCI Outbound Base Address Registers (POBARn) .................................................. 12-3

12.4.3 PCI Outbound Comparison Mask Registers (POCMRn)..........................................12-4

12.4.4 Power Management Control Register (PMCR).........................................................12-5

12.4.5 Discard Timer Control Register (DTCR) .................................................................. 12-6

12.5 Functional Description................................................................................................... 12-6

12.5.1 Transaction Forwarding............................................................................................. 12-6

12.5.1.1 Transactions from the Coherency System Bus (CSB) Port...................................12-7

12.5.1.2 Transactions from the PCI Port ............................................................................. 12-7

12.5.1.3 Transactions from the DMA Port .......................................................................... 12-7

12.5.2 PCI Outbound Address Translation........................................................................... 12-7

12.5.3 Transaction Ordering ................................................................................................. 12-8

MPC8379E PowerQUICC II Pro Integrated Host Processor Family Reference Manual, Rev. 1

xx Freescale Semiconductor

Contents

Paragraph

Number Title

Page

Number

Chapter 13

DMA/Messaging Unit

13.1 Features..........................................................................................................................13-1

13.2 External Signal Description........................................................................................... 13-2

13.2.1 Detailed Signal Descriptions ..................................................................................... 13-2

13.3 Memory Map/Register Definition ................................................................................. 13-3

13.4 Register Descriptions..................................................................................................... 13-4

13.4.1 Outbound Message Interrupt Status Register (OMISR)............................................ 13-4

13.4.2 Outbound Message Interrupt Mask Register (OMIMR)............................................13-5

13.4.3 Inbound Message Registers (IMR0–IMR1) .............................................................. 13-6

13.4.4 Outbound Message Registers (OMR0–OMR1).........................................................13-6

13.4.5 Doorbell Registers ..................................................................................................... 13-7

13.4.5.1 Outbound Doorbell Register (ODR)...................................................................... 13-7

13.4.5.2 Inbound Doorbell Register (IDR)..........................................................................13-8

13.4.6 Inbound Message Interrupt Status Register (IMISR) ................................................ 13-8

13.4.7 Inbound Message Interrupt Mask Register (IMIMR)................................................13-9

13.4.8 DMA Registers ........................................................................................................ 13-10

13.4.8.1 DMA Mode Register (DMAMRn)...................................................................... 13-10

13.4.8.2 DMA Status Register (DMASRn)....................................................................... 13-12

13.4.8.3 DMA Current Descriptor Address Register (DMACDARn) ..............................13-13

13.4.8.4 DMA Source Address Register (DMASARn)..................................................... 13-14

13.4.8.5 DMA Destination Address Register (DMADARn)............................................. 13-14

13.4.8.6 DMA Byte Count Register (DMABCRn) ........................................................... 13-15

13.4.8.7 DMA Next Descriptor Address Register (DMANDARn)................................... 13-15

13.4.8.8 DMA General Status Register (DMAGSR).........................................................13-16

13.5 Functional Description................................................................................................. 13-16

13.5.1 Message Unit ........................................................................................................... 13-16

13.5.1.1 Messaging Registers (IMR0–IMR1, OMR0–OMR1).........................................13-16

13.5.1.2 Doorbell Registers (IDR and ODR) .................................................................... 13-17

13.5.2 DMA Controller....................................................................................................... 13-17

13.5.3 DMA Operation....................................................................................................... 13-17

13.5.3.1 External Control................................................................................................... 13-18

13.5.3.2 DMA Coherency.................................................................................................. 13-19

13.5.3.3 Halt and Error Conditions.................................................................................... 13-19

13.5.4 DMA Segment Descriptors...................................................................................... 13-20

13.5.4.1 Descriptor in Big-Endian Mode........................................................................... 13-21

13.5.4.2 Descriptor in Little-Endian Mode........................................................................13-22

13.6 Initialization/Application Information......................................................................... 13-22

13.6.1 Initialization Steps in Direct Mode..........................................................................13-22

13.6.2 Initialization Steps in Chaining Mode.....................................................................13-22

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