NXP MPC601 User guide

Brand: NXP

Model: MPC601

Type: User guide

MPR601UM-01 MPC601UM/AD

PowerPC

™

601

RISC Microprocessor User's Manual

Contents

iii

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Title

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Number

About This Book

Audience..............................................................................................................xlii

Organization.........................................................................................................xlii

Additional Reading............................................................................................. xliv

Conventions ........................................................................................................ xliv

Acronyms and Abbreviations ............................................................................. xliv

Terminology Conventions .................................................................................xlvii

Chapter 1

Overview

1.1 PowerPC 601 Microprocessor Overview.............................................................1-1

1.1.1 601 Features.....................................................................................................1-2

1.1.2 Block Diagram.................................................................................................1-3

1.1.3 Instruction Unit................................................................................................1-5

1.1.3.1 Instruction Queue......................................................................................... 1-5

1.1.4 Independent Execution Units...........................................................................1-5

1.1.4.1 Branch Processing Unit (BPU)....................................................................1-6

1.1.4.2 Integer Unit (IU)..........................................................................................1-6

1.1.4.3 Floating-Point Unit (FPU)........................................................................... 1-7

1.1.5 Memory Management Unit (MMU)................................................................1-7

1.1.6 Cache Unit .......................................................................................................1-8

1.1.7 Memory Unit....................................................................................................1-8

1.1.8 System Interface ............................................................................................1-10

1.2 Levels of the PowerPC Architecture..................................................................1-10

1.3 The 601 as a PowerPC Implementation.............................................................1-11

1.3.1 Features..........................................................................................................1-12

1.3.2 Registers and Programming Model ...............................................................1-13

1.3.2.1 PowerPC Registers and Programming Model........................................... 1-13

1.3.2.1.1 General-Purpose Registers (GPRs)........................................................1-13

1.3.2.1.2 Floating-Point Registers (FPRs)............................................................1-14

1.3.2.1.3 Condition Register (CR)........................................................................1-14

1.3.2.1.4 Floating-Point Status and Control Register (FPSCR) ...........................1-14

1.3.2.1.5 Machine State Register (MSR)..............................................................1-14

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1.3.2.1.6 Segment Registers (SRs)........................................................................1-14

1.3.2.1.7 Special-Purpose Registers (SPRs)..........................................................1-14

1.3.2.1.8 User-Level SPRs ....................................................................................1-14

1.3.2.1.9 Supervisor-Level SPRs ..........................................................................1-15

1.3.2.2 Additional Registers in the 601..................................................................1-16

1.3.3 Instruction Set and Addressing Modes...........................................................1-18

1.3.3.1 PowerPC Instruction Set and Addressing Modes.......................................1-18

1.3.3.1.1 PowerPC Instruction Set ........................................................................1-18

1.3.3.1.2 Calculating Effective Addresses ............................................................1-19

1.3.3.2 601 Instruction Set......................................................................................1-20

1.3.4 Cache Implementation....................................................................................1-20

1.3.4.1 PowerPC Cache Characteristics.................................................................1-21

1.3.4.2 601 Cache Implementation.........................................................................1-21

1.3.5 Exception Model ............................................................................................1-22

1.3.5.1 PowerPC Exception Model ........................................................................1-23

1.3.5.2 The 601 Exception Model..........................................................................1-24

1.3.6 Memory Management ....................................................................................1-27

1.3.6.1 PowerPC Memory Management ................................................................1-27

1.3.6.2 601 Memory Management .........................................................................1-28

1.3.7 601 Instruction Timing...................................................................................1-29

1.3.8 System Interface.............................................................................................1-31

1.3.8.1 Memory Accesses.......................................................................................1-32

1.3.8.2 I/O Controller Interface Operations ...........................................................1-33

1.3.8.3 601 Signals.................................................................................................1-33

1.3.8.4 Signal Configuration ..................................................................................1-34

1.3.8.5 Real-Time Clock ........................................................................................1-35

Chapter 2

Registers and Data Types

2.1 Normal Instruction Execution State .....................................................................2-1

2.1.1 Changing Privilege Levels ...............................................................................2-6

2.2 User-Level Registers ............................................................................................2-6

2.2.1 General Purpose Registers (GPRs)...................................................................2-6

2.2.2 Floating-Point Registers (FPRs).......................................................................2-7

2.2.3 Floating-Point Status and Control Register (FPSCR)......................................2-8

2.2.4 Condition Register (CR).................................................................................2-11

2.2.4.1 Condition Register CR0 Field Definition...................................................2-12

2.2.4.2 Condition Register CR1 Field Definition...................................................2-12

2.2.4.3 Condition Register CR

Field—Compare Instruction...............................2-12

2.2.5 User-Level SPRs ............................................................................................2-13

2.2.5.1 MQ Register (MQ).....................................................................................2-13

Contents

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2.2.5.2 Integer Exception Register (XER).............................................................2-15

2.2.5.3 Real-Time Clock (RTC) Registers (User-Level).......................................2-16

2.2.5.3.1 Real-Time Clock Lower (RTCL) Register ............................................2-17

2.2.5.3.2 Real-Time Clock Upper (RTCU) Register ............................................2-18

2.2.5.3.3 Reading the RTC....................................................................................2-18

2.2.5.3.4 RTC Synchronization in a Multiprocessor System................................2-19

2.2.5.4 Link Register (LR).....................................................................................2-19

2.2.5.5 Count Register (CTR)................................................................................2-20

2.3 Supervisor-Level Registers................................................................................2-20

2.3.1 Machine State Register (MSR) ......................................................................2-20

2.3.2 Segment Registers..........................................................................................2-22

2.3.3 Supervisor-Level SPRs ..................................................................................2-24

2.3.3.1 Synchronization for Supervisor-Level SPRs and Segment Registers........2-25

2.3.3.1.1 Context Synchronization........................................................................2-25

2.3.3.1.2 Other Synchronization Requirements by Register.................................2-29

2.3.3.2 DAE/Source Instruction Service Register (DSISR)...................................2-29

2.3.3.3 Data Address Register (DAR)....................................................................2-30

2.3.3.4 Real-Time Clock (RTC) Registers (Supervisor-Level) .............................2-30

2.3.3.5 Decrementer (DEC) Register.....................................................................2-30

2.3.3.5.1 Decrementer Operation..........................................................................2-31

2.3.3.5.2 Writing and Reading the DEC...............................................................2-31

2.3.3.6 Table Search Description Register 1 (SDR1) ............................................2-32

2.3.3.7 Machine Status Save/Restore Register 0 (SRR0) ......................................2-32

2.3.3.8 Machine Status Save/Restore Register 1 (SRR1) ......................................2-33

2.3.3.9 General SPRs (SPRG0–SPRG3)................................................................2-33

2.3.3.10 External Access Register (EAR)................................................................2-34

2.3.3.11 Processor Version Register (PVR).............................................................2-35

2.3.3.12 BAT Registers............................................................................................2-36

2.3.3.13 601 Implementation-Specific HID Registers.............................................2-38

2.3.3.13.1 Checkstop Sources and Enables Register—HID0.................................2-38

2.3.3.13.2 601 Debug Modes Register—HID1.......................................................2-41

2.3.3.13.3 Instruction Address Breakpoint Register (IABR)—HID2.....................2-42

2.3.3.13.4 Data Address Breakpoint Register (DABR)—HID5.............................2-42

2.3.3.13.5 Processor Identification Register (PIR)—HID15..................................2-44

2.4 Operand Conventions.........................................................................................2-44

2.4.1 Data Organization in Memory and Data Transfers........................................2-44

2.4.1.1 Alignment and Misaligned Accesses.........................................................2-45

2.4.2 Effect of Operand Placement on Performance...............................................2-45

2.4.2.1 Instruction Restart......................................................................................2-46

2.4.2.2 Atomicity ...................................................................................................2-47

2.4.2.3 Access Order..............................................................................................2-47

2.4.3 Byte and Bit Ordering....................................................................................2-47

2.4.3.1 Little-Endian Address Manipulation..........................................................2-48

PowerPC 601 RISC Microprocessor User's Manual

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2.4.3.2 Little-Endian Alignment Exceptions..........................................................2-49

2.4.3.3 Little-Endian Instruction Fetching .............................................................2-49

2.4.3.4 Big-Endian Byte Ordering..........................................................................2-50

2.4.3.5 Little-Endian Byte Ordering.......................................................................2-50

2.4.4 Structure Mapping Examples.........................................................................2-50

2.4.4.1 Big-Endian Mapping..................................................................................2-50

2.4.4.2 Little-Endian Mapping ...............................................................................2-51

2.4.5 PowerPC Byte Ordering.................................................................................2-51

2.4.5.1 Aligned Scalars...........................................................................................2-52

2.4.5.2 Misaligned Scalars .....................................................................................2-53

2.4.5.3 Non-Scalars ................................................................................................2-54

2.4.5.3.1 String Operations....................................................................................2-54

2.4.5.3.2 Load and Store Multiple Instructions.....................................................2-55

2.4.6 PowerPC Instruction Memory Addressing in Little-Endian Mode................2-55

2.4.7 PowerPC Input/Output in Little-Endian Mode...............................................2-57

2.5 Floating-Point Execution Models.......................................................................2-57

2.5.1 Execution Model for IEEE Operations...........................................................2-58

2.5.1.1 Execution Model for Multiply-Add Type Instructions ..............................2-60

2.5.2 Floating-Point Data Format............................................................................2-61

2.5.2.1 Value Representation .................................................................................2-63

2.5.2.2 Binary Floating-Point Numbers .................................................................2-64

2.5.2.3 Normalized Numbers (

NORM)................................................................2-64

2.5.2.4 Zero Values (

0) ........................................................................................2-65

2.5.2.5 Denormalized Numbers (

DENORM).......................................................2-65

2.5.2.6 Infinities (

±∞

).............................................................................................2-66

2.5.2.7 Not a Numbers (NaNs)...............................................................................2-66

2.5.3 Sign of Result.................................................................................................2-68

2.5.4 Normalization and Denormalization ..............................................................2-68

2.5.5 Data Handling and Precision..........................................................................2-69

2.5.6 Rounding ........................................................................................................2-70

2.6 PowerPC Registers Unimplemented in the 601 .................................................2-73

2.7 Reset ...................................................................................................................2-74

2.7.1 Hard Reset......................................................................................................2-74

2.7.2 Soft Reset........................................................................................................2-75

Chapter 3

Addressing Modes and Instruction Set Summary

3.1 Memory Addressing.............................................................................................3-2

3.1.1 Effective Address Calculation..........................................................................3-2

3.1.2 Context Synchronization..................................................................................3-3

3.2 Exception Summary .............................................................................................3-3

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3.3 Integer Instructions...............................................................................................3-4

3.3.1 Integer Arithmetic Instructions........................................................................3-4

3.3.2 Integer Compare Instructions.........................................................................3-15

3.3.3 Integer Logical Instructions ...........................................................................3-16

3.3.4 Integer Rotate and Shift Instructions..............................................................3-18

3.3.4.1 Integer Rotate Instructions.........................................................................3-21

3.3.4.2 Integer Shift Instructions............................................................................3-24

3.4 Floating-Point Instructions.................................................................................3-31

3.4.1 Floating-Point Arithmetic Instructions ..........................................................3-31

3.4.2 Floating-Point Multiply-Add Instructions......................................................3-34

3.4.3 Floating-Point Rounding and Conversion Instructions..................................3-38

3.4.4 Floating-Point Compare Instructions.............................................................3-39

3.4.5 Floating-Point Status and Control Register Instructions................................3-40

3.5 Load and Store Instructions................................................................................3-42

3.5.1 Integer Load and Store Address Generation..................................................3-42

3.5.1.1 Register Indirect with Immediate Index Addressing .................................3-42

3.5.1.2 Register Indirect with Index Addressing ...................................................3-43

3.5.1.3 Register Indirect Addressing......................................................................3-44

3.5.2 Integer Load Instructions ...............................................................................3-44

3.5.3 Integer Store Instructions...............................................................................3-47

3.5.4 Integer Load and Store with Byte Reversal Instructions ...............................3-49

3.5.5 Integer Load and Store Multiple Instructions ................................................3-49

3.5.6 Integer Move String Instructions ...................................................................3-50

3.5.7 Memory Synchronization Instructions...........................................................3-53

3.5.8 Floating-Point Load and Store Address Generation ......................................3-56

3.5.8.1 Register Indirect with Immediate Index Addressing .................................3-57

3.5.8.2 Register Indirect with Index Addressing ...................................................3-57

3.5.9 Floating-Point Load Instructions....................................................................3-58

3.5.9.1 Double-Precision Conversion for Floating-Point Load Instructions .........3-60

3.5.10 Floating-Point Store Instructions ...................................................................3-61

3.5.10.1 Double-Precision Conversion for Floating-Point Store Instructions.........3-62

3.5.11 Floating-Point Move Instructions ..................................................................3-62

3.6 Branch and Flow Control Instructions...............................................................3-63

3.6.1 Branch instruction Address Calculation.........................................................3-63

3.6.1.1 Branch Relative Address Mode .................................................................3-64

3.6.1.2 Branch Conditional Relative Address Mode .............................................3-64

3.6.1.3 Branch to Absolute Address Mode............................................................3-65

3.6.1.4 Branch Conditional to Absolute Address Mode ........................................3-66

3.6.1.5 Branch Conditional to Link Register Address Mode.................................3-66

3.6.1.6 Branch Conditional to Count Register.......................................................3-67

3.6.2 Conditional Branch Control...........................................................................3-68

3.6.3 Basic Branch Mnemonics ..............................................................................3-70

3.6.4 Branch Mnemonics Incorporating Conditions...............................................3-73

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3.6.5 Branch Instructions.........................................................................................3-75

3.6.6 Condition Register Logical Instructions.........................................................3-76

3.6.7 System Linkage Instructions ..........................................................................3-78

3.6.8 Simplified Mnemonics for Branch Processor Instructions.............................3-78

3.6.9 Trap Instructions and Mnemonics..................................................................3-79

3.7 Processor Control Instructions............................................................................3-81

3.7.1 Move to/from Machine State Register and Condition Register Instructions .3-81

3.7.2 Move to/from Special-Purpose Register Instructions.....................................3-82

3.8 Memory Control Instructions .............................................................................3-86

3.8.1 Supervisor-Level Cache Management Instruction.........................................3-86

3.8.2 User-Level Cache Instructions.......................................................................3-87

3.8.3 Segment Register Manipulation Instructions .................................................3-90

3.8.4 Translation Lookaside Buffer Management Instruction.................................3-91

3.9 External Control Instructions..............................................................................3-92

3.10 Miscellaneous Simplified Mnemonics ...............................................................3-93

3.10.1 No-Op.............................................................................................................3-94

3.10.2 Load Immediate..............................................................................................3-94

3.10.3 Load Address..................................................................................................3-94

3.10.4 Move Register ................................................................................................3-94

3.10.5 Complement Register.....................................................................................3-95

Chapter 4

Cache and Memory Unit Operation

4.1 Cache Organization ..............................................................................................4-2

4.2 Cache Arbitration .................................................................................................4-3

4.3 Cache Access Priorities........................................................................................4-4

4.4 Basic Cache Operations........................................................................................4-4

4.4.1 Cache Reloads..................................................................................................4-4

4.4.2 Cache Cast-Out Operation................................................................................4-4

4.4.3 Cache Sector Push Operation...........................................................................4-5

4.4.4 Optional Cache Sector Line-Fill Operation......................................................4-5

4.5 Cache Data Transactions......................................................................................4-5

4.6 Access to I/O Controller Interface Segments.......................................................4-6

4.7 Cache Coherency..................................................................................................4-6

4.7.1 Memory Management Access Mode Bits—W, I, and M.................................4-7

4.7.2 MESI Protocol..................................................................................................4-8

4.7.3 MESI State Diagram.........................................................................................4-9

4.7.4 MESI Hardware Considerations.....................................................................4-10

4.7.5 Coherency Precautions...................................................................................4-11

4.7.5.1 Coherency in Single-Processor Systems....................................................4-12

4.7.5.2 Coherency in Multiprocessor Systems.......................................................4-12

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4.7.6 Memory Loads and Stores .............................................................................4-13

4.7.7 Atomic Memory References..........................................................................4-14

4.7.8 Snoop Response to Bus Operations ...............................................................4-14

4.7.9 Cache Reaction to Specific Bus Operations...................................................4-15

4.7.10 Internal

ARTRY

Scenarios............................................................................4-17

4.7.11 Enveloped High-Priority Cache Sector Push Operation................................4-17

4.8 Cache Control Instructions.................................................................................4-17

4.8.1 Cache Line Compute Size Instruction (

clcs

)..................................................4-18

4.8.2 Data Cache Block Touch Instruction (

dcbt

)..................................................4-18

4.8.3 Data Cache Block Touch for Store Instruction (

dcbtst

)................................4-19

4.8.4 Data Cache Block Set to Zero Instruction (

dcbz

)..........................................4-19

4.8.5 Data Cache Block Store Instruction (

dcbst

)..................................................4-19

4.8.6 Data Cache Block Flush Instruction (

dcbf

)...................................................4-20

4.8.7 Enforce In-Order Execution of I/O Instruction (

eieio

) ..................................4-20

4.8.8 Instruction Cache Block Invalidate Instruction (

icbi

)....................................4-21

4.8.9 Instruction Synchronize Instruction (

isync

)...................................................4-21

4.9 Bus Operations Caused by Cache Control Instructions.....................................4-21

4.10 Memory Unit......................................................................................................4-22

4.10.1 Memory Unit Queuing Structure ...................................................................4-24

4.10.2 Memory Unit Queuing Priorities ...................................................................4-24

4.10.3 Bus Interface ..................................................................................................4-25

4.11 MESI State Transactions....................................................................................4-25

Chapter 5

Exceptions

5.1 Exception Classes.................................................................................................5-2

5.1.1 Precise Exceptions ...........................................................................................5-5

5.1.1.1 Synchronous/Precise Exceptions .................................................................5-6

5.1.1.2 Asynchronous/Precise Exceptions...............................................................5-6

5.1.1.3 Asynchronous, Imprecise Exceptions..........................................................5-7

5.1.2 Exception Priorities..........................................................................................5-7

5.1.3 Recognition of Exceptions...............................................................................5-8

5.1.3.1 Recognition of Asynchronous, Imprecise Exceptions.................................5-9

5.1.3.2 Recognition of Precise Exceptions ..............................................................5-9

5.2 Exception Processing .........................................................................................5-10

5.2.1 Enabling and Disabling Exceptions...............................................................5-13

5.2.2 Steps for Exception Processing......................................................................5-14

5.2.3 Returning from Supervisor Mode ..................................................................5-14

5.3 Process Switching ..............................................................................................5-15

5.4 Exception Definitions.........................................................................................5-15

5.4.1 Reset Exceptions (x'00100')...........................................................................5-16

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5.4.1.1 Soft Reset ...................................................................................................5-16

5.4.1.2 Hard Reset..................................................................................................5-17

5.4.2 Machine Check Exception (x'00200').............................................................5-19

5.4.2.1 Machine Check Exception Enabled (MSR[ME] = 1) ................................5-20

5.4.2.2 Checkstop State (MSR[ME] = 0)...............................................................5-20

5.4.3 Data Access Exception (x'00300')..................................................................5-21

5.4.4 Instruction Access Exception (x'00400')........................................................5-23

5.4.5 External Interrupt (x'00500') ..........................................................................5-24

5.4.6 Alignment Exception (x'00600').....................................................................5-25

5.4.6.1 Integer Alignment Exceptions....................................................................5-26

5.4.6.1.1 Direct-Translation Access......................................................................5-27

5.4.6.1.2 I/O Controller Interface Access..............................................................5-27

5.4.6.1.3 Memory-Forced I/O Controller Interface Access ..................................5-27

5.4.6.1.4 Page Address Translation Access...........................................................5-28

5.4.6.2 Floating-Point Alignment Exceptions........................................................5-29

5.4.6.3 Little-Endian Mode Alignment Exceptions ...............................................5-29

5.4.6.4 Interpretation of the DSISR as Set by an Alignment Exception................5-29

5.4.7 Program Exception (x'00700')........................................................................5-32

5.4.7.1 Floating-Point Enabled Program Exceptions .............................................5-33

5.4.7.2 Invalid Operation Exception Conditions....................................................5-39

5.4.7.2.1 Action for Invalid Operation Exception Conditions ..............................5-40

5.4.7.3 Zero Divide Exception Condition ..............................................................5-41

5.4.7.3.1 Action for Zero Divide Exception Condition.........................................5-41

5.4.7.4 Overflow Exception Condition ..................................................................5-42

5.4.7.4.1 Action for Overflow Exception Condition.............................................5-42

5.4.7.5 Underflow Exception Condition ................................................................5-43

5.4.7.5.1 Action for Underflow Exception Condition...........................................5-43

5.4.7.6 Inexact Exception Condition......................................................................5-44

5.4.7.6.1 Action for Inexact Exception Condition ................................................5-44

5.4.8 Floating-Point Unavailable Exception (x'00800') ..........................................5-44

5.4.9 Decrementer Exception (x'00900').................................................................5-45

5.4.10 I/O Controller Interface Error Exception (x'00A00') .....................................5-46

5.4.11 System Call Exception (x'00C00')..................................................................5-47

5.4.12 Run Mode/Trace Exception (x'02000')...........................................................5-48

5.4.12.1 Run Mode Exception..................................................................................5-48

5.4.12.2 Trace Exception..........................................................................................5-50

Chapter 6

Memory Management Unit

6.1 MMU Overview ...................................................................................................6-2

6.1.1 Memory Addressing.........................................................................................6-3

Contents

CONTENTS

6.1.2 MMU Organization..........................................................................................6-3

6.1.3 Address Translation Mechanisms....................................................................6-5

6.1.4 Memory Protection Facilities...........................................................................6-7

6.1.5 Page History Information.................................................................................6-8

6.1.6 General Flow of MMU Address Translation...................................................6-8

6.1.7 Memory/MMU Coherency Model.................................................................6-10

6.1.8 Effects of Instruction Fetch on MMU............................................................6-11

6.1.9 Breakpoint Facility.........................................................................................6-12

6.1.10 MMU Exceptions Summary ..........................................................................6-12

6.1.11 MMU Instructions and Register Summary....................................................6-14

6.1.12 TLB Entry Invalidation..................................................................................6-14

6.2 ITLB Description ...............................................................................................6-15

6.3 Memory/Cache Access Modes...........................................................................6-16

6.3.1 Write-Through Bit (W)..................................................................................6-16

6.3.2 Caching Inhibited Bit (I)................................................................................6-17

6.3.3 Memory Coherence Bit (M)...........................................................................6-17

6.3.4 W, I, and M Bit Combinations.......................................................................6-18

6.4 General Memory Protection Mechanism ...........................................................6-19

6.5 Selection of Address Translation Type..............................................................6-21

6.5.1 Address Translation Selection for Instruction Accesses................................6-21

6.5.1.1 Instruction Address Translation Disabled: MSR[IT] = 0...........................6-22

6.5.1.2 Instruction Address Translation Enabled: MSR[IT] = 1............................6-22

6.5.2 Address Translation Selection for Data Accesses..........................................6-23

6.5.2.1 I/O Controller Interface Address Translation: T = 1 in Segment Register 6-23

6.5.2.2 Data Translation Disabled: MSR[DT] = 0.................................................6-23

6.5.2.3 Data Translation Enabled: MSR[DT] = 1..................................................6-23

6.6 Direct Address Translation.................................................................................6-24

6.7 Block Address Translation.................................................................................6-24

6.7.1 BAT Array Organization................................................................................6-25

6.7.2 Recognition of Addresses in BAT Array.......................................................6-26

6.7.3 BAT Register Implementation of BAT Array ...............................................6-27

6.7.4 Block Memory Protection..............................................................................6-29

6.7.5 Block Physical Address Generation...............................................................6-29

6.7.6 Block Address Translation Summary ............................................................6-30

6.8 Memory Segment Model....................................................................................6-33

6.8.1 Page Address Translation Resources.............................................................6-33

6.8.2 Recognition of Addresses in Segments..........................................................6-34

6.8.2.1 Selection of Memory Segments.................................................................6-35

6.8.2.2 Selection of I/O Controller Interface Segments.........................................6-35

6.8.3 Page Address Translation...............................................................................6-36

6.8.3.1 Segment Register Definition......................................................................6-37

6.8.3.2 Page Table Entry (PTE) Format.................................................................6-38

6.8.4 Page History Recording .................................................................................6-40

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6.8.4.1 Reference Bit..............................................................................................6-41

6.8.4.2 Change Bit..................................................................................................6-41

6.8.5 Page Memory Protection................................................................................6-41

6.8.6 Page Address Translation Summary ..............................................................6-42

6.9 Hashed Page Tables............................................................................................6-42

6.9.1 Page Table Definition.....................................................................................6-44

6.9.1.1 Table Search Description Register (SDR1)................................................6-45

6.9.1.2 Page Table Size ..........................................................................................6-46

6.9.1.3 Hashing Functions......................................................................................6-47

6.9.1.4 Page Table Addresses.................................................................................6-48

6.9.1.5 Page Table Structure ..................................................................................6-50

6.9.1.5.1 Page Table Structure Example...............................................................6-51

6.9.1.5.2 PTEG Address Mapping Example.........................................................6-52

6.9.2 Page Table Search Operation .........................................................................6-55

6.9.3 Page Table Updates........................................................................................6-58

6.9.3.1 Adding a Page Table Entry ........................................................................6-59

6.9.3.2 Modifying a Page Table Entry ...................................................................6-60

6.9.3.2.1 General Case ..........................................................................................6-60

6.9.3.2.2 Clearing the Reference (R) Bit...............................................................6-60

6.9.3.2.3 Modifying the Virtual Address ..............................................................6-61

6.9.3.3 Deleting a Page Table Entry.......................................................................6-61

6.9.4 Segment Register Updates..............................................................................6-61

6.10 I/O Controller Interface Address Translation.....................................................6-62

6.10.1 Segment Register Format for I/O Controller Interface...................................6-62

6.10.2 I/O Controller Interface Accesses ..................................................................6-63

6.10.3 I/O Controller Interface Segment Protection..................................................6-63

6.10.4 Memory-Forced I/O Controller Interface Accesses .......................................6-63

6.10.5 Instructions Not Supported in I/O Controller Interface Segments.................6-64

6.10.6 Instructions with No Effect in I/O Controller Interface Segments.................6-64

6.10.7 I/O Controller Interface Summary Flow ........................................................6-65

Chapter 7

Instruction Timing

7.1 Terminology and Conventions .............................................................................7-1

7.1.1 Definition of Terms..........................................................................................7-1

7.1.2 Timing Tables...................................................................................................7-3

7.2 Pipeline Description .............................................................................................7-4

7.2.1 Processor Core..................................................................................................7-4

7.2.1.1 Dispatch Stage Logic....................................................................................7-9

7.2.1.2 Integer Unit (IU).........................................................................................7-10

7.2.1.3 Floating-Point Unit (FPU)..........................................................................7-11

Contents

xiii

CONTENTS

7.2.1.4 Branch Processing Unit (BPU) ..................................................................7-12

7.2.1.5 Memory Subsystem Pipeline Stages..........................................................7-13

7.2.2 Memory Subsystem........................................................................................7-14

7.2.2.1 Memory Management Unit (MMU) ..........................................................7-14

7.2.2.2 Bus Interface Unit......................................................................................7-14

7.2.2.2.1 Write Queue...........................................................................................7-15

7.2.2.2.2 Read Queue............................................................................................7-15

7.2.2.2.3 Bus Interface Arbitration .......................................................................7-16

7.2.2.2.4 Bus Parking............................................................................................7-17

7.2.2.3 Cache Unit..................................................................................................7-17

7.2.2.3.1 Cache Arbiter.........................................................................................7-17

7.2.2.3.2 Cache Hit Timing...................................................................................7-17

7.2.2.3.3 Cache Miss Timing................................................................................7-18

7.2.2.3.4 Timings When the Processor Clock Frequency Equals the Bus Clock

Frequency ............................................................................................7-18

7.2.2.3.5 Timings When the Processor Clock Frequency Does Not Equal the Bus

Clock Frequency..................................................................................7-20

7.3 Pipeline Timing..................................................................................................7-22

7.3.1 Common Stages/BPU Pipeline Stages...........................................................7-23

7.3.1.1 Common Stages—Fetch Arbitration (FA) Stage.......................................7-23

7.3.1.2 Common Stages—Cache Arbitration (CARB) Stage................................7-24

7.3.1.3 Common Stages—Cache Access (CACC) Stage.......................................7-24

7.3.1.4 Common Stages—Dispatch (DS) Stage ....................................................7-25

7.3.1.4.1 Branch Dispatch.....................................................................................7-25

7.3.1.4.2 Integer Dispatch.....................................................................................7-25

7.3.1.4.3 Floating-Point Dispatch .........................................................................7-26

7.3.1.4.4 Synchronization Tags for the Precise Exception Model........................7-26

7.3.1.4.5 Dispatch Considerations Related to IU/FPU Synchronization..............7-28

7.3.2 BPU Pipeline Stages ......................................................................................7-29

7.3.2.1 Speculative Execution and Mispredict Recovery Mechanism...................7-29

7.3.2.2 Branch Pipeline Timing .............................................................................7-31

7.3.3 Integer Pipeline Stages...................................................................................7-35

7.3.3.1 Integer Pipeline—Integer Decode (ID) Stage............................................7-37

7.3.3.2 Integer Pipeline—Integer Execute (IE) Stage............................................7-38

7.3.3.2.1 IE Stage—ALU Instruction Operation ..................................................7-38

7.3.3.2.2 IE Stage—Basic Load and Store Instruction Operation ........................7-39

7.3.3.3 Integer Operations that Access the Memory Subsystem ...........................7-39

7.3.3.3.1 Integer Pipeline—CARB Stage .............................................................7-39

7.3.3.3.2 Integer and Floating-Point Store Buffer Stages (ISB and FPSB)..........7-40

7.3.3.3.3 Address Translation ...............................................................................7-40

7.3.3.3.4 Unaligned Load/Store Operations..........................................................7-40

7.3.3.3.5 Load/Store String/Multiple Operations..................................................7-41

7.3.3.3.6 Integer Pipeline—Cache Access (CACC) Stage ...................................7-41

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Number

Title

Page

Number

7.3.3.4 Integer Pipeline—Integer Writeback Stages (IWA and IWL)...................7-42

7.3.3.5 Integer Pipeline Instruction Timings..........................................................7-42

7.3.3.5.1 Arithmetic Instructions...........................................................................7-42

7.3.3.5.2 Boolean Logic Instruction Timings........................................................7-46

7.3.3.5.3 Rotate, Shift, and Mask Instruction Timings .........................................7-47

7.3.3.5.4 Condition Register (CR) Instruction Timings........................................7-49

7.3.3.5.5 Move to SPR (

mtspr

) Instruction Timings............................................7-51

7.3.3.5.6 Move to MSR (

mtmsr

) Instruction........................................................7-52

7.3.3.5.7 Move to Segment Register Instructions .................................................7-53

7.3.3.5.8 Move from Special Purpose Register (

mfspr

).......................................7-54

7.3.3.5.9 Move from Machine State Register (

mfmsr

) Instruction Timing .........7-55

7.3.3.5.10 Move from Segment Register Instruction Timing .................................7-55

7.3.3.5.11 System Call (

) and Return from Interrupt (

rfi

) Instruction Timings...7-56

7.3.3.5.12 Cache Instruction Timings .....................................................................7-56

7.3.3.5.13 Load Instruction Timing.........................................................................7-58

7.3.3.5.14 Load with Update Instruction Timing....................................................7-59

7.3.3.5.15 Load Multiple Word (

lmw

) and Load String Word Immediate (

lswi

)...7-60

7.3.3.5.16 Load String Word Indexed (

lswx

) and Load String and Compare Byte

Indexed (

lscbx

) Instruction Timing.....................................................7-61

7.3.3.5.17 Integer Store Instruction Timings...........................................................7-63

7.3.3.5.18 Store with Update Instruction Timing....................................................7-64

7.3.3.5.19 Floating-Point Store Instruction Timing ................................................7-64

7.3.3.5.20 Update-Form Floating-Point Store Instruction Timings........................7-66

7.3.3.5.21 Store Multiple Word (

stmw

) and Store String Word Immediate

(

stswi

) ..................................................................................................7-68

7.3.3.5.22 Store String Word Indexed (

stswx

) Instruction Timings.......................7-69

7.3.3.5.23 Store Conditional Word Indexed Instruction .........................................7-71

7.3.4 Floating-Point Pipeline Stages .......................................................................7-72

7.3.4.1 Floating-Point Decode Stage (FD).............................................................7-73

7.3.4.2 Floating-Point Multiply Stage (FPM) ........................................................7-74

7.3.4.3 Floating-Point Add Stage (FPA)................................................................7-74

7.3.4.4 Floating-Point Write-Back Stage (FWA)...................................................7-75

7.3.4.5 Floating-Point Pipeline Timing..................................................................7-75

7.3.4.5.1 Single-Precision Instructions..................................................................7-75

7.3.4.5.2 Double-Precision Instruction Timing.....................................................7-77

7.3.4.5.3 Floating-Point Move/Store Instruction Timing......................................7-80

7.3.4.5.4 Convert-to-Integer Instruction Timing...................................................7-80

7.3.4.5.5 Special Instructions Implemented in the FPU........................................7-80

7.3.4.5.6 Floating-Point Special-Case Number-Handling Stalls...........................7-81

7.3.4.5.7 Floating-Point Normalization Stalls.......................................................7-83

7.4 Execute Stage Delay Summary ..........................................................................7-84

Contents

CONTENTS

Chapter 8

Signal Descriptions

8.1 Signal Configuration............................................................................................8-2

8.2 Signal Descriptions ..............................................................................................8-3

8.2.1 Address Bus Arbitration Signals......................................................................8-3

8.2.1.1 Bus Request (

)—Output .........................................................................8-4

8.2.1.2 Bus Grant (

)—Input................................................................................8-4

8.2.1.3 Address Bus Busy (

ABB

) ............................................................................8-5

8.2.1.3.1 Address Bus Busy (

ABB

)—Output .........................................................8-5

8.2.1.3.2 Address Bus Busy (

ABB

)—Input............................................................8-5

8.2.2 Address Transfer Start Signals.........................................................................8-6

8.2.2.1 Transfer Start (

) .......................................................................................8-6

8.2.2.1.1 Transfer Start (

)—Output....................................................................8-6

8.2.2.1.2 Transfer Start (

)—Input.......................................................................8-6

8.2.2.2 Extended Address Transfer Start (

XATS

) ...................................................8-6

8.2.2.2.1 Extended Address Transfer Start (

XATS

)—Output................................8-7

8.2.2.2.2 Extended Address Transfer Start (

XATS

)—Input...................................8-7

8.2.3 Address Transfer Signals .................................................................................8-7

8.2.3.1 Address Bus (A0–A31)................................................................................8-7

8.2.3.1.1 Address Bus (A0–A31)—Output (Memory Operations).........................8-7

8.2.3.1.2 Address Bus (A0–A31)—Input (Memory Operations) ...........................8-8

8.2.3.1.3 Address Bus (A0–A31)—Output (I/O Controller Interface Operations).8-8

8.2.3.1.4 Address Bus (A0–A31)—Input (I/O Controller Interface Operations)...8-8

8.2.3.2 Address Bus Parity (AP0–AP3)...................................................................8-8

8.2.3.2.1 Address Bus Parity (AP0–AP3)—Output................................................8-9

8.2.3.2.2 Address Bus Parity (AP0–AP3)—Input ..................................................8-9

8.2.3.3 Address Parity Error (

APE

)—Output..........................................................8-9

8.2.4 Address Transfer Attribute Signals................................................................8-10

8.2.4.1 Transfer Type (TT0–TT4) .........................................................................8-10

8.2.4.1.1 Transfer Type (TT0–TT4)—Output ......................................................8-10

8.2.4.1.2 Transfer Type (TT0–TT3)—Input.........................................................8-10

8.2.4.2 Transfer Size (TSIZ0–TSIZ2)....................................................................8-12

8.2.4.2.1 Transfer Size (TSIZ0–TSIZ2)—Output.................................................8-12

8.2.4.2.2 Transfer Size (TSIZ0–TSIZ2)—Input...................................................8-13

8.2.4.3 Transfer Burst (

TBST

) ...............................................................................8-13

8.2.4.3.1 Transfer Burst (

TBST

)—Output............................................................8-13

8.2.4.3.2 Transfer Burst (

TBST

)—Input...............................................................8-14

8.2.4.4 Transfer Code (TC0–TC1)—Output..........................................................8-14

8.2.4.5 Cache Inhibit (

)—Output.......................................................................8-14

8.2.4.6 Write-Through (

)—Output ..................................................................8-15

8.2.4.7 Global (

GBL

).............................................................................................8-15

8.2.4.7.1 Global (

GBL

)—Output..........................................................................8-15

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8.2.4.7.2 Global (GBL

)—Input.............................................................................8-15

8.2.4.8 Cache Set Element (CSE0–CSE2)—Output..............................................8-15

8.2.4.9 High-Priority Snoop Request (HP_SNP_REQ

)........................................8-16

8.2.5 Address Transfer Termination Signals...........................................................8-16

8.2.5.1 Address Acknowledge (AACK

)—Input....................................................8-16

8.2.5.2 Address Retry (ARTRY

)............................................................................8-17

8.2.5.2.1 Address Retry (ARTRY

)—Output.........................................................8-17

8.2.5.2.2 Address Retry (ARTRY

)—Input ...........................................................8-18

8.2.5.3 Shared (SHD

).............................................................................................8-18

8.2.5.3.1 Shared (SHD

)—Output..........................................................................8-18

8.2.5.3.2 Shared (SHD

)—Input............................................................................8-19

8.2.6 Data Bus Arbitration Signals..........................................................................8-19

8.2.6.1 Data Bus Grant (DBG

)—Input ..................................................................8-19

8.2.6.2 Data Bus Write Only (DBWO

)—Input .....................................................8-20

8.2.6.3 Data Bus Busy (DBB

) ................................................................................8-20

8.2.6.3.1 Data Bus Busy (DBB

)—Output.............................................................8-20

8.2.6.3.2 Data Bus Busy (DBB

)—Input................................................................8-20

8.2.7 Data Transfer Signals.....................................................................................8-21

8.2.7.1 Data Bus (DH0–DH31, DL0–DL31) .........................................................8-21

8.2.7.1.1 Data Bus (DH0–DH31, DL0–DL31)—Output......................................8-22

8.2.7.1.2 Data Bus (DH0–DH31, DL0–DL31)—Input.........................................8-22

8.2.7.2 Data Bus Parity (DP0–DP7).......................................................................8-22

8.2.7.2.1 Data Bus Parity (DP0–DP7)—Output....................................................8-22

8.2.7.2.2 Data Bus Parity (DP0–DP7)—Input ......................................................8-23

8.2.7.3 Data Parity Error (DPE

)—Output..............................................................8-23

8.2.8 Data Transfer Termination Signals ................................................................8-23

8.2.8.1 Transfer Acknowledge (TA

)—Input..........................................................8-24

8.2.8.2 Data Retry (DRTRY

)—Input.....................................................................8-24

8.2.8.3 Transfer Error Acknowledge (TEA

)—Input..............................................8-25

8.2.9 System Status Signals.....................................................................................8-25

8.2.9.1 Interrupt (INT

)—Input...............................................................................8-25

8.2.9.2 Checkstop Input (CKSTP_IN

)—Input......................................................8-26

8.2.9.3 Checkstop Output (CKSTP_OUT

)—Output.............................................8-26

8.2.9.4 Reset Signals ..............................................................................................8-26

8.2.9.4.1 Hard Reset (HRESET

)—Input...............................................................8-27

8.2.9.4.2 Soft Reset (SRESET

)—Input.................................................................8-27

8.2.9.5 System Quiesced (SYS_QUIESC

).............................................................8-27

8.2.9.6 Resume (RESUME) ...................................................................................8-28

8.2.9.7 Quiesce Request (QUIESC_REQ).............................................................8-28

8.2.9.8 Reservation (RSRV

)—Output....................................................................8-28

8.2.9.9 Driver Mode (SC_DRIVE) ........................................................................8-29

8.2.10 COP/Scan Interface........................................................................................8-29

8.2.11 Clock Signals..................................................................................................8-30

Contents xvii

CONTENTS

8.2.11.1 Double-Speed Processor Clock (2X_PCLK)—Input ................................8-30

8.2.11.2 Clock Phase (PCLK_EN

)—Input .............................................................8-31

8.2.11.3 Bus Phase (BCLK_EN

)—Input.................................................................8-32

8.2.11.4 Real-Time Clock (RTC)—Input................................................................8-35

8.3 Clocking in a Multiprocessor System ................................................................8-35

Chapter 9

System Interface Operation

9.1 PowerPC 601 Microprocessor System Interface Overview.................................9-1

9.1.1 Operation of the On-Chip Cache......................................................................9-2

9.1.2 Operation of the Memory Unit for Loads and Stores ......................................9-4

9.1.3 Operation of the System Interface....................................................................9-4

9.1.4 I/O Controller Interface Accesses....................................................................9-5

9.2 Memory Access Protocol.....................................................................................9-6

9.2.1 Arbitration Signals...........................................................................................9-8

9.2.2 Address Pipelining and Split-Bus Transactions...............................................9-9

9.3 Address Bus Tenure...........................................................................................9-10

9.3.1 Address Bus Arbitration.................................................................................9-10

9.3.2 Address Transfer............................................................................................9-12

9.3.2.1 Address Bus Parity.....................................................................................9-13

9.3.2.2 Address Transfer Attribute Signals............................................................9-13

9.3.2.2.1 Transfer Type (TT0–TT4) Signals.........................................................9-13

9.3.2.2.2 Transfer Size (TSIZ0–TSIZ2) Signals...................................................9-14

9.3.2.3 Effect of Alignment in Data Transfers.......................................................9-15

9.3.2.3.1 Alignment of External Control Instructions...........................................9-17

9.3.2.4 Transfer Code (TC0–TC1) Signals............................................................9-18

9.3.3 Address Transfer Termination .......................................................................9-19

9.3.3.1 Address Retry Sources...............................................................................9-21

9.4 Data Bus Tenure.................................................................................................9-21

9.4.1 Data Bus Arbitration......................................................................................9-22

9.4.1.1 Using the DBB

Signal................................................................................9-22

9.4.2 Data Transfer..................................................................................................9-23

9.4.3 Data Transfer Termination.............................................................................9-24

9.4.3.1 Normal Single-Beat Termination...............................................................9-24

9.4.3.2 Data Transfer Termination Due to a Bus Error..........................................9-26

9.4.4 Memory Coherency—MESI Protocol............................................................9-28

9.5 Timing Examples ...............................................................................................9-30

9.6 Memory- vs. I/O-Mapped I/O Operations..........................................................9-37

9.6.1 I/O Controller Interface Transactions ............................................................9-39

9.6.1.1 Store Operations.........................................................................................9-40

9.6.1.2 Load Operations.........................................................................................9-40

xviii PowerPC 601 RISC Microprocessor User's Manual

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Paragraph

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Title

Page

Number

9.6.2 I/O Controller Interface Transaction Protocol Details ...................................9-41

9.6.2.1 Packet 0 ......................................................................................................9-42

9.6.2.2 Packet 1 ......................................................................................................9-43

9.6.3 I/O Reply Operations......................................................................................9-43

9.6.4 I/O Controller Interface Operation Timing ....................................................9-45

9.7 Interrupt, Checkstop, and Reset Signals.............................................................9-47

9.7.1 External Interrupt............................................................................................9-47

9.7.2 Checkstops......................................................................................................9-47

9.7.3 Reset Inputs....................................................................................................9-48

9.7.4 Soft Stop Control Signals...............................................................................9-48

9.8 Processor State Signals.......................................................................................9-48

9.8.1 Support for the lwarx/stwcx. Instruction Pair................................................9-48

9.9 IEEE 1149.1-Compatible Interface ....................................................................9-49

9.9.1 Deviations from the IEEE 1149.1 Boundary-Scan Specifications.................9-49

9.9.2 Additional Information about the IEEE 1149.1 Interface ..............................9-50

9.9.3 IEEE 1149.1 Interface Description.................................................................9-50

9.9.4 IEEE Interface Clock Requirements ..............................................................9-50

9.9.5 IEEE 1149.1 Interface Reset Requirements...................................................9-52

9.9.6 IEEE Interface Instruction Set........................................................................9-53

9.9.7 IEEE 1149.1 Interface Boundary-Scan Chain................................................9-53

9.10 Using DBWO

(Data Bus Write Only) ...............................................................9-60

Chapter 10

Instruction Set

10.1 Instruction Formats.............................................................................................10-1

10.1.1 Split-Field Notation........................................................................................10-1

10.1.2 Instruction Fields............................................................................................10-2

10.1.3 Notation and Conventions..............................................................................10-4

10.2 Instruction Set.....................................................................................................10-6

10.3 Instructions Not Implemented by the 601 ......................................................10-219

Appendix A

Instruction Set Listings

A.1 Complete Instruction List Sorted by Mnemonic.......................................A-1

A.2 Complete Instruction List Sorted by Opcode..........................................A-10

A.3 Instructions Grouped by Functional Categories......................................A-18

A.4 Complete Instruction List Sorted by Form..............................................A-28

Contents xix

CONTENTS

Appendix B

POWER Architecture Cross Reference

B.1 New Instructions, Formerly Supervisor-Level Instructions......................B–1

B.2 Newly Supervisor-Level Instructions.......................................................B–1

B.3 Reserved Bits in Instructions....................................................................B–2

B.4 Reserved Bits in Registers........................................................................B–2

B.5 Alignment Check......................................................................................B–2

B.6 Condition Register....................................................................................B–2

B.7 Inappropriate Use of LK and Rc bits........................................................B–3

B.8 BO Field....................................................................................................B–3

B.9 Branch Conditional to Count Register......................................................B–4

B.10 System Call/Supervisor Call.....................................................................B–4

B.11 Integer Exception Register (XER)............................................................B–4

B.12 Update Forms of Memory Access ............................................................B–4

B.13 Multiple Register Loads............................................................................B–5

B.14 Alignment for Load/Store Multiple..........................................................B–5

B.15 Load String Instructions............................................................................B–5

B.16 Synchronization ........................................................................................B–5

B.17 Move to/from SPR....................................................................................B–6

B.18 Effects of Exceptions on FPSCR Bits FR and FI .....................................B–6

B.19 Floating-Point Store Instructions..............................................................B–6

B.20 Move from FPSCR ...................................................................................B–6

B.21 Clearing Bytes in the Data Cache.............................................................B–7

B.22 Segment Register Instructions ..................................................................B–7

B.23 TLB Entry Invalidation.............................................................................B–7

B.24 Timing Facilities.......................................................................................B–7

B.24.1 Real-Time Clock...................................................................................B–7

B.24.2 Decrementer..........................................................................................B–8

B.25 Deleted Instructions..................................................................................B–8

B.26 POWER Instructions Supported by the PowerPC Architecture.............B–10

Appendix C

PowerPC Instructions Not Implemented

xx PowerPC 601 RISC Microprocessor User's Manual

CONTENTS

Paragraph

Number

Title

Page

Number

Appendix D

Classes of Instructions

D.1 Classes of Instructions...............................................................................D-1

D.1.1 Defined Instruction Class ......................................................................D-1

D.1.1.1 Invalid Instruction Forms ..................................................................D-2

D.1.2 Illegal Instruction Class.........................................................................D-2

D.1.3 Reserved Instructions ............................................................................D-3

Appendix E

Multiple-Precision Shifts

E.1 Multiple-Precision Shift Examples ...........................................................E-1

Appendix F

Floating-Point Models

F.1 Conversion from Floating-Point Number to Signed Fixed-Point

Integer Word ........................................................................................... F-1

F.2 Conversion from Floating-Point Number to Unsigned Fixed-Point

Integer Word ........................................................................................... F-1

F.3 Floating-Point Models............................................................................... F-2

F.3.1 Floating-Point Round to Single-Precision Model ................................. F-2

F.3.2 Floating-Point Convert to Integer Model .............................................. F-6

Appendix G

Synchronization Programming Examples

G.1 General Information..................................................................................G-1

G.2 Synchronization Primitives.......................................................................G-2

G.2.1 Fetch and No-Op ...................................................................................G-2

G.2.2 Fetch and Store......................................................................................G-2

G.2.3 Fetch and Add........................................................................................G-3

G.2.4 Fetch and AND......................................................................................G-3

G.2.5 Test and Set ...........................................................................................G-3

G.3 Compare and Swap....................................................................................G-4

G.4 Lock Acquisition and Release...................................................................G-4

G.5 List Insertion .............................................................................................G-5

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NXP MPC601 User guide

NXP MPC601 User guide

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