xvi PowerPC 601 RISC Microprocessor User's Manual
CONTENTS
Paragraph
Number
Title
Page
Number
8.2.4.7.2 Global (GBL
)—Input.............................................................................8-15
8.2.4.8 Cache Set Element (CSE0–CSE2)—Output..............................................8-15
8.2.4.9 High-Priority Snoop Request (HP_SNP_REQ
)........................................8-16
8.2.5 Address Transfer Termination Signals...........................................................8-16
8.2.5.1 Address Acknowledge (AACK
)—Input....................................................8-16
8.2.5.2 Address Retry (ARTRY
)............................................................................8-17
8.2.5.2.1 Address Retry (ARTRY
)—Output.........................................................8-17
8.2.5.2.2 Address Retry (ARTRY
)—Input ...........................................................8-18
8.2.5.3 Shared (SHD
).............................................................................................8-18
8.2.5.3.1 Shared (SHD
)—Output..........................................................................8-18
8.2.5.3.2 Shared (SHD
)—Input............................................................................8-19
8.2.6 Data Bus Arbitration Signals..........................................................................8-19
8.2.6.1 Data Bus Grant (DBG
)—Input ..................................................................8-19
8.2.6.2 Data Bus Write Only (DBWO
)—Input .....................................................8-20
8.2.6.3 Data Bus Busy (DBB
) ................................................................................8-20
8.2.6.3.1 Data Bus Busy (DBB
)—Output.............................................................8-20
8.2.6.3.2 Data Bus Busy (DBB
)—Input................................................................8-20
8.2.7 Data Transfer Signals.....................................................................................8-21
8.2.7.1 Data Bus (DH0–DH31, DL0–DL31) .........................................................8-21
8.2.7.1.1 Data Bus (DH0–DH31, DL0–DL31)—Output......................................8-22
8.2.7.1.2 Data Bus (DH0–DH31, DL0–DL31)—Input.........................................8-22
8.2.7.2 Data Bus Parity (DP0–DP7).......................................................................8-22
8.2.7.2.1 Data Bus Parity (DP0–DP7)—Output....................................................8-22
8.2.7.2.2 Data Bus Parity (DP0–DP7)—Input ......................................................8-23
8.2.7.3 Data Parity Error (DPE
)—Output..............................................................8-23
8.2.8 Data Transfer Termination Signals ................................................................8-23
8.2.8.1 Transfer Acknowledge (TA
)—Input..........................................................8-24
8.2.8.2 Data Retry (DRTRY
)—Input.....................................................................8-24
8.2.8.3 Transfer Error Acknowledge (TEA
)—Input..............................................8-25
8.2.9 System Status Signals.....................................................................................8-25
8.2.9.1 Interrupt (INT
)—Input...............................................................................8-25
8.2.9.2 Checkstop Input (CKSTP_IN
)—Input......................................................8-26
8.2.9.3 Checkstop Output (CKSTP_OUT
)—Output.............................................8-26
8.2.9.4 Reset Signals ..............................................................................................8-26
8.2.9.4.1 Hard Reset (HRESET
)—Input...............................................................8-27
8.2.9.4.2 Soft Reset (SRESET
)—Input.................................................................8-27
8.2.9.5 System Quiesced (SYS_QUIESC
).............................................................8-27
8.2.9.6 Resume (RESUME) ...................................................................................8-28
8.2.9.7 Quiesce Request (QUIESC_REQ).............................................................8-28
8.2.9.8 Reservation (RSRV
)—Output....................................................................8-28
8.2.9.9 Driver Mode (SC_DRIVE) ........................................................................8-29
8.2.10 COP/Scan Interface........................................................................................8-29
8.2.11 Clock Signals..................................................................................................8-30