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NXP KW20Z, KW30Z, KW40Z Reference guide

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MKW40Z/30Z/20Z Reference Manual
Bluetooth® Low Energy and IEEE 802.15.4 System on a Chip (SoC)
Reference Manual
Document Number: MKW40Z160RM
Rev. 1.3, 05/2018
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Contents
Section number Title Page
Chapter 1
Introduction
1.1 Introduction...................................................................................................................................................................61
1.2 Features Overview........................................................................................................................................................ 62
1.3 Feature Summary..........................................................................................................................................................65
1.4 Block Diagram..............................................................................................................................................................68
Chapter 2
Signal Multiplexing and Signal Descriptions
2.1 Pinouts.......................................................................................................................................................................... 69
2.2 Signal Multiplexing and Pin Assignments....................................................................................................................70
2.3 KW40Z SoC Signal Descriptions.................................................................................................................................73
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................77
3.2 Module to module interconnects...................................................................................................................................77
3.2.1 Module to Module Interconnects................................................................................................................. 77
3.3 Core modules................................................................................................................................................................ 80
3.3.1 ARM Cortex-M0+ core configuration......................................................................................................... 80
3.3.1.1 ARM Cortex M0+ core ...........................................................................................................80
3.3.1.2 Buses, Interconnects, and Interfaces........................................................................................81
3.3.1.3 System Tick Timer...................................................................................................................82
3.3.1.4 Debug Facilities....................................................................................................................... 82
3.3.1.5 Core Privilege Levels...............................................................................................................82
3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration......................................................................82
3.3.2.1 Interrupt priority levels............................................................................................................ 83
3.3.2.2 Non-maskable interrupt............................................................................................................83
3.3.2.3 Interrupt channel assignments..................................................................................................83
3.3.2.4 Serialization of memory operations when clearing interrupt flags..........................................85
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3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................85
3.3.3.1 Wake-up sources......................................................................................................................86
3.4 System modules............................................................................................................................................................ 87
3.4.1 SIM configuration........................................................................................................................................87
3.4.2 System mode controller (SMC) configuration.............................................................................................87
3.4.3 PMC configuration.......................................................................................................................................88
3.4.4 DCDC configuration....................................................................................................................................89
3.4.5 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................90
3.4.5.1 LLWU interrupt....................................................................................................................... 91
3.4.5.2 Wake-up Sources..................................................................................................................... 91
3.4.6 MCM configuration..................................................................................................................................... 92
3.4.7 Crossbar-light switch configuration.............................................................................................................93
3.4.7.1 Crossbar-Light Switch Master Assignments............................................................................93
3.4.7.2 Crossbar Switch Slave Assignments........................................................................................94
3.4.8 Peripheral bridge configuration................................................................................................................... 94
3.4.8.1 Number of peripheral bridges.................................................................................................. 94
3.4.8.2 Memory maps.......................................................................................................................... 95
3.4.9 DMA request multiplexer configuration......................................................................................................95
3.4.9.1 DMA MUX Request Sources.................................................................................................. 95
3.4.9.2 DMA transfers via PIT trigger.................................................................................................97
3.4.10 DMA Controller Configuration................................................................................................................... 97
3.4.11 Computer operating properly (COP) watchdog configuration.................................................................... 98
3.4.11.1 COP clocks...............................................................................................................................99
3.4.11.2 COP watchdog operation......................................................................................................... 99
3.4.11.3 Clock Gating............................................................................................................................ 101
3.5 Clock modules.............................................................................................................................................................. 101
3.5.1 MCG configuration......................................................................................................................................101
3.5.1.1 MCG Instantiation Information............................................................................................... 102
3.5.1.2 MCG FLL modes.....................................................................................................................102
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3.5.2 32kHz OSC Configuration...........................................................................................................................102
3.5.2.1 32kHz OSC Instantiation Information..................................................................................... 103
3.5.3 Reference Oscillator Configuration............................................................................................................. 103
3.5.3.1 Reference Oscillator Instantiation Information........................................................................104
3.6 Memories and memory interfaces.................................................................................................................................105
3.6.1 Flash Memory Configuration.......................................................................................................................105
3.6.1.1 Flash Memory Sizes.................................................................................................................105
3.6.1.2 Flash Memory Map..................................................................................................................105
3.6.1.3 Flash Security...........................................................................................................................106
3.6.1.4 Flash Modes............................................................................................................................. 106
3.6.1.5 Erase All Flash Contents..........................................................................................................106
3.6.1.6 FTFA_FOPT Register..............................................................................................................106
3.6.2 Flash Memory Controller Configuration..................................................................................................... 107
3.6.3 SRAM Configuration...................................................................................................................................107
3.6.3.1 SRAM Sizes.............................................................................................................................108
3.6.3.2 SRAM Ranges..........................................................................................................................108
3.6.3.3 SRAM retention in low power modes......................................................................................109
3.6.4 System Register File Configuration.............................................................................................................109
3.6.4.1 System Register file................................................................................................................. 110
3.7 Analog...........................................................................................................................................................................110
3.7.1 Analog reference options............................................................................................................................. 110
3.7.2 16-bit SAR ADC configuration................................................................................................................... 111
3.7.2.1 ADC Instantiation Information................................................................................................ 111
3.7.2.2 DMA Support on ADC............................................................................................................ 112
3.7.2.3 ADC0 Connections/Channel Assignment................................................................................112
3.7.2.4 ADC analog supply and reference connections....................................................................... 113
3.7.2.5 Alternate clock......................................................................................................................... 113
3.7.3 CMP Configuration......................................................................................................................................113
3.7.3.1 CMP Instantiation Information................................................................................................ 114
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3.7.3.2 CMP input connections............................................................................................................115
3.7.3.3 CMP external references..........................................................................................................115
3.7.3.4 CMP trigger mode....................................................................................................................115
3.7.4 12-bit DAC configuration............................................................................................................................ 116
3.7.4.1 12-bit DAC Instantiation Information......................................................................................116
3.7.4.2 12-bit DAC Output...................................................................................................................116
3.7.4.3 12-bit DAC Analog Supply Connections.................................................................................116
3.7.4.4 12-bit DAC Reference............................................................................................................. 117
3.8 Radio.............................................................................................................................................................................117
3.8.1 Radio module configuration.........................................................................................................................117
3.8.1.1 Radio Overview....................................................................................................................... 118
3.9 Timers........................................................................................................................................................................... 119
3.9.1 Timer/TPM Configuration........................................................................................................................... 119
3.9.1.1 TPM Instantiation Information................................................................................................ 119
3.9.1.2 Clock Options.......................................................................................................................... 120
3.9.1.3 Trigger Options........................................................................................................................120
3.9.1.4 Global timebase........................................................................................................................121
3.9.1.5 Interrupts.................................................................................................................................. 121
3.9.2 PIT Configuration........................................................................................................................................ 121
3.9.2.1 PIT/DMA Periodic Trigger Assignments ............................................................................... 122
3.9.2.2 PIT/ADC Triggers....................................................................................................................122
3.9.2.3 PIT/FTM Triggers....................................................................................................................122
3.9.2.4 PIT/DAC Triggers....................................................................................................................123
3.9.3 Low-power timer configuration...................................................................................................................123
3.9.3.1 LPTMR Instantiation Information........................................................................................... 123
3.9.3.2 LPTMR pulse counter input options........................................................................................124
3.9.3.3 LPTMR prescaler/glitch filter clocking options...................................................................... 124
3.9.4 RTC configuration....................................................................................................................................... 124
3.9.4.1 RTC Instantiation Information.................................................................................................125
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3.9.4.2 RTC_CLKOUT options...........................................................................................................125
3.10 Communication interfaces............................................................................................................................................ 126
3.10.1 SPI configuration......................................................................................................................................... 126
3.10.1.1 SPI Instantiation Information...................................................................................................126
3.10.2 I2C Configuration........................................................................................................................................ 127
3.10.2.1 I2C Instantiation Information...................................................................................................127
3.10.3 UART Configuration................................................................................................................................... 128
3.10.3.1 UART0 overview.....................................................................................................................128
3.11 Human-machine interfaces (HMI)................................................................................................................................128
3.11.1 GPIO Configuration.....................................................................................................................................129
3.11.1.1 GPIO Instantiation Information............................................................................................... 129
3.11.1.2 Port control and interrupt summary......................................................................................... 129
3.11.1.3 GPIO accessibility in the memory map................................................................................... 130
3.11.2 TSI Configuration........................................................................................................................................ 131
3.11.2.1 TSI Instantiation Information...................................................................................................131
3.11.2.2 TSI Interrupts........................................................................................................................... 131
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................133
4.2 System memory map.....................................................................................................................................................133
4.3 Flash Memory Map.......................................................................................................................................................134
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................134
4.4 SRAM memory map.....................................................................................................................................................135
4.5 Bit Manipulation Engine...............................................................................................................................................135
4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................135
4.6.1 Read-after-write sequence and required serialization of memory operations..............................................136
4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map.............................................................................................. 136
4.6.3 Modules Restricted Access in User Mode................................................................................................... 140
4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................140
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Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................143
5.2 Programming model......................................................................................................................................................143
5.3 High-Level device clocking diagram............................................................................................................................143
5.4 Clock definitions...........................................................................................................................................................144
5.4.1 Device clock summary.................................................................................................................................145
5.5 Internal clocking requirements..................................................................................................................................... 146
5.5.1 Clock divider values after reset....................................................................................................................147
5.5.2 VLPR mode clocking...................................................................................................................................147
5.6 Clock Gating.................................................................................................................................................................148
5.7 Module clocks...............................................................................................................................................................148
5.7.1 PMC 1-kHz LPO clock................................................................................................................................149
5.7.2 COP clocking............................................................................................................................................... 150
5.7.3 RTC clocking............................................................................................................................................... 150
5.7.4 LPTMR clocking..........................................................................................................................................151
5.7.5 TPM clocking...............................................................................................................................................151
5.7.6 UART clocking............................................................................................................................................152
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................153
6.2 Reset..............................................................................................................................................................................153
6.2.1 Power-on reset (POR).................................................................................................................................. 154
6.2.2 System reset sources.................................................................................................................................... 154
6.2.2.1 External pin reset (RESET_b)..................................................................................................154
6.2.2.2 Low-voltage detect (LVD).......................................................................................................155
6.2.2.3 Computer operating properly (COP) watchdog timer..............................................................156
6.2.2.4 Low leakage wakeup (LLWU)................................................................................................ 156
6.2.2.5 Multipurpose clock generator loss-of-clock (LOC).................................................................156
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6.2.2.6 Stop mode acknowledge error (SACKERR) .......................................................................... 157
6.2.2.7 Software reset (SW).................................................................................................................157
6.2.2.8 Lockup reset (LOCKUP)......................................................................................................... 157
6.2.2.9 MDM-AP system reset request................................................................................................157
6.2.3 MCU resets.................................................................................................................................................. 158
6.2.3.1 POR Only ................................................................................................................................158
6.2.3.2 Chip POR not VLLS ...............................................................................................................158
6.2.3.3 Chip POR ................................................................................................................................ 158
6.2.3.4 Chip Reset not VLLS ..............................................................................................................158
6.2.3.5 Chip Reset not VLLS3/2..........................................................................................................158
6.2.3.6 Early Chip Reset ..................................................................................................................... 159
6.2.3.7 Chip Reset ...............................................................................................................................159
6.2.4 RESET_b pin .............................................................................................................................................. 159
6.3 Boot...............................................................................................................................................................................159
6.3.1 Boot sources.................................................................................................................................................160
6.3.2 FOPT boot options.......................................................................................................................................160
6.3.3 Boot sequence.............................................................................................................................................. 161
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................163
7.2 Clocking Modes............................................................................................................................................................163
7.2.1 Partial Stop...................................................................................................................................................163
7.2.2 DMA Wakeup..............................................................................................................................................164
7.2.3 Compute Operation......................................................................................................................................165
7.2.4 Peripheral Doze............................................................................................................................................166
7.2.5 Clock Gating................................................................................................................................................ 167
7.3 Power modes.................................................................................................................................................................167
7.4 Entering and exiting power modes............................................................................................................................... 169
7.5 Module Operation in Low Power Modes......................................................................................................................170
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Chapter 8
Security
8.1 Introduction...................................................................................................................................................................175
8.2 Flash security................................................................................................................................................................ 175
8.3 Security interactions with other modules......................................................................................................................175
8.3.1 Security interactions with Debug.................................................................................................................176
8.3.2 Firmware Distribution Protection ............................................................................................................... 176
8.4 Security Peripherals...................................................................................................................................................... 176
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................177
9.2 Debug port pin descriptions..........................................................................................................................................177
9.3 SWD status and control registers..................................................................................................................................177
9.3.1 MDM-AP Control Register..........................................................................................................................179
9.3.2 MDM-AP Status Register............................................................................................................................ 181
9.4 Debug Resets................................................................................................................................................................ 182
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................183
9.6 Debug in low-power modes..........................................................................................................................................183
9.7 Debug and security....................................................................................................................................................... 184
Chapter 10
Port control and interrupt (PORT)
10.1 Introduction...................................................................................................................................................................185
10.2 Overview.......................................................................................................................................................................185
10.2.1 Features........................................................................................................................................................ 185
10.2.2 Modes of operation...................................................................................................................................... 186
10.2.2.1 Run mode................................................................................................................................. 186
10.2.2.2 Wait mode................................................................................................................................186
10.2.2.3 Stop mode................................................................................................................................ 186
10.2.2.4 Debug mode............................................................................................................................. 186
10.3 External signal description............................................................................................................................................186
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10.4 Detailed signal description............................................................................................................................................187
10.5 Memory map and register definition.............................................................................................................................187
10.5.1
Pin Control Register n (PORTx_PCRn).......................................................................................................191
10.5.2
Global Pin Control Low Register (PORTx_GPCLR)..................................................................................194
10.5.3
Global Pin Control High Register (PORTx_GPCHR).................................................................................194
10.5.4
Interrupt Status Flag Register (PORTx_ISFR)............................................................................................ 195
10.6 Functional description...................................................................................................................................................195
10.6.1 Pin control....................................................................................................................................................195
10.6.2 Global pin control........................................................................................................................................ 196
10.6.3 External interrupts........................................................................................................................................196
Chapter 11
System Integration Module (SIM)
11.1 Introduction...................................................................................................................................................................199
11.1.1 Features........................................................................................................................................................ 199
11.2 Memory map and register definition.............................................................................................................................199
11.2.1 System Options Register 1 (SIM_SOPT1).................................................................................................. 201
11.2.2 System Options Register 2 (SIM_SOPT2).................................................................................................. 202
11.2.3 System Options Register 4 (SIM_SOPT4).................................................................................................. 203
11.2.4 System Options Register 5 (SIM_SOPT5).................................................................................................. 205
11.2.5 System Options Register 7 (SIM_SOPT7).................................................................................................. 206
11.2.6 System Device Identification Register (SIM_SDID)...................................................................................208
11.2.7 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................209
11.2.8 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................211
11.2.9 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................214
11.2.10 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................216
11.2.11 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................217
11.2.12 Flash Configuration Register 1 (SIM_FCFG1)........................................................................................... 218
11.2.13 Flash Configuration Register 2 (SIM_FCFG2)........................................................................................... 220
11.2.14 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................221
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11.2.15 Unique Identification Register Mid Low (SIM_UIDML)........................................................................... 221
11.2.16 Unique Identification Register Low (SIM_UIDL)...................................................................................... 222
11.2.17 COP Control Register (SIM_COPC)........................................................................................................... 222
11.2.18 Service COP (SIM_SRVCOP).....................................................................................................................224
Chapter 12
System Mode Controller (SMC)
12.1 Introduction...................................................................................................................................................................225
12.2 Modes of operation....................................................................................................................................................... 225
12.3 Memory map and register descriptions.........................................................................................................................227
12.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................228
12.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................229
12.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................230
12.3.4 Power Mode Status register (SMC_PMSTAT)........................................................................................... 232
12.4 Functional description...................................................................................................................................................232
12.4.1 Power mode transitions................................................................................................................................232
12.4.2 Power mode entry/exit sequencing.............................................................................................................. 235
12.4.2.1 Stop mode entry sequence........................................................................................................236
12.4.2.2 Stop mode exit sequence..........................................................................................................236
12.4.2.3 Aborted stop mode entry..........................................................................................................237
12.4.2.4 Transition to wait modes..........................................................................................................237
12.4.2.5 Transition from stop modes to Debug mode............................................................................237
12.4.3 Run modes....................................................................................................................................................237
12.4.3.1 RUN mode............................................................................................................................... 238
12.4.3.2 Very-Low Power Run (VLPR) mode...................................................................................... 238
12.4.4 Wait modes.................................................................................................................................................. 239
12.4.4.1 WAIT mode............................................................................................................................. 239
12.4.4.2 Very-Low-Power Wait (VLPW) mode....................................................................................239
12.4.5 Stop modes...................................................................................................................................................240
12.4.5.1 STOP mode..............................................................................................................................240
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12.4.5.2 Very-Low-Power Stop (VLPS) mode......................................................................................241
12.4.5.3 Low-Leakage Stop (LLSx) modes...........................................................................................241
12.4.5.4 Very-Low-Leakage Stop (VLLSx) modes...............................................................................242
12.4.6 Debug in low power modes......................................................................................................................... 243
Chapter 13
Power Management Controller (PMC)
13.1 Introduction...................................................................................................................................................................245
13.2 Features.........................................................................................................................................................................245
13.3 Low-voltage detect (LVD) system................................................................................................................................245
13.3.1 LVD reset operation.....................................................................................................................................246
13.3.2 LVD interrupt operation...............................................................................................................................246
13.3.3 Low-voltage warning (LVW) interrupt operation....................................................................................... 246
13.4 I/O retention..................................................................................................................................................................247
13.5 Memory map and register descriptions.........................................................................................................................247
13.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................ 248
13.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................ 249
13.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................250
Chapter 14
DCDC Converter (DCDC)
14.1 About this module.........................................................................................................................................................253
14.1.1 Introduction..................................................................................................................................................253
14.1.2 Features........................................................................................................................................................ 253
14.1.3 Block diagram..............................................................................................................................................254
14.1.4 Configurations..............................................................................................................................................254
14.1.5 Functional Description.................................................................................................................................255
14.1.6 Application Guideline..................................................................................................................................256
14.2 Memory map and register definition.............................................................................................................................257
14.2.1 Register Reset.............................................................................................................................................. 257
14.2.2 DCDC REGISTER 0 (DCDC_REG0).........................................................................................................258
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14.2.3 DCDC REGISTER 1 (DCDC_REG1).........................................................................................................261
14.2.4 DCDC REGISTER 2 (DCDC_REG2).........................................................................................................263
14.2.5 DCDC REGISTER 3 (DCDC_REG3).........................................................................................................265
14.2.6 DCDC REGISTER 4 (DCDC_REG4).........................................................................................................268
14.2.7 DCDC REGISTER 6 (DCDC_REG6).........................................................................................................269
14.2.8 DCDC REGISTER 7 (DCDC_REG7).........................................................................................................270
Chapter 15
Low-Leakage Wakeup Unit (LLWU)
15.1 Introduction...................................................................................................................................................................273
15.1.1 Features........................................................................................................................................................ 273
15.1.2 Modes of operation...................................................................................................................................... 274
15.1.2.1 LLS mode.................................................................................................................................274
15.1.2.2 VLLS modes............................................................................................................................ 274
15.1.2.3 Non-low leakage modes...........................................................................................................274
15.1.2.4 Debug mode............................................................................................................................. 274
15.1.3 Block diagram..............................................................................................................................................275
15.2 LLWU signal descriptions............................................................................................................................................ 276
15.3 Memory map/register definition................................................................................................................................... 276
15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................277
15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................278
15.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................279
15.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................280
15.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................ 281
15.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................283
15.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................285
15.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................286
15.3.9 LLWU Pin Filter 1 register (LLWU_FILT1).............................................................................................. 288
15.3.10 LLWU Pin Filter 2 register (LLWU_FILT2).............................................................................................. 289
15.4 Functional description...................................................................................................................................................290
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15.4.1 LLS mode.....................................................................................................................................................291
15.4.2 VLLS modes................................................................................................................................................ 291
15.4.3 Initialization................................................................................................................................................. 291
Chapter 16
Reset Control Module (RCM)
16.1 Introduction...................................................................................................................................................................293
16.2 Reset memory map and register descriptions............................................................................................................... 293
16.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................ 294
16.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................ 295
16.2.3 Reset Pin Filter Control register (RCM_RPFC).......................................................................................... 296
16.2.4 Reset Pin Filter Width register (RCM_RPFW)........................................................................................... 297
Chapter 17
Bit Manipulation Engine (BME)
17.1 Introduction...................................................................................................................................................................299
17.1.1 Overview......................................................................................................................................................300
17.1.2 Features........................................................................................................................................................ 301
17.1.3 Modes of operation...................................................................................................................................... 301
17.2 Memory map and register definition.............................................................................................................................301
17.3 Functional description...................................................................................................................................................302
17.3.1 BME decorated stores.................................................................................................................................. 302
17.3.1.1 Decorated store logical AND (AND).......................................................................................304
17.3.1.2 Decorated store logical OR (OR).............................................................................................305
17.3.1.3 Decorated store logical XOR (XOR).......................................................................................306
17.3.1.4 Decorated store bit field insert (BFI)....................................................................................... 307
17.3.2 BME decorated loads...................................................................................................................................309
17.3.2.1 Decorated load: load-and-clear 1 bit (LAC1).......................................................................... 312
17.3.2.2 Decorated Load: Load-and-Set 1 Bit (LAS1)..........................................................................313
17.3.2.3 Decorated load unsigned bit field extract (UBFX).................................................................. 314
17.3.3 Additional details on decorated addresses and GPIO accesses....................................................................315
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17.4 Application information................................................................................................................................................316
Chapter 18
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................319
18.1.1 Features........................................................................................................................................................ 319
18.2 Memory map/register descriptions............................................................................................................................... 319
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................320
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................ 321
18.2.3 Platform Control Register (MCM_PLACR)................................................................................................321
18.2.4 Compute Operation Control Register (MCM_CPO)................................................................................... 324
Chapter 19
Micro Trace Buffer (MTB)
19.1 Introduction...................................................................................................................................................................327
19.1.1 Overview......................................................................................................................................................327
19.1.2 Features........................................................................................................................................................ 330
19.1.3 Modes of operation...................................................................................................................................... 331
19.2 External signal description............................................................................................................................................331
19.3 Memory map and register definition.............................................................................................................................332
19.3.1 MTB_RAM Memory Map...........................................................................................................................332
19.3.1.1 MTB Position Register (MTB_POSITION)............................................................................334
19.3.1.2 MTB Master Register (MTB_MASTER)................................................................................336
19.3.1.3 MTB Flow Register (MTB_FLOW)........................................................................................337
19.3.1.4 MTB Base Register (MTB_BASE)......................................................................................... 339
19.3.1.5 Integration Mode Control Register (MTB_MODECTRL)......................................................340
19.3.1.6 Claim TAG Set Register (MTB_TAGSET).............................................................................340
19.3.1.7 Claim TAG Clear Register (MTB_TAGCLEAR)...................................................................341
19.3.1.8 Lock Access Register (MTB_LOCKACCESS)...................................................................... 341
19.3.1.9 Lock Status Register (MTB_LOCKSTAT)............................................................................. 342
19.3.1.10 Authentication Status Register (MTB_AUTHSTAT)............................................................. 342
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19.3.1.11 Device Architecture Register (MTB_DEVICEARCH)...........................................................343
19.3.1.12 Device Configuration Register (MTB_DEVICECFG)............................................................343
19.3.1.13 Device Type Identifier Register (MTB_DEVICETYPID)...................................................... 344
19.3.1.14
Peripheral ID Register (MTB_PERIPHIDn)........................................................................... 344
19.3.1.15
Component ID Register (MTB_COMPIDn)............................................................................345
19.3.2 MTB_DWT Memory Map...........................................................................................................................345
19.3.2.1 MTB DWT Control Register (MTB_DWT_CTRL)................................................................346
19.3.2.2
MTB_DWT Comparator Register (MTB_DWT_COMPn).....................................................347
19.3.2.3
MTB_DWT Comparator Mask Register (MTB_DWT_MASKn)...........................................348
19.3.2.4 MTB_DWT Comparator Function Register 0 (MTB_DWT_FCT0)...................................... 349
19.3.2.5 MTB_DWT Comparator Function Register 1 (MTB_DWT_FCT1)...................................... 351
19.3.2.6 MTB_DWT Trace Buffer Control Register (MTB_DWT_TBCTRL)....................................352
19.3.2.7 Device Configuration Register (MTB_DWT_DEVICECFG).................................................354
19.3.2.8 Device Type Identifier Register (MTB_DWT_DEVICETYPID)...........................................354
19.3.2.9
Peripheral ID Register (MTB_DWT_PERIPHIDn)................................................................ 355
19.3.2.10
Component ID Register (MTB_DWT_COMPIDn)................................................................ 355
19.3.3 System ROM Memory Map.........................................................................................................................355
19.3.3.1
Entry (ROM_ENTRYn)...........................................................................................................357
19.3.3.2 End of Table Marker Register (ROM_TABLEMARK)..........................................................358
19.3.3.3 System Access Register (ROM_SYSACCESS)......................................................................358
19.3.3.4
Peripheral ID Register (ROM_PERIPHIDn)...........................................................................359
19.3.3.5
Component ID Register (ROM_COMPIDn)........................................................................... 359
Chapter 20
Crossbar Switch Lite (AXBS-Lite)
20.1 Introduction...................................................................................................................................................................361
20.1.1 Features........................................................................................................................................................ 361
20.2 Memory Map / Register Definition...............................................................................................................................361
20.3 Functional Description..................................................................................................................................................362
20.3.1 General operation.........................................................................................................................................362
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20.3.2 Arbitration....................................................................................................................................................363
20.3.2.1 Arbitration during undefined length bursts..............................................................................363
20.3.2.2 Fixed-priority operation........................................................................................................... 363
20.3.2.3 Round-robin priority operation................................................................................................ 364
20.4 Initialization/application information........................................................................................................................... 364
Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Introduction...................................................................................................................................................................365
21.1.1 Features........................................................................................................................................................ 365
21.1.2 General operation.........................................................................................................................................365
21.2 Memory map/register definition................................................................................................................................... 366
21.2.1 Master Privilege Register A (AIPS_MPRA)............................................................................................... 366
21.2.2
Peripheral Access Control Register (AIPS_PACRn)...................................................................................368
21.2.3
Peripheral Access Control Register (AIPS_PACRn)...................................................................................374
21.3 Functional description...................................................................................................................................................378
21.3.1 Access support............................................................................................................................................. 378
Chapter 22
Direct Memory Access Multiplexer (DMAMUX)
22.1 Introduction...................................................................................................................................................................379
22.1.1 Overview......................................................................................................................................................379
22.1.2 Features........................................................................................................................................................ 380
22.1.3 Modes of operation...................................................................................................................................... 380
22.2 External signal description............................................................................................................................................381
22.3 Memory map/register definition................................................................................................................................... 381
22.3.1
Channel Configuration register (DMAMUXx_CHCFGn).......................................................................... 381
22.4 Functional description...................................................................................................................................................382
22.4.1 DMA channels with periodic triggering capability......................................................................................383
22.4.2 DMA channels with no triggering capability...............................................................................................385
22.4.3 Always-enabled DMA sources.................................................................................................................... 385
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22.5 Initialization/application information........................................................................................................................... 386
22.5.1 Reset.............................................................................................................................................................386
22.5.2 Enabling and configuring sources................................................................................................................386
Chapter 23
DMA Controller Module
23.1 Introduction...................................................................................................................................................................389
23.1.1 Overview......................................................................................................................................................389
23.1.2 Features........................................................................................................................................................ 390
23.2 DMA Transfer Overview..............................................................................................................................................391
23.3 Memory Map/Register Definition.................................................................................................................................392
23.3.1
Source Address Register (DMA_SARn)..................................................................................................... 393
23.3.2
Destination Address Register (DMA_DARn)............................................................................................. 394
23.3.3
DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................395
23.3.4
DMA Control Register (DMA_DCRn)........................................................................................................397
23.4 Functional Description..................................................................................................................................................401
23.4.1 Transfer requests (Cycle-Steal and Continuous modes)..............................................................................401
23.4.2 Channel initialization and startup................................................................................................................ 402
23.4.2.1 Channel prioritization.............................................................................................................. 402
23.4.2.2 Programming the DMA Controller Module.............................................................................402
23.4.3 Dual-Address Data Transfer Mode..............................................................................................................403
23.4.4 Advanced Data Transfer Controls: Auto-Alignment...................................................................................404
23.4.5 Termination..................................................................................................................................................405
Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................407
24.1.1 Features........................................................................................................................................................ 407
24.1.2 Modes of Operation..................................................................................................................................... 409
24.2 External Signal Description.......................................................................................................................................... 409
24.3 Memory Map/Register Definition.................................................................................................................................410
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24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................410
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................412
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................413
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................414
24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................415
24.3.5 MCG Control 6 Register (MCG_C6)...........................................................................................................415
24.3.6 MCG Status Register (MCG_S).................................................................................................................. 416
24.3.7 MCG Status and Control Register (MCG_SC)............................................................................................417
24.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................ 418
24.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................419
24.3.10 MCG Control 7 Register (MCG_C7)...........................................................................................................419
24.3.11 MCG Control 8 Register (MCG_C8)...........................................................................................................420
24.3.12 MCG Control 12 Register (MCG_C12).......................................................................................................421
24.3.12 MCG Status 2 Register (MCG_S2)............................................................................................................. 421
24.3.12 MCG Test 3 Register (MCG_T3)................................................................................................................ 421
24.4 Functional description...................................................................................................................................................422
24.4.1 MCG mode state diagram............................................................................................................................ 422
24.4.1.1 MCG modes of operation.........................................................................................................422
24.4.1.2 MCG mode switching.............................................................................................................. 424
24.4.2 Low-power bit usage....................................................................................................................................425
24.4.3 MCG Internal Reference Clocks..................................................................................................................425
24.4.3.1 MCG Internal Reference Clock............................................................................................... 425
24.4.4 External Reference Clock............................................................................................................................ 425
24.4.5 MCG Auto TRIM (ATM)............................................................................................................................426
24.5 Initialization / Application information........................................................................................................................ 427
24.5.1 MCG module initialization sequence...........................................................................................................427
24.5.1.1 Initializing the MCG................................................................................................................ 428
24.5.2 Using a 32.768 kHz reference......................................................................................................................430
24.5.3 MCG mode switching.................................................................................................................................. 430
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