Semtech GX3290 User guide

EB-GX3290

Evaluation Board User Guide

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GX3290

EB-GX3290

Evaluation Board User Guide

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Revision History

Contents

1. Evaluation Board User Guide ....................................................................................................................4

1.1 Power ....................................................................................................................................................4

1.1.1 Changing the Power Supply Voltage Levels................................................................5

1.1.2 Power Supply Fault..............................................................................................................5

1.2 Thermal ................................................................................................................................................6

1.3 Reset ......................................................................................................................................................6

1.4 Power On Reset (POR) .....................................................................................................................6

1.5 High-Speed I/Os ................................................................................................................................6

1.6 Communications ...............................................................................................................................7

1.6.1 GSPI ...........................................................................................................................................7

1.6.2 APPI...........................................................................................................................................8

1.6.3 GS2970A and GS4911B Communications....................................................................8

1.6.4 Update Enable .......................................................................................................................8

1.6.5 JTAG ..........................................................................................................................................8

1.6.6 Probe Headers........................................................................................................................9

1.7 High-Speed Mezzanine Connector (HSMC) ......................................................................... 10

1.8 GS4911B ........................................................................................................................................... 10

1.9 GS2970A ........................................................................................................................................... 11

1.10 Configuring Device for HDMI ................................................................................................. 11

1.11 GX3290 Control Software ........................................................................................................ 11

1.12 Start-up Process ........................................................................................................................... 11

Version ECR Date Changes and / or Modifications

1 158345 July 2012

Updated the Altera Cyclone III FPGA information.

Added the Appendix - Relevant Documentation

table for list of relevant documents.

0 155039 October 2010 New document.

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General Description

The EB-GX3290 evaluation package is designed to accelerate the evaluation process of

the GX3290; a Gennum 290x290 3.5Gb/s crosspoint switch with trace equalization and

output de-emphasis.

It is strongly recommended to read the GX3290 Data Sheet before using this evaluation

kit.

Overview

Figure A below shows a block diagram of the features and the functions of the

EB-GX3290. The board includes a GX3290 crosspoint switch, a +12V power supply

connection, a GSPI header, a JTAG header, a high-speed mezzanine connector (HSMC),

and status indication LEDs. The EB-GX3290 provides access to the GX3290's internal

registers via GSPI or APPI. A GSPI dongle is included in the kit to connect the supplied

Graphical User Interface (GUI) software with the GX3290 through a USB connection on

a PC running Microsoft Windows XP or later. The GUI provides for control and

monitoring of the GX3290, and the included GS2970A 3Gb/s SDI receiver and GS4911B

clock and timing generator devices on the evaluation board. The EB-GX3290 is

compatible with the Altera Cyclone III (EP3C25F324C6H) FPGA Starter Kit (not

supplied), and is required for APPI communication and frame boundary switching. The

EB-GX3290 utilizes a standard Altera HSMC, allowing for different development kits to

be connected.

NOTE: For Schematics, PCB Layout and Bill of Materials refer to the EB-GX3290

Schematics, PCB Layout and Bill of Materials document.

Figure A: Block Diagram of the EB-GX3290

GX3290

1.2V

2.5V

1.2V

2.5V

1.8V

2.5V

Power Good

Power Fault

Over T emp

GX3290 Reset

JTAG

GSPI

Sync Block

GS2970A

HSMC

VCC_25A

VCC_OUT

VCC_IN

Reset

GS4911/GS2970

VDD_4V

VDD_25D

VDDIO_D

VDD_18D

+3.3V

+12V Supply

Connection

Lock

Loss of Lock

Ref Lost

RefLock

LOCK LED

Y ANC LED

DATA ERR LED

Update Pins

Probe1 Probe2

SDI Odd SDI Even

SDO Odd

SDO Even

+1.2V

Main Power Switch

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1. Evaluation Board User Guide

Figure 1-1 shows the inputs, outputs and power connections for the EB-GX3290:

Figure 1-1: GX3290 Evaluation Board (EB-GX3290)

1.1 Power

The EB-GX3290 requires a single +12V DC power supply. The board is powered through

connector J100. The Power Good LED (CR503) indicates the power on/off state of the

board. On the evaluation board for the GX3290, the following power supplies have been

tied together:

VCC_IN1 tied to VCC_IN2 = VCC_IN

VCC_OUT1 tied to VCC_OUT2 = VCC_OUT

VDD_18_D1 tied to VDD_18_D2 = VDD_18D

VDD_25_D1 tied to VDD_25_D2 = VDD_25_D

Power In (J100)

GSPI Header (J1302)

JTAG Header (J1301)

FPGA Board

Ribbon Cable & Gennum USB Dongle

GX3290

Crosspoint

Outputs

Inputs

Probe1 Probe2

GS4911B/GS2970A Reset (SW1302)

UPDATE_EN[7:0] (J1303)

APPI_CS (JP601)

GSPI_CS (JP603)

Main Power (SW501)

GS4911 Control (SW1101)

GS2970A Control (SW1201)

VCC_IN Level Selection

(J201, J202)

VCC_OUT Level Selection

(J203, J204)

GX3290 Reset (SW1301)

HSMC Connector (J1300)

(located on bottom-side)

Inputs

Power Fault LED (CR501)

Over Temp LED (CR502)

Power Good LED (CR503)

Outputs

Synchronous Signal Input Connector (J1102)

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The EB-GX3290 allows for selection of the VCC_IN, VCC_OUT, and VDDIO_D voltage

levels for the GX3290. Table 1-1 lists the supply levels:

NOTE: When using a Cyclone III FPGA Starter Kit, VDDIO_D on the EB-GX3290 must be

set to 2.5V.

1.1.1 Changing the Power Supply Voltage Levels

To reconfigure any of the selectable power supplies, follow these steps:

1. Power-down the EB-GX3290.

2. Set jumpers accordingly:

3. Re-power the EB-GX3290.

NOTE 1: When changing VCC_IN, both J201 and J202 must have the same population.

NOTE 2: When changing VCC_OUT, both J203 and J204 must have the same population.

1.1.2 Power Supply Fault

If a power related fault is detected, the Power Fault LED (CR501) will be illuminated and

the power supplies will be shut down.

Power supply faults are caused by over-voltage or under-voltage conditions. These

conditions can be related to either the main +12V power supply, or the on-board

regulated 2.5V (U100, U101, U200, U201, U302 and/or U303), 1.8V (U301 and/or U303),

1.2V (U200, U201) or 4V (U300) supplies. All supplies are monitored to be within ±5% of

the set voltage.

Table 1-1: Power Supply Configurations

VCC_25_A Fixed at 2.5V

VCC_IN Selectable between 1.2V or 2.5V

VCC_OUT Selectable between 1.2V or 2.5V

VDD_18D Fixed at 1.8V

VDDIO_D Selectable between 1.8V or 2.5V

VDD_25_D Fixed at 2.5V

Table 1-2: Power Jumpers

Condition

VCC_IN

(J201, J202)

VCC_OUT

(J203, J204)

VDDIO_D

(J301)

Open 1.2V 1.2V 2.5V

Short 2.5V 2.5V 1.8V

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1.2 Thermal

The EB-GX3290 monitors the die of the GX3290 device for over-temperature fault

conditions. When an over-temperature fault exists, the Over Temp LED (CR502) will be

illuminated. In an over-temperature condition (≥85°C), the temperature monitor is set to

turn off all power supplies.

1.3 Reset

The EB-GX3290 has two reset switches. GX3290 Reset (SW1301) will reset the GX3290

device back to its default settings. The GS4911B/GS2970A Reset (SW1302) will reset

the GS4911B and the GS2970A back to their default settings.

1.4 Power On Reset (POR)

The GX3290 has a built-in POR, and no external circuitry is required.

1.5 High-Speed I/Os

The EB-GX3290 includes standard SMA connectors for the following high-speed

differential inputs and outputs:

Table 1-3: High Speed I/Os

Input Name

SMA Connection

Output Name

SMA Connection

P N P N

SDI_0

1, 2, 3

J1400 J1401

SDO_0

J1432 J1433

SDI_8 J1402 J1403 SDO_22 J1434 J1435

SDI_22 J1404 J1405

SDO_116

J1436 J1437

SDI_94 J1406 J1407 SDO_186 J1438 J1439

SDI_164 J1408 J1409 SDO_264 J1440 J1441

SDI_278 J1410 J1411 SDO_278 J1442 J1443

SDI_286 J1412 J1413 SDO_286 J1444 J1445

SDI_1 J1414 J1415 SDO_1 J1446 J1447

SDI_9 J1416 J1417 SDO_9 J1448 J1449

SDI_81 J1418 J1419 SDO_23 J1450 J1451

SDI_201 J1420 J1421 SDO_129 J1452 J1453

SDI_265 J1422 J1423 SDO_149 J1454 J1455

SDI_279 J1424 J1425 SDO_265 J1456 J1457

SDI_287 J1426 J1427

SDO_287

J1458 J1459

EXT_PG0 J1428 J1429 SDO_95 J1460J1461

EXT_PG1 J1430 J1431 MON0 J1462J1463

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1.6 Communications

The GX3290 contains a set of internal status and configuration registers. These registers

are available to the host system via the GX3290's GSPI or APPI pins. The GX3290 can

only communicate with GSPI or the APPI; simultaneous bus transactions are not

permitted. If the Cyclone III FPGA Starter Kit is not present, communication to the

GX3290 must be via GSPI.

The GS4911B and GS2970A communication is via GSPI only.

The mode of communication can be selected as follows:

1.6.1 GSPI

Access to the applicable pins on the GX3290 is provided using the GSPI header (J1302)

and the following jumpers must be set:

JP601 installed in position 1-2

JP603 installed in position 2-3

Input Name

Connection

Output Name

Connection

P N P N

–––

MON1

GS2970A_SDI

SDI_275

GS2970A_SDO

–– –

1. Short path.

2. Medium path.

3. Long path.

4. MON1 output is connected directly to the GS2970A input and the GS2970A output is connected directly to SDI_275 which in turn can be

routed to any output.

Table 1-4: GSPI Communications

Header J1302

Pin Name Short Name Pin Number Description

Slave Select 0 SS0 1 GX3290 chip select

Master In Slave Out MISO 3 Master read

Master Out Slave In MOSI 5 Master write

Slave Clock SCLK 7 GSPI clock

Slave Select 1 SS12GS2970 chip select

Slave Select 2 SS24GS4911 chip select

Slave Select 3 SS3 10 FPGA chip select

Ground 8, 9 Ground

I/O Select 6 VCC level for dongle level

translator

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1.6.2 APPI

To use APPI communication, the Cyclone III FPGA Starter Kit must be present. The GUI

will send GSPI commands to the FPGA board where they are translated to APPI.

The following jumpers must also be set when using the APPI:

JP601 installed in position 2-3

JP603 installed in position 1-2

1.6.3 GS2970A and GS4911B Communications

Communication with the GS2970A and GS4911B is provided by GSPI.

The MISO data path for the GS2970A and GS4911B must be configured. This path is

determined by the presence of the Cyclone III FPGA Starter Kit. By default the

EB-GX3290 is populated for GSPI communication. The following resistor selections only

affect GS2970A and GS4911B read-back.

1.6.4 Update Enable

A rising edge on the Update Enable pins (J1303), in conjunction with programming the

DYNAMIC [287:0] registers, will cause the switch matrix configuration to be updated.

The update enable pin levels must be at the same logic level as VDDIO_D. See the

GX3290 Data Sheet for more details.

Frame Boundary Switching (UPDATE_EN0 only)

For information on programming the UPDATE, refer to the GX3290 Host Control

Software User Manual.

1.6.5 JTAG

JTAG-controlled boundary scan communication is provided through a standard pin out

connection on J1301.

Table 1-5: GS2970 and GS4911 Communications

FPGA Present FPGA Not Present

R1301: populate R1301: depopulate

R1302: depopulate R1302: populate

R1323: populate R1323: depopulate

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1.6.6 Probe Headers

Probe 1 and Probe 2 are landing pads for Tektronix P6419 logic analyzer probes. These

landings have the APPI signals present.

Table 1-6: Probe Headers

Landing Probe 1 Probe 2

A1 Address 0 Data 0

A2 GND GND

A3 Address 1 Data 1

A4 Address 4 Data 4

A5 GND GND

A6 Address 5 Data 5

A7 Address 8 Data 8

A8 GND GND

A9 Address 9 Data 9

A10 HOST_S/P

Data 12

A11 GND GND

A12 R/W

Data 13

A13 ADS NC

A14 GND GND

A15 NC NC

B1 Address 2 Data 2

B2 GND GND

B3 Address 3 Data 3

B4 Address 6 Data 6

B5 GND GND

B6 Address 7 Data 7

B7 Address 10 Data 10

B8 GND GND

B9 Address 11 Data 11

B10 NC Data 14

B11 GND GND

B12 CS Data 15

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1.7 High-Speed Mezzanine Connector (HSMC)

On the EB-GX3290, the HSMC includes the following signals:

NOTE: When connecting a Cyclone III FPGA starter kit to the HSMC (J1300), the

EB-GX3290’s VDDIO_D must be set to 2.5V. For other FPGA development boards, verify

2.5V and/or 1.8V compliance.

1.8 GS4911B

The GS4911B is available for use in conjunction with an FPGA (connected via the HSMC)

to create frame boundary update signals for the GX3290.

If a valid external sync signal is applied to J1102, the Ref Lock (CR1104) and Lock

(CR1102) LEDs for the GS4911B will be illuminated once the correct video standard has

been set via the GUI or hardware pins. If the external sync signal is invalid or not

present, the Ref Lost (CR1103) and the Lock Lost (CR1101) LEDs will be illuminated.

The VID_STD[5:0] and GENLOCK

signals can be controlled by the on-board dip switch

(SW1101) or through the HSMC (J1300). By default, the GS4911B requires the dip

switches to be set in the open position. The lock status is also shown in the GUI.

For more details on the GS4911B’s controls and features, please see the GS4911B Data

Sheet.

Table 1-7: HSMC Signals

GX3290 Signals

P_CS

, P_R/W, P_ADS, P_ADD[11:0], P_DAT[15:0], SCLK, SDIN,

SDOUT, S_CS

, HOST_S/P, UPDATE_EN[7:0], TCK, TMS, TDO, TDI,

EXT_REF_CLK_[3:0], RESET_A

, RESET

GS4911B Signals GENLOCK, VID_STD[5:0], PCLK1, TIMING_OUT_[2,4,5]

GS2970A Signals SMPTE_BYPASS, RC_BYP, STANDBY, H, V, F, PCLK

Miscellaneous Signals SMBCLK, SMBDAT, TCRIT1, TCRIT2, TCRIT3

NOTE: See the EB-GX3290 schematics for pin and ball identifications in the GX3290 Data

Sheet

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1.9 GS2970A

The GS2970A is present for format recognition, re-clocking of SDI signals if necessary

and for use in conjunction with an FPGA (connected via the HSMC) to create frame

boundary update signals for the GX3290.

If a valid SDI signal is detected by the GS2970A, the Lock LED (CR1201) will be

illuminated. If the valid signal contains Luma ancillary data, the Y ANC LED (CR1202)

will be illuminated whenever that data is present. If the signal contains errors, the Data

Error LED (CR1203) will be illuminated.

SDI format recognition values can be found on the GS2970A tab of the GUI.

STANDBY, RC_BYP

and SMPTE_BYPASS can be controlled by the on-board dip switches

(SW1201), or by the FPGA via the HSMC (J1300). The default switch settings are:

STANDBY = 0*

RC_BYP

= 0*

SMPTE_BYPASS

= 1

*If an FPGA is connected, set to 1 for GUI control.

For more details on the GS2970A’s controls and features, please see the GS2970A Data

Sheet.

NOTE: DVB-ASI must not be applied to the GS2970A on the EB-GX3290 board. Due to

the schematic configuration of the GS2970A, doing so could result in damage to the

GS2970A.

1.10 Configuring Device for HDMI

Using a HDMI break-out boards (EBK-GX3290-HDMI00) pass each signal through the

crosspoint. When reconfiguring and recombining ensure proper mapping. The clock

output swing must be set to 800mVppd and can be adjustable for the video portions.

Longer traces may require larger output swing. See Interfacing HDMI/DVI and

DisplayPort to the Semtech Crosspoint Family for more detail.

1.11 GX3290 Control Software

Please refer to the GX3290 Host Control Software User Manual.

1.12 Start-up Process

1. Ensure the software and drivers are installed on your PC.

2. Connect the GSPI dongle board to the EB-GX3290 board by using the supplied

ribbon cable.

3. Connect the power supplies as per Section 1.1, and power-up the board using the

main power switch (SW501.1). In the OFF position, all power supplies are disabled

and the power supply monitor is still active. When switching to the ON position,

there could be a delay of up to 3s for the power supply monitor device to enable all

power supplies.

4. Connect the GSPI dongle board to a PC USB port via a USB cable.

5. Launch the GX3290 Control Software on the PC.

The GX3290 registers can now be controlled through the GUI.

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Appendix - Relevant Documentation

Document Description Document Identification

GX3290 Data Sheet 53317

GS2970A Data Sheet 54244

EB-GX3290 Schematics, PCB Layout and Bill of

Materials

56057

GX3290 Host Control Software User Manual 55970

GS4911B Data Sheet 36655

Interfacing HDMI/DVI and DisplayPort to the Semtech

Crosspoint Family

56947

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operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or

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Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners

DOCUMENT IDENTIFICATION

EVALUATION BOARD USER GUIDE

Information relating to this product and the application or design described

herein is believed to be reliable, however such information is provided as a

guide only and Semtech assumes no liability for any errors in this document, or

for the application or design described herein. Semtech reserves the right to

make changes to the product or this document at any time without notice.

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Contact Information

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Gennum Products Division

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Phone: (805) 498-2111, Fax: (805) 498-3804

www.semtech.com

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