Altera Cyclone III LS Reference guide

101 Innovation Drive

San Jose, CA 95134

www.altera.com

Cyclone III LS FPGA Development Board

Reference Manual

Document Version: 1.0

Document Date: October 2009

words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other

countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending ap-

plications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,

but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of

any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of

device specifications before relying on any published information and before placing orders for products or services.

MNL-01049-1.0

ry

Contents

Chapter 1. Overview

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Featured Device: Cyclone III LS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

MAX II CPLD EPM2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

Configuration, Status, and Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

JTAG Chain Header Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Anti-Tamper JTAG Select Header Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

LCD/HSMC Port B Data Select Header Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

Configuration Push-button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Cyclone III LS FPGA Clock Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

Cyclone III LS FPGA Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

User-Defined Push-Button Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

User-Defined DIP Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–25

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

High-Speed Mezzanine Cards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–29

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–35

DDR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–36

SSRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–39

Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–41

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–44

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–44

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47

iv

Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation

ary

Additional Information

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2

1. Overview

Introduction

This document describes the hardware features of the Cyclone

®

III LS FPGA

development board, including the detailed pin-out and component reference

information required to create custom FPGA designs that interface with all

components of the board.

General Description

The Cyclone III LS FPGA development board provides a hardware platform for

developing and prototyping low-power, secure, high-volume, feature-rich designs as

well as to demonstrate the Cyclone III LS device's on-chip memory, embedded

multipliers, and the Nios

®

II embedded soft processor. The board provides a wide

range of peripherals and memory interfaces to facilitate the development of the

Cyclone III LS FPGA designs.

Two high-speed mezzanine card (HSMC) connectors are available to add additional

functionality via a variety of HSMCs available from Altera

®

and various partners.

f To see a list of the latest HSMCs available or to download a copy of the HSMC

specification, refer to the Development Board Daughtercards page of the Altera

website (www.altera.com).

The Cyclone III LS FPGAs are the first to offer a suite of security features at the silicon,

software, and intellectual property (IP) level on a low-power, high-functionality

FPGA. This suite of security features protects your IP from tampering, reverse

engineering, and cloning. Additionally, these devices enable you to introduce

redundancy in a single chip using design separation, which in turn reduces the size,

weight, and power of your applications.

The Cyclone III LS FPGA development board is especially suitable for low-power,

secure, logic-rich applications that require stringent signal and power integrity

solutions.

f For more information on the following topics, refer to the respective documents:

■ Cyclone III device family, refer to the Cyclone III Device Handbook.

■ Cyclone III LS security features, refer to the Partitioning FPGA Designs for

Redundancy and Information Security Webcast page of the Altera website.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

1–2 Chapter 1: Overview

Board Component Blocks

Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation

Board Component Blocks

The board features the following major component blocks:

■ Cyclone III LS EP3CLS200F780 FPGA in the 780-pin FineLine BGA (FBGA)

package

■ 198,464 LEs

■ 8,211 Kbit on-die memory

■ 20 global clocks

■ 413 user I/O

■ 4 phase locked loops (PLLs)

■ 396 18x18 multipliers

■ 1.2-V core power

■ MAX

®

II EPM2210F256 CPLD in the 256-pin FBGA package

■ 2.5-V core power

■ FPGA configuration circuitry

■ MAX

II CPLD EPM2210 System Controller and flash passive serial (PS)

configuration

■ On-board USB-Blaster

TM

for use with the Quartus

®

II Programmer

■ On-Board ports

■ Two HSMC expansion ports

■ One gigabit Ethernet port

■ On-Board memory

■ Two 512-Mbit 64-bit DDR2

■ 2-Mbyte Synchronous Static Random Access Memory (SSRAM)

■ 64-Mbyte flash

■ I

2

C EEPROM

■ On-Board clocking circuitry

■ Four on-board oscillators

■ 50-MHz oscillator

■ 66.6-MHz oscillator

■ 100-MHz oscillator

■ Programmable oscillator with a default frequency of 125-MHz

■ LVPECL SMA connectors for external clock input

■ LVDS SMA connectors for external clock output

■ SMA connector for FPGA clock output

Chapter 1: Overview 1–3

Board Component Blocks

■ General user I/O

■ LEDs and display

■ Four user LEDs

■ Two-line character LCD display

■ One configuration done LED

■ Three anti-tamper example design status LEDs

■ Five Ethernet LEDs

■ Push-Button switches

■ One CPU reset push-button switch

■ One MAX II configuration reset push-button switch

■ One PGM configure push-button switch (configure the FPGA from flash

memory)

■ One PGM select push-button switch (select image to load from flash

memory)

■ One VCCA shutdown push-button switch

■ One CRC error insert push-button switch

■ Four general user push-button switches

■ DIP switches

■ Four user DIP switches

■ Eight MAX II CPLD EPM2210 System Controller DIP switches

■ Power supply

■ 14-V – 20-V DC input

■ On-board power measurement circuitry

1–4 Chapter 1: Overview

Development Board Block Diagram

Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation

Development Board Block Diagram

Figure 1–1 shows the block diagram of the Cyclone III LS FPGA development board.

Handling the Board

When handling the board, it is important to observe the following static discharge

precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

Figure 1–1. Cyclone III LS FPGA Development Board Block Diagram

EP3CLS200F780

Port B

Port A

EEPROM

(32 Kbit I

2

C)

2x16 LCD

Push-button

Switches,

DIP Switches,

LEDs

CPLD

64 Mbyte

Flash

2 Mbyte

SSRAM

512 Mbyte

DDR2 (x16)

Gigabit

Ethernet

PHY (RGMII)

Clock_SMA

Programmable Oscillator

100 M, 125 M, 156.25 M,

SMA (LVPECL)

Embedded

Blaster

USB

2.0

x47

x16

x2 CLK IN

x2

x11

x13

x26 ADDR

Config I/O

x74

CLKIN x2

CLKOUT x2

x74

CLKIN x3

CLKOUT x3

JTAG Chain

x32 DATA

x1 CLK IN

(1.8 V)

Migratable to

EP3CLS70F780

Z Z

66.6 MHz

512 Mbyte

DDR2 (x16)

x47

SMA

Anti-Tamper

Example

Design

x6

(LVPECL)

2. Board Components

Introduction

This chapter introduces the major components on the Cyclone III LS FPGA

development board.

Figure 2–1 illustrates major component locations and Table 2–1

provides a brief description of all component features of the board.

1 A complete set of schematics, a physical layout database, and GERBER files for the

development board reside in the Cyclone III LS FPGA development kit documents

directory.

f For information about powering up the board and installing the demonstration

software, refer to the Cyclone III LS FPGA Development Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Cyclone III LS Device” on page 2–4

■ “MAX II CPLD EPM2210 System Controller” on page 2–6

■ “Configuration, Status, and Setup Elements” on page 2–11

■ “Clock Circuitry” on page 2–20

■ “General User Input/Output” on page 2–23

■ “Components and Interfaces” on page 2–27

■ “Memory” on page 2–35

■ “Power Supply” on page 2–44

■ “Statement of China-RoHS Compliance” on page 2–47

Board Overview

This section provides an overview of the Cyclone III LS FPGA development board,

including an annotated board image and component descriptions.

Figure 2–1

provides an overview of the development board features.

2–2 Chapter 2: Board Components

Board Overview

Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation

Table 2–1 describes the components and lists their corresponding board references.

Figure 2–1. Overview of the Cyclone III LS FPGA Development Board Features

Clock Input SMAs

Connector (J7, J9)

Max II Reset

Push-Button

Switch (S10)

General User

Push-buttons

Switches

(S3 - S6)

Board Settings

DIP Switch (SW2)

DC Input Jack (J5)

Cyclone III LS FPGA (U15)

Character LCD

(J19)

CPU Reset

Push-button

Switch (S2)

Power Switch (SW1)

General

User DIP

Switch (S7)

General

User LEDs

(D25-D28)

MAX II CPLD

EPM2210 System

Controller (U22)

Clock Output SMA

Connector (J15)

HSMC Port B (J1) HSMC Port A (J2)

Configuration Status

LEDs (D10-D14)

Flash x16 Memory (U9)

DDR2 Memory (U5, U6)

Programmable

Oscillator Output

(J13, J14)

USB Type-B

Connector (J4)

Gigabit Ethernet

Port (J16)

JTAG Connector

(J8)

SSRAM x36

Memory (U14)

Configuration

Select

LEDs

(D29-D31)

Configuration

Program and

Select

Push-buttons

Switches (S8, S9)

Power LED (D3)

JTAG Chain Header

& JTAG Select

Jumpers (J11, J12)

CRC Error (S1)

JTAG Anti-Tamper

Select LEDs (D6-D9)

LCD/HSMC Port B

Data Select (J18)

VCCA Shutdown

Push-Button

Switch (S11)

Table 2–1. Cyclone III LS FPGA Development Board Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U15 FPGA EP3CLS200F780, 780-pin FBGA.

U22 CPLD EPM2210F256, 256-pin FBGA.

Configuration, Status, and Setup Elements

J4 USB type-B connector Connects to the computer to enable embedded USB-Blaster JTAG.

J11 JTAG chain header Enables and disables devices in the JTAG chain.

J12 Anti-Tamper JTAG select

header

Placing a shunt on this jumper breaks the default JTAG chain, giving

FPGA JTAG signals control to the MAX II EPM2210 System Controller.

D6 Anti-Tamper JTAG select LED Illuminated when the default JTAG chain is broken and the MAX II

EPM2210 System Controller has control of the FPGA JTAG signals.

SW2 Board settings DIP switch Controls the MAX

II CPLD EPM2210 System Controller functions such

as clock enable, SMA clock input control, and which image to load

from flash memory at power-up.

J8 JTAG connector Disables embedded blaster (for use with external USB-Blasters).

D13 Configuration done LED Illuminates when the FPGA is configured.

Chapter 2: Board Components 2–3

Board Overview

D11 Load LED Illuminates when the MAX II CPLD EPM2210 System Controller is

actively configuring the FPGA.

D10 Error LED Illuminates when the FPGA configuration from flash memory fails.

D12 Factory LED Illuminates when the factory image is loaded to the FPGA.

D29, D30, D31 Configuration select LEDs Illuminates to show the LED sequence that determines which flash

memory image loads to the FPGA when PGM SEL is pressed.

D15, D16, D18,

D20, D22

Ethernet LEDs Shows the connection speed as well as transmit or receive activity.

D2 HSMC port A present LED Illuminates when a daughtercard is plugged into the HSMC port A.

D1 HSMC port B present LED Illuminates when a daughtercard is plugged into the HSMC port B.

D3 Power LED Illuminates when 12-V power is present.

J18 LCD/HSMC Port B data select Controls data multiplexing to the FPGA from the LCD or

HSMB_D[65:75]. Placing a shunt on the jumper allows the FPGA to

control the LCD signals.

J6 PS standard/fast select Placing a shunt sets the MSEL pins for passive serial standard

configuration. Otherwise, the MSEL pins is set for passive serial fast

configuration.

S2 CPU reset push-button switch Press to reset the FPGA logic.

S11 VCCA shutdown push-button

switch

Turns VCCA power to the FPGA on and off. This switch initiates a

power-on reset.

S10 MAX II reset push-button

switch

Press to reset the MAX II CPLD EPM2210 System Controller.

S9 PGM select push-button

switch

Toggles the PGM LEDs which selects the program image that loads

from flash memory to the FPGA.

S8 PGM configure push-button

switch

Configure the FGPA from flash memory based on the PGM LEDs

setting.

Clock Circuitry

U17 Programmable oscillator

(125 MHz default)

Programmable oscillator with a default frequency of 125.00 MHz. The

frequency is programmable using the MAX II CPLD EPM2210 System

Controller. For general use such as HSMC logic or gigabit Ethernet

(125 M/156.25 M)

X3 66.6 MHz oscillator 66.6 MHz crystal oscillator for general purpose logic and DDR2

memory.

X5 50 MHz oscillator 50 MHz crystal oscillator for general purpose logic.

Y3 100 MHz oscillator 100 MHz crystal oscillator for configuration purpose.

J7, J9 Clock FPGA input SMAs Drive LVPECL-compatible clock inputs into the clock multiplexer buffer

(U20).

J15 Clock FPGA output SMA Drive out 2.5-V CMOS clock output from the FPGA.

J13, J14 Clock output SMAs LVDS output clock from the clock multiplexer buffer (U20).

General User Input/Output

D25, D26, D27,

D28

User LEDs Four user LEDs. Illuminates when driven low.

S7 User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.

Table 2–1. Cyclone III LS FPGA Development Board Components (Part 2 of 3)

Board Reference Type Description

2–4 Chapter 2: Board Components

Featured Device: Cyclone III LS Device

Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation

Featured Device: Cyclone III LS Device

The Cyclone III LS FPGA development board features the Cyclone III LS

EP3CLS200F780 device (U15) in a 780-pin FBGA package.

f For more information about Cyclone III device family, refer to the Cyclone III Device

Handbook.

Table 2–2 describes the features of the Cyclone III LS EP3CLS200F780 device.

Table 2–3 lists the Cyclone III LS device component reference and manufacturing

information.

S3, S4, S5, S6 User push-button switches Four user push-button switches. Driven low when pressed.

J19 Character LCD Connector which interfaces to the provided 16 character × 2 line LCD

module.

Memory Devices

U5, U6 DDR2 x16 memory Two independent 16-bit, 64-Mbyte DDR2 devices.

U14 SSRAM x36 memory Standard synchronous RAM which makes a 36-bit 2-Mbyte SSRAM

port.

U9 Flash x16 memory Synchronous burst mode flash device which provides a 16-bit 64-

Mbyte non-volatile memory port.

U21 EEPROM I

2

C EEPROM

Components and Interfaces

J2 HSMC port A Provides 80 CMOS or 17 LVDS channels per the HSMC specification.

J1 HSMC port B Provides 76 CMOS channels per the HSMC specification.

J16 Gigabit Ethernet RJ-45 connector which provides a 10/100/1000 Ethernet connection

via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed

Ethernet MegaCore function in RGMII mode.

Anti-Tamper Interface

J10 JTAG header to MAX II general

I/O

JTAG header connected to general purpose I/O (GPIO) on the MAX II

EPM2210 System Controller.

D8, D9, D10 Anti-Tamper status LEDs Three anti-tamper status indicator LEDs.

S1 CRC error push-button Insert a CRC error when running the anti-tamper example design.

Power Supply

J5 DC input jack Accepts a 14-V – 20-V DC power supply.

SW1 Power switch Switch to power on or off the board when power is supplied from the

DC input jack.

Table 2–1. Cyclone III LS FPGA Development Board Components (Part 3 of 3)

Board Reference Type Description

Table 2–2. Cyclone III LS Device EP3CLS200F780 Features

Equivalent LEs M9K RAM Blocks Total RAM Kbits 18-bit × 18-bit Multipliers PLLs Package Type

198,464 891 8,211 396 4 780-pin FBGA

Chapter 2: Board Components 2–5

Featured Device: Cyclone III LS Device

I/O Resources

Figure 2–2 illustrates the bank organization and I/O count for the EP3CLS200 device

in the 780-pin FBGA package.

Table 2–4 lists the Cyclone III LS device pin count and usage by function on the

development board.

Table 2–3. Cyclone III LS Device Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U15 FPGA, Cyclone III LS F780,

198K LEs, lead-free

Altera

Corporation EP3CLS200F780C7N www.altera.com

Figure 2–2. EP3CLS200 Device I/O Bank Diagram

B8

58 I/O

B7

59 I/O

B6

48 I/O

B5

52 I/O

B4

58 I/O

B3

59 I/O

B2

49 I/O

B1

47 I/O

Table 2–4. Cyclone III LS Device Pin Count and Usage (Part 1 of 2)

Function I/O Standard I/O Count Special Pins

DDR2 1.8-V SSTL 94 2 differential clocks, 4 DQS

MAX Bus 2.5-V CMOS 8 —

Flash, SSRAM, FSM Bus 2.5-V CMOS 82 —

HSMC Port A 2.5-V CMOS + LVDS 84 34 LVDS, 2 differential clock inputs, 1

clock input

HSMC Port B 2.5-V CMOS 84 1 differential clock input, 1 clock input

Gigabit Ethernet 2.5-V CMOS 16 1 clock input

Buttons 1.8-V / 2.5-V CMOS 5 1 DEV_CLRn

Switches 1.8-V CMOS 5 —

LCD (1) 2.5-V CMOS 11 —

2–6 Chapter 2: Board Components

MAX II CPLD EPM2210 System Controller

Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation

MAX II CPLD EPM2210 System Controller

The board utilizes the EPM2210 System Controller, an Altera MAX

II CPLD, for the

following purposes:

■ FPGA configuration from flash memory

■ Power consumption monitoring

■ Virtual JTAG interface for PC-based GUI

■ Control registers for clocks

■ Control registers for remote system update

■ Anti-Tamper example design

1 The development kit includes the anti-tamper example design in the

<install_dir>\kits\cycloneIIILS_3cls200_fpga\examples\max2\at_example\

readme_at_example.txt directory.

Figure 2–3 illustrates the MAX II CPLD EPM2210 System Controller's functionality

and external circuit connections as a block diagram.

LEDs 1.8-V CMOS 5 1 INIT_DONE

Clocks or Oscillators 1.8-V / 2.5-V CMOS + LVDS 5 2 differential clock input, 1 clock input

EEPROM 2.5-V CMOS 2 —

Device I/O Total:

390

Note to Table 2–4:

(1) The LCD signals are multiplexed with HSMB_D[65:75] and therefore not included in the total pin count.

Table 2–4. Cyclone III LS Device Pin Count and Usage (Part 2 of 2)

Function I/O Standard I/O Count Special Pins

Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram

Information

Register

Embedded

Blaster

MAX-II

Power

Calculations

SLD-HUB

PFL

Power

Measurement

Results

Virtual-JTAG

PC

3CLS

LTC2418

Controller

FLASH

Decoder

Encoder

GPIO

JTAG Control

SSRAM

Control

Register

Anti-Tamper

Example Design

Chapter 2: Board Components 2–7

MAX II CPLD EPM2210 System Controller

Table 2–5 lists the I/O signals present on the MAX

II CPLD EPM2210 System

Controller. The signal names and functions are relative to the MAX

II device (U22).

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 1 of 4)

Schematic Signal Name I/O Standard

EPM2210

Pin Number

EP3CLS200

Pin Number Description

CLK50_EN

2.5-V

H16 — 50 MHz oscillator enable

CLK66_EN H13 — 66.6 MHz oscillator enable

CLK_CONFIG J12 — 100 MHz configuration clock input

CLK_ENABLE N7 — DIP - clock oscillator enable

CLK_SEL T5 — DIP - clock select SMA or oscillator

CLKIN_50 J5 — 50 MHz clock input

CPU_RESETn R8 W27 FPGA reset push-button switch

CRC_ERROR K5 P26 FPGA CRC error

CRC_ERROR_MAX K12 — CRC error LED

CRC_ERROR_PB R16 — CRC error insert push-button switch

CRC_LATCH_SIG K4 AF5 Anti-Tamper FPGA general I/O

FLASH_ADVn B3 AF18 FSM bus flash memory address valid

FLASH_CEn E6 AH22 FSM bus flash memory chip enable

FLASH_CLK C6 AH6 FSM bus flash memory clock

FLASH_OEn B4 AD7 FSM bus flash memory output enable

FLASH_RDYBSYn D6 V4 FSM bus flash memory ready

FLASH_RESETn C4 AH5 FSM bus flash memory reset

FLASH_WEn A4 AH17 FSM bus flash memory write enable

FPGA_CONF_DONE J1 P22 FPGA configuration done

FPGA_CONFIG_D0 D3 K1 FPGA configuration data

FPGA_DCLK H4 L6 FPGA configuration clock

FPGA_EPM2210_TCK C15 — FPGA JTAG TCK

FPGA_EPM2210_TDI E13 — FPGA JTAG TDI

FPGA_EPM2210_TDO E14 — FPGA JTAG TDO

FPGA_EPM2210_TMS C14 — FPGA JTAG TMS

FPGA_INIT_DONE N5 P27 FPGA INIT_DONE signal

FPGA_nCONFIG T2 M3 FPGA configuration active

FPGA_nSTATUS H3 M1 FPGA configuration ready

FPGA_TCK P14 — Anti-Tamper example design JTAG connector TCK

FPGA_TDI P15 — Anti-Tamper example design JTAG connector TDI

FPGA_TDO M14 — Anti-Tamper example design JTAG connector

TDO

FPGA_TMS N13 — Anti-Tamper example design JTAG connector

TMS

FSM_A0 C13 AG6 FSM bus address

FSM_A1 B16 AD14 FSM bus address

FSM_A2 C12 AA17 FSM bus address

2–8 Chapter 2: Board Components

MAX II CPLD EPM2210 System Controller

Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation

FSM_A3

2.5-V

A15 AE12 FSM bus address

FSM_A4 D12 AF21 FSM bus address

FSM_A5 B14 AH2 FSM bus address

FSM_A6 C11 AB12 FSM bus address

FSM_A7 B13 AG24 FSM bus address

FSM_A8 D11 AE25 FSM bus address

FSM_A9 A13 AH21 FSM bus address

FSM_A10 E11 AD25 FSM bus address

FSM_A11 B12 AC9 FSM bus address

FSM_A12 C10 AF4 FSM bus address

FSM_A13 A12 AE10 FSM bus address

FSM_A14 D10 AH26 FSM bus address

FSM_A15 B11 AG22 FSM bus address

FSM_A16 E10 AF12 FSM bus address

FSM_A17 A11 AE19 FSM bus address

FSM_A18 B10 AA9 FSM bus address

FSM_A19 C9 AE6 FSM bus address

FSM_A20 A10 AG18 FSM bus address

FSM_A21 D9 AE11 FSM bus address

FSM_A22 B9 AB16 FSM bus address

FSM_A23 D4 AE13 FSM bus address

FSM_A24 B1 AG11 FSM bus address

FSM_A25 D5 AE9 FSM bus address

FSM_D0 E9 AH9 FSM bus data

FSM_D1 A9 AH24 FSM bus data

FSM_D2 A8 AF25 FSM bus data

FSM_D3 B8 AE5 FSM bus data

FSM_D4 E8 AB11 FSM bus data

FSM_D5 A7 AD24 FSM bus data

FSM_D6 D8 AF9 FSM bus data

FSM_D7 B7 AE7 FSM bus data

FSM_D8 C8 AE23 FSM bus data

FSM_D9 A6 AF15 FSM bus data

FSM_D10 B6 AD17 FSM bus data

FSM_D11 E7 AF20 FSM bus data

FSM_D12 A5 AH25 FSM bus data

FSM_D13 D7 AE18 FSM bus data

FSM_D14 B5 AD6 FSM bus data

FSM_D15 C7 AG20 FSM bus data

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 4)

Schematic Signal Name I/O Standard

EPM2210

Pin Number

EP3CLS200

Pin Number Description

Chapter 2: Board Components 2–9

MAX II CPLD EPM2210 System Controller

FSM_D16

2.5-V

N9 AH20 FSM bus data

FSM_D17 T8 AH18 FSM bus data

FSM_D18 T9 AF8 FSM bus data

FSM_D19 R9 AE20 FSM bus data

FSM_D20 P9 AB19 FSM bus data

FSM_D21 T10 AB10 FSM bus data

FSM_D22 M10 AC17 FSM bus data

FSM_D23 T11 AD10 FSM bus data

FSM_D24 N10 AG9 FSM bus data

FSM_D25 R11 AE21 FSM bus data

FSM_D26 P10 AD22 FSM bus data

FSM_D27 T12 AH23 FSM bus data

FSM_D28 M11 AG5 FSM bus data

FSM_D29 R12 AB9 FSM bus data

FSM_D30 N11 AD9 FSM bus data

FSM_D31 T13 AD16 FSM bus data

HEARTBEAT M1 AH7 Anti-Tamper FPGA general I/O

HSMA_PRSNTn J16 — HSMC port A present

HSMB_PRSNTn J13 — HSMC port B present

JTAG_AT_SEL K16 — Jumper OFF (default): Select JTAG chain

Jumper ON: MAX II controls FPGA JTAG

JTAG_SECURE R5 — DIP - JTAG security mode ON/OFF

M2Z_CONF_DONE R13 — On-board USB-Blaster FPGA configuration done

M2Z_D0 T15 — On-board USB-Blaster FPGA configuration data

M2Z_DCLK N12 — On-board USB-Blaster FPGA configuration clock

M2Z_nCONFIG R14 — On-board USB-Blaster FPGA configuration active

M2Z_nSTATUS M12 — On-board USB-Blaster FPGA configuration ready

MAX2_BEn0 F5 AG21 FSM bus MAX II byte enable 0

MAX2_BEn1 F2 AF11 FSM bus MAX II byte enable 1

MAX2_BEn2 F6 AG2 FSM bus MAX II byte enable 2

MAX2_BEn3 F1 AC16 FSM bus MAX II byte enable 3

MAX2_CLK E1 AE24 FSM bus MAX II clock

MAX2_CSn E2 AG4 FSM bus MAX II chip select

MAX2_OEn F3 AC10 FSM bus MAX II output enable

MAX2_WEn F4 AA8 FSM bus MAX II write enable

MAX_CONF_DONE E15 — FPGA configuration done LED

MAX_DIP0 F16 — DIP - Anti-Tamper example design

MAX_DIP1 G13 — DIP - Anti-Tamper example design

AT_ACTIVE F15 — DIP - Anti-Tamper example design ON/OFF

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 4)

Schematic Signal Name I/O Standard

EPM2210

Pin Number

EP3CLS200

Pin Number Description

2–10 Chapter 2: Board Components

MAX II CPLD EPM2210 System Controller

Table 2–6 lists the MAX

II CPLD EPM2210 System Controller component reference

and manufacturing information.

MAX_ERROR

2.5-V

G3 — FPGA configuration error LED

MAX_FACTORY G4 — FPGA factory configuration LED

MAX_LOAD G2 — FPGA configuration active LED

MAX_RESETn M9 — MAX II reset push-button switch

PGM_CONFIG K2 — Load the flash memory image identified by the

PGM LEDs

PGM_LED0 J2 — Flash memory PGM select indicator 0

PGM_LED1 J4 — Flash memory PGM select indicator 1

PGM_LED2 K1 — Flash memory PGM select indicator 2

PGM_SEL J3 — Toggles the PGM_LED[0:2] sequence

PLL_CE L13 — Programmable oscillator chip select

PLL_OD0 M15 — Programmable oscillator output divider 0

PLL_OD1 L12 — Programmable oscillator output divider 1

PLL_OD2 M16 — Programmable oscillator output divider 2

PLL_PR0 L11 — Programmable oscillator prescaler 0

PLL_PR1 L15 — Programmable oscillator prescaler 1

PLL_RSTn N16 — Programmable oscillator reset

SECURITY K3 AG12 Anti-Tamper FPGA general I/O

SECURITY_LED0 L1 — Anti-Tamper example design security LED0

SECURITY_LED1 L2 — Anti-Tamper example design security LED1

SENSE_ADC_F0 L3 — Power monitor frequency

SENSE_CS0n N1 — Power monitor chip select

SENSE_SCK L5 — Power monitor serial peripheral interface (SPI)

clock

SENSE_SDI M3 — Power monitor SPI data in

SENSE_SDO L4 — Power monitor SPI data out

SRAM_MODE P4 — FSM bus SSRAM burst sequence selection

SRAM_ZZ L14 AH14 FSM bus SSRAM power sleep mode

USB_DISABLEn G14 — DIP - embedded USB-Blaster disable

USB_LED F12 — Embedded USB-Blaster active LED

USER_PGM M6 — DIP - factory or user load on power-up

Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 4)

Schematic Signal Name I/O Standard

EPM2210

Pin Number

EP3CLS200

Pin Number Description

Table 2–6. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information

Board Reference Description Manufacturer

Manufacturing

Part Number

Manufacturer

Website

U22 IC - MAX II CPLD EPM2210

256FBGA -3 LF 2.5 V VCCINT

Altera

Corporation EPM2210F256C3N www.altera.com

Chapter 2: Board Components 2–11

Configuration, Status, and Setup Elements

This section describes the board's configuration, status, and setup elements.

Configuration

This section describes the FPGA, flash memory, and MAX

II CPLD EPM2210 System

Controller device programming methods supported by the Cyclone III LS FPGA

development board. The Cyclone III LS FPGA development board supports the

following three configuration methods:

■ Embedded USB-Blaster is the default method for configuring the FPGA at any

time using the Quartus II Programmer in JTAG mode with the supplied USB cable.

■ Flash memory download is used for storing FPGA images which the MAX

II

CPLD EPM2210 System Controller uses to configure the Cyclone III LS device

either on board power up or after the the PGM configure push-button switch (S8)

is pressed.

■ External USB-Blaster for configuring the FPGA using an external USB-Blaster.

FPGA Programming over Embedded USB-Blaster

The USB-Blaster is implemented using a USB Type-B connector (J4), a FTDI USB 2.0

PHY device (U11), and an Altera MAX IIZ CPLD (U13). This allows the configuration

of the FPGA using a USB cable directly connected between the USB port on the board

(J4) and a USB port of a PC running the Quartus II software. The JTAG chain is

normally mastered by the embedded USB-Blaster found in the MAX

IIZ CPLD

EPM240Z.

The embedded USB-Blaster is automatically disabled when an external USB-Blaster is

connected to the JTAG chain.

Figure 2–4 illustrates the JTAG chain.

2–12 Chapter 2: Board Components

Configuration, Status, and Setup Elements

For normal JTAG operation, the shunt jumper must be removed from the

JTAG_AT_SEL jumper (J12). To connect a device or interface to the chain, the

corresponding shunt must be installed onto the JTAG chain header (J11). Remove all

of the shunt jumpers to only have the FPGA in the chain.

The MAX

II CPLD EPM2210 System Controller must be in the chain to use the power

monitor or the Board Test System. For this setting, install the upper-most jumper

shunt onto the JTAG chain header (J11).

When a shunt is installed on the JTAG_AT_SEL jumper (J12), the default JTAG chain

breaks and the MAX II EPM2210 System Controller gains control of the FPGA JTAG.

For more information on the anti-tamper example design, refer to

<install_dir>\kits\cycloneIIILS_3cls200_fpga\examples\max2\at_example\

readme_at_example.txt.

Figure 2–4. JTAG Chain

Embedded

Blaster

GPIO

TCK

EP3CLS200

FPGA

EPM2210

System

Controller

HSMC

Port A

HSMC

Port B

GPIO

TMS

GPIO

TDO

GPIO

TDI

JTAG Master

GPIO

DISABLE

JTAG Master/Slave

Installed

HSMC

Card

Installed

HSMC

Card

TCK

TMS

TDI

TDO

TCK

TMS

TDI

TDO

TCK

TMS

TDI

TDO

TCK

TMS

TDI

TDO

JTAG Slave

Analog

Switch

Analog

Switch

EPM2210_JTAG_EN

HSMA_JTAG_EN

ALWAYS

ENABLED

(in chain)

SW2.5

10-pin

JTAG Connector

Flash

Memory

Analog

Switch

HSMB_JTAG_EN

Embedded

Blaster

Connection

USB

PHY

J4

J8

2x3 Jumper

J11

NC

SEL

JTAG_AT_SEL

J12

Break JTAG chain for

MAX II EPM2210

System Controller

GPIO to control

FPGA JTAG

Analog

Switch

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Altera Cyclone III LS Reference guide

Altera Cyclone III LS Reference guide

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