Altera Cyclone V GX FPGA Reference guide

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Reference Manual

Cyclone V GX FPGA Development Board

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Cyclone V GX FPGA Development Board Reference

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May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

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9001:2008

Registered

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

Contents

Chapter 1. Overview

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1

Board Component Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4

Chapter 2. Board Components

Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2

Featured Device: Cyclone V GX FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

I/O Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5

MAX V CPLD 5M2210 System Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

FPGA Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–10

FPGA Programming over Embedded USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–11

FPGA Programming from Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–13

FPGA Programming over External USB-Blaster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

Status Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15

Setup Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

Board Settings DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

JTAG Chain Control DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16

PCI Express Link Width DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

CPU Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

MAX V Reset Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Program Configuration Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Program Select Push Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–17

Clock Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

On-Board Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–18

Off-Board Clock Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–19

General User Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

User-Defined Push Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

User-Defined DIP Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–20

User-Defined LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

General LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

HSMC LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

PCI Express LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Character LCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–22

Debug Header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–23

Components and Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–24

10/100/1000 Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–26

HSMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–27

SDI Video Output/Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–31

Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

DDR3 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–33

Synchronous SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–42

Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–43

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–45

Power Distribution System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–46

Power Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–47

iv ContentsContents

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

Statement of China-RoHS Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–48

Chapter 3. Board Components Reference

Additional Information

Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

1. Overview

This document describes the hardware features of the Cyclone

®

V GX FPGA

development board, including the detailed pin-out and component reference

information required to create custom FPGA designs that interface with all

components of the board.

General Description

The Cyclone V GX FPGA development board provides a hardware platform for

developing and prototyping low-power, high-performance, and logic-intensive

designs using Altera’s Cyclone V GX FPGA device. The board provides a wide range

of peripherals and memory interfaces to facilitate the development of Cyclone V GX

designs.

One high-speed mezzanine card (HSMC) connectors are available to add additional

functionality via a variety of HSMCs available from Altera

®

and various partners.

f To see a list of the latest HSMCs available or to download a copy of the HSMC

specification, refer to the Development Board Daughtercards page of the Altera

website.

Design advancements and innovations, such as the PCI Express hard IP, partial

reconfiguration, and hard memory controller implementation ensure that designs

implemented in the Cyclone V GXs operate faster, with lower power, and have a

faster time to market than previous FPGA families.

f For more information on the following topics, refer to the respective documents:

■ Cyclone V device family, refer to the Cyclone V Device Handbook.

■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide.

■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification.

1–2 Chapter 1: Overview

Board Component Blocks

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

Board Component Blocks

The development board features the following major component blocks:

■ One Cyclone V GX FPGA (5CGXFC7D6F31C7NES) in a 896-pin FineLine BGA

(FBGA) package

■ 150,000 LEs

■ 136,880 adaptive logic modules (ALMs)

■ 7,024 Kbit (Kb) on-die block memory

■ Nine 3.125-Gbps high-speed transceivers

■ Seven fractional phase locked loops (PLLs)

■ 312 18x18-bit multipliers

■ 480 general purpose input/output (GPIO)

■ 1.1-V core voltage

■ FPGA configuration circuitry

■ MAX

®

V CPLD (5M2210ZF256C4N) in a 256-pin FBGA package as the System

Controller

■ Flash fast passive parallel (FPP) configuration

■ MAX II CPLD (EPM240M100C4N) in a 100-pin FBGA package as part of the

embedded USB-Blaster

TM

II for use with the Quartus

®

II Programmer

■ Clocking circuitry

■ Programmable clock generator for the FPGA reference clock input

■ 125-MHz LVDS oscillator for the FPGA reference clock input

■ 148.5/148.35-MHz LVDS VCXO for the FPGA reference clock input

■ 50-MHz single-ended oscillator for the FPGA and MAX V CPLD clock input

■ 100-MHz single-ended oscillator for the MAX V CPLD configuration clock

input

■ SMA input (LVPECL)

■ Memory

■ DDR3 SDRAM

■ Four 128-Mbyte (MB) device with a 16-bit data bus

■ Two 128-MB device with a 8-bit data bus

■ One 18-MB SSRAM

■ One 512-MB synchronous flash

Chapter 1: Overview 1–3

Board Component Blocks

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

■ General user input/output

■ LEDs and displays

■ Four user LEDs

■ One configuration load LED

■ One configuration done LED

■ One error LED

■ Four embedded USB-Blaster II status LEDs

■ Two HSMC interface link LEDs

■ Three PCI Express link width LEDs

■ Five Ethernet LEDs

■ One serial digital interface (SDI) carrier detect LED

■ One power on LED

■ One two-line character LCD display

■ Push buttons

■ One CPU reset push button

■ One MAX V reset push button

■ One program select push button

■ One program configuration push button

■ Three general user push buttons

■ DIP switches

■ Board settings DIP switch

■ JTAG chain control DIP switch

■ PCI Express link width DIP switch

■ General user DIP switch

■ Power supply

■ 14–20-V (laptop) DC input

■ PCI Express edge connector

■ Mechanical

■ PCI Express card standard size (6.600" x 4.199")

1–4 Chapter 1: Overview

Development Board Block Diagram

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

Development Board Block Diagram

Figure 1–1 shows a block diagram of the Cyclone V GX FPGA development board.

Handling the Board

When handling the board, it is important to observe the following static discharge

precaution:

c Without proper anti-static handling, the board can be damaged. Therefore, use

anti-static handling precautions when touching the board.

Figure 1–1. Cyclone V GX FPGA Development Board Block Diagram

LVDS/Single-Ended

128-MB

DDR3

128-MB

DDR3

2x16 LCD

Push Buttons

DIP Switches

LEDs

18-MB

SSRAM

512-MB

Flash

x4 Edge

Trigger SMA Out

REFCLK SMA In

Gigabit Ethernet

PHY

Embedded

USB-Blaster II

Type-B

USB 2.0

XCVR x1

SDI TX/RX

XCVR x1

Debug Header

x1

x11

x32

x4

x3

ADDR x25

DATA x16

CONFIG x16

XVCR x4

x80

CLKIN x1

CLKOUT x1

XCVR x4

JTAG Chain

x1 LVPECL

Programmable

Oscillator

x4

5

6

C

L

5M2210ZF256C4N

5CGXFC7D7F31C7NES

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

2. Board Components

This chapter introduces the major components on the Cyclone V GX FPGA

development board. Figure 2–1 illustrates the component locations and Table 2–1

provides a brief description of all component features of the board.

1 A complete set of schematics, a physical layout database, and GERBER files for the

development board reside in the Cyclone V GX FPGA development kit documents

directory.

f For information about powering up the board and installing the demonstration

software, refer to the Cyclone V GX FPGA Development Kit User Guide.

This chapter consists of the following sections:

■ “Board Overview”

■ “Featured Device: Cyclone V GX FPGA” on page 2–5

■ “MAX V CPLD 5M2210 System Controller” on page 2–6

■ “FPGA Configuration” on page 2–10

■ “Clock Circuitry” on page 2–18

■ “General User Input/Output” on page 2–20

■ “Components and Interfaces” on page 2–24

■ “Memory” on page 2–33

■ “Power Supply” on page 2–45

■ “Statement of China-RoHS Compliance” on page 2–48

2–2 Chapter 2: Board Components

Board Overview

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

Board Overview

This section provides an overview of the Cyclone V GX FPGA development board,

including an annotated board image and component descriptions. Figure 2–1 shows

an overview of the board features.

Table 2–1 describes the components and lists their corresponding board references.

Figure 2–1. Overview of the Cyclone V GX FPGA Development Board Features

Clock Input SMA

Connector

(J16, J17)

Max V Reset

Push Button (S1)

General User

Push Buttons

(S3-S5)

Flash x16

Memory (U18)

PCI Express Edge

Connector (J19)

DDR3B x32

+ ECC Memory

(U6, U15, U19)

DDR3A x32

+ ECC Memory

(U21, U22, U23)

DC Input

Jack (J9)

Character

LCD (J18)

CPU Reset

Push Button (S2)

Power

Switch

(SW1)

User LEDs

(D4-D7)

MAX V CPLD

EPM2210 System

Controller (U12)

Clock Output

SMA Connector

(J4)

HSMC Port

(J1)

Configuration Done,

Load, and Error

LEDs (D15-D17)

Program Config,

Program Select

Push Buttons

(S6, S7)

Program Select

LEDs (D12-D14)

Transceiver SMA

Connectors

RX (J2, J6)

TX (J3, J7)

USB Type-B

Connector (J12)

SDI Video

Port (J5, J10)

Debug Header

(J14)

Gigabit Ethernet

Port (J11)

JTAG Chain

Header

(J13)

Fan Power

Header (J8)

PCI Express

Mode

DIP Switch (SW4)

JTAG Chain

Control

DIP Switch (SW5)

Board Settings

DIP switch (SW3)

Cyclone V GX

FPGA (U11)

Table 2–1. Board Components (Part 1 of 3)

Board Reference Type Description

Featured Devices

U11 FPGA Cyclone V GX, 5CGXFC7D6F31C7NES, 896-pin FBGA.

U12 CPLD MAX V CPLD, 5M2210ZF256C4N, 256-pin FBGA.

Configuration, Status, and Setup Elements

J13 JTAG chain header

Provides access to the JTAG chain and disables the embedded

USB-Blaster II when using an external USB-Blaster cable.

SW5 JTAG chain control DIP switch Remove or include devices in the active JTAG chain.

J12 USB type-B connector

USB interface for FPGA programming and debugging through the

embedded USB-Blaster II JTAG via a type-B USB cable.

Chapter 2: Board Components 2–3

Board Overview

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

SW3 Board settings DIP switch

Controls the MAX V CPLD 5M2210 System Controller functions such

as clock enable, SMA clock input control, and which image to load

from flash memory at power-up.

SW4 PCI Express DIP switch

Controls the PCI Express lane width by connecting the

prsnt

pins

together on the PCI Express edge connector.

S7 Program select push button

Toggles the program select LEDs, which selects the program image

that loads from flash memory to the FPGA.

S6

Program configuration push

button

Load image from flash memory to the FGPA based on the settings of

the program select LEDs.

D15 Configuration done LED Illuminates when the FPGA is configured.

D17 Load LED

Illuminates when the MAX V CPLD 5M2210 System Controller is

actively configuring the FPGA.

D16 Error LED Illuminates when the FPGA configuration from flash memory fails.

D23 Power LED Illuminates when 5.0-V power is present.

D12, D13, D14 Program select LEDs

Illuminates to show the LED sequence that determines which flash

memory image loads to the FPGA when you press the program select

push button. Refer to Table 2–6 for the LED settings.

D19, D20, D21,

D22, D24

Ethernet LEDs

Illuminates to show the connection speed as well as transmit or

receive activity.

D1, D2 HSMC port LEDs You can configure these LEDs to indicate transmit or receive activity.

D3 HSMC port present LED Illuminates when a daughtercard is plugged into the HSMC port A.

D8, D9, D10 PCI Express link LEDs

You can configure these LEDs to indicate the PCI Express link width

(x1, x4) and Gen1 link.

Clock Circuitry

U25 Quad-output oscillator

Programmable oscillator with default frequencies of 125 MHz,

409.6 MHz, 156.25 MHz, and 100 MHz. The frequency is

programmable using the clock control GUI running on the MAX V

CPLD 5M2210 System Controller.

X2 148.5-MHz oscillator

148.500-MHz voltage controlled crystal oscillator for the serial digital

interface (SDI) video. This oscillator is programmable to any frequency

between 20–810 MHz using the clock control GUI running on the

MAX V CPLD 5M2210 System Controller.

X4 50-MHz oscillator 50.000-MHz crystal oscillator for general purpose logic.

X1 100-MHz oscillator

100.000-MHz crystal oscillator for the MAX V CPLD 5M2210 System

Controller.

J2, J3, J6, J7 Transceiver SMA connectors Drives serial data input/output to or from the SDI video port.

J16, J17 Clock input SMA connectors

Drive LVPECL-compatible clock inputs into the clock multiplexer

buffer.

J4 Clock output SMA connector Drive out 2.5-V CMOS clock output from the FPGA.

General User Input/Output

D4–D7 User LEDs Four user LEDs. Illuminates when driven low.

SW2 User DIP switch Quad user DIP switches. When the switch is ON, a logic 0 is selected.

S2 CPU reset push button Reset the FPGA logic.

Table 2–1. Board Components (Part 2 of 3)

Board Reference Type Description

2–4 Chapter 2: Board Components

Board Overview

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

S1 MAX V reset push button Reset the MAX V CPLD 5M2210 System Controller.

S3, S4, S5 General user push buttons Three user push buttons. Driven low when pressed.

Memory Devices

U6, U15, U21,

U22, U19, U23

DDR3 x32 memory

Four 128-MB DDR3 SDRAM with a 16-bit data bus and two 128-MB

DDR3 SDRAM with a 8-bit data bus.

U37 SSRAM x16 memory

18-MB standard synchronous RAM with a 12-bit data bus and 4-bit

parity.

U18 Flash x16 memory

512-MB synchronous flash devices with a 16-bit data bus for

non-volatile memory.

Communication Ports

J19 PCI Express edge connector

Gold-plated edge fingers connector for up to ×8 signaling in Gen1

mode.

J1 HSMC port

Provides eight transceiver channels and 84 CMOS or 17 LVDS

channels per the HSMC specification.

J11 Gigabit Ethernet port

RJ-45 connector which provides a 10/100/1000 Ethernet connection

via a Marvell 88E1111 PHY and the FPGA-based Altera Triple Speed

Ethernet MegaCore function in RGMII mode.

Video and Display Ports

J18 Character LCD

Connector that interfaces to a provided 16 character × 2 line LCD

module along with two standoffs.

J5, J10 SDI video port

Two 75-Ω sub-miniature version B (SMB) connectors that provide a

full-duplex SDI interface through a LMH0303 cable driver and

LMH0384 cable equalizer.

Power Supply

J19 PCI Express edge connector

Interfaces to a PCI Express root port such as an appropriate PC

motherboard.

J9 DC input jack

Accepts a 14–20-V DC power supply. Do not use this input jack while

the board is plugged into a PCI Express slot.

SW1 Power switch

Switch to power on or off the board when power is supplied from the

DC input jack.

Table 2–1. Board Components (Part 3 of 3)

Board Reference Type Description

Chapter 2: Board Components 2–5

Featured Device: Cyclone V GX FPGA

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

Featured Device: Cyclone V GX FPGA

The Cyclone V GX FPGA development board features a Cyclone V GX

5CGXFC7D6F31C7NES device (U11) in a 896-pin FBGA package.

f For more information about Cyclone V device family, refer to the Cyclone V Device

Handbook.

Table 2–2 describes the features of the Cyclone V GX 5CGXFC7D6F31C7NES device.

I/O Resources

The Cyclone V GX 5CGXFC7D6F31C7NES device has total of 480 user I/Os and nine

transceiver channels. Table 2–3 lists the Cyclone V GX device I/O pin count and usage

by function on the board.

Table 2–2. Cyclone V GX FPGA Features

ALMs

Equivalent

LEs

M10K RAM

Blocks

Total RAM

(Kbits)

18-bit × 18-bit

Multipliers

PLLs Transceivers Package Type

136,880 150,000 1,726 7,024 312 7 9 896-pin FBGA

Table 2–3. Cyclone V GX Device I/O Pin Count

Function I/O Standard I/O Count Special Pins

DDR3A 1.5-V SSTL 81 One differential x4 DQS pin

DDR3B 1.5-V SSTL 81 One differential x4 DQS pin

Flash, SSRAM, and MAX V FSM bus 2.5-V CMOS 80 —

PCI Express x4 port 2.5-V CMOS + XCVR 13 One reference clock

HSMA port 2.5-V CMOS + LVDS + XCVR 93 Four transceivers, 17 LVDS, I

2

C

Gigabit Ethernet port 2.5-V CMOS + LVDS 6 —

Embedded USB-Blaster II 2.5-V CMOS 19 —

SDI video port 2.5-V CMOS + XCVR 6 One reference clock

Push buttons 2.5-V CMOS 4 One

DEV_CLRn

DIP switches 2.5-V CMOS 4 —

Character LCD 2.5-V CMOS 11 —

LEDs 2.5-V CMOS 7 —

Clock or Oscillators 2.5-V CMOS + LVDS + PCML 18 Nine reference clock

Total I/O Used: 423

2–6 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the

following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Control and status registers for remote system update

Figure 2–2 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Table 2–4 lists the I/O signals present on the MAX V CPLD 5M2210 System

Controller. The signal names and functions are relative to the MAX V device.

Figure 2–2. MAX V CPLD 5M2210 System Controller Block Diagram

Information

Register

Embedded

USB-Blaster II

Si571

Controller

Si5538

Controller

SLD-HUB

PFL

FSM Bus

MAX V CPLD System Controller

Power

Measurement

Results

Virtual-JTAG

PC

FPGA

LTC2418

Controller

Flash

Decoder

Encoder

GPIO

JTAG Control

SSRAM

Control

Register

Si571

Programmable

Oscillator

Si5338

Programmable

Oscillator

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 5)

Board

Reference (U12)

Schematic Signal Name I/O Standard Description

N4

5M2210_JTAG_TMS

2.5-V MAX V JTAG TMS

E13

CLK50_EN

2.5-V 50 MHz oscillator enable

J5

CLK_CONFIG

2.5-V 100 MHz configuration clock input

N14

CLK_ENABLE

2.5-V DIP switch for clock oscillator enable

N15

CLK_SEL

2.5-V DIP switch for clock select—SMA or oscillator

J12

CLKIN_50_MAXV

2.5-V 50 MHz clock input

L5

CLOCK_SCL

2.5-V Programmable oscillator I

2

C clock

K4

CLOCK_SDA

2.5-V Programmable oscillator I

2

C data

R7

CPU_RESETN

2.5-V FPGA reset push button

M16

EXTRA_SIG0

2.5-V Embedded USB-Blaster II interface. Reserved for future use

Chapter 2: Board Components 2–7

MAX V CPLD 5M2210 System Controller

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

P9

EXTRA_SIG1

2.5-V Embedded USB-Blaster II interface. Reserved for future use

M8

EXTRA_SIG2

2.5-V Embedded USB-Blaster II interface. Reserved for future use

P15

FACTORY_LOAD

2.5-V DIP switch to load factory or user design at power-up

R14

FACTORY_REQUEST

2.5-V

Embedded USB-Blaster II request to send FACTORY

command

N12

FACTORY_STATUS

2.5-V Embedded USB-Blaster II FACTORY command status

E12

FAN_FORCE_ON

2.5-V DIP switch to on or off the fan

T5

FLASH_ADVN

2.5-V FSM bus flash memory address valid

P7

FLASH_CEN

2.5-V FSM bus flash memory chip enable

M6

FLASH_CLK

2.5-V FSM bus flash memory clock

N6

FLASH_OEN

2.5-V FSM bus flash memory output enable

N7

FLASH_RDYBSYN

2.5-V FSM bus flash memory ready

R6

FLASH_RESETN

2.5-V FSM bus flash memory reset

R5

FLASH_WEN

2.5-V FSM bus flash memory write enable

H13

FPGA_CONF_DONE

2.5-V FPGA configuration done LED

H16

FPGA_CONFIG_D0

2.5-V FPGA configuration data

G15

FPGA_CONFIG_D1

2.5-V FPGA configuration data

H15

FPGA_CONFIG_D2

2.5-V FPGA configuration data

C15

FPGA_CONFIG_D3

2.5-V FPGA configuration data

E16

FPGA_CONFIG_D4

2.5-V FPGA configuration data

D16

FPGA_CONFIG_D5

2.5-V FPGA configuration data

F14

FPGA_CONFIG_D6

2.5-V FPGA configuration data

E15

FPGA_CONFIG_D7

2.5-V FPGA configuration data

G13

FPGA_CONFIG_D8

2.5-V FPGA configuration data

H14

FPGA_CONFIG_D9

2.5-V FPGA configuration data

D15

FPGA_CONFIG_D10

2.5-V FPGA configuration data

G16

FPGA_CONFIG_D11

2.5-V FPGA configuration data

F16

FPGA_CONFIG_D12

2.5-V FPGA configuration data

E14

FPGA_CONFIG_D13

2.5-V FPGA configuration data

J13

FPGA_CONFIG_D14

2.5-V FPGA configuration data

F15

FPGA_CONFIG_D15

2.5-V FPGA configuration data

M13

FPGA_CVP_CONFDONE

2.5-V FPGA configuration via protocol done LED

P4

FPGA_DCLK

2.5-V FPGA configuration clock

L14

FPGA_NCONFIG

2.5-V FPGA configuration active

P5

FPGA_NSTATUS

2.5-V FPGA configuration ready

J14

FPGA_PR_DONE

2.5-V FPGA partial reconfiguration done

M15

FPGA_PR_ERROR

2.5-V FPGA partial reconfiguration error

D13

FPGA_PR_READY

2.5-V FPGA partial reconfiguration ready

F13

FPGA_PR_REQUEST

2.5-V FPGA partial reconfiguration request

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 2 of 5)

Board

Reference (U12)

Schematic Signal Name I/O Standard Description

2–8 Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

J4

FSM_A0

2.5-V FSM address bus

G5

FSM_A1

2.5-V FSM address bus

F5

FSM_A2

2.5-V FSM address bus

F6

FSM_A3

2.5-V FSM address bus

E5

FSM_A4

2.5-V FSM address bus

D1

FSM_A5

2.5-V FSM address bus

D2

FSM_A6

2.5-V FSM address bus

E1

FSM_A7

2.5-V FSM address bus

E2

FSM_A8

2.5-V FSM address bus

E4

FSM_A9

2.5-V FSM address bus

H4

FSM_A10

2.5-V FSM address bus

F1

FSM_A11

2.5-V FSM address bus

F2

FSM_A12

2.5-V FSM address bus

G3

FSM_A13

2.5-V FSM address bus

G2

FSM_A14

2.5-V FSM address bus

J2

FSM_A15

2.5-V FSM address bus

J3

FSM_A16

2.5-V FSM address bus

G1

FSM_A17

2.5-V FSM address bus

F3

FSM_A18

2.5-V FSM address bus

D3

FSM_A19

2.5-V FSM address bus

C3

FSM_A20

2.5-V FSM address bus

G4

FSM_A21

2.5-V FSM address bus

F4

FSM_A22

2.5-V FSM address bus

E3

FSM_A23

2.5-V FSM address bus

C2

FSM_A24

2.5-V FSM address bus

H2

FSM_A25

2.5-V FSM address bus

H3

FSM_A26

2.5-V FSM address bus

R3

FSM_D0

2.5-V FSM data bus

T2

FSM_D1

2.5-V FSM data bus

K1

FSM_D2

2.5-V FSM data bus

L1

FSM_D3

2.5-V FSM data bus

K3

FSM_D4

2.5-V FSM data bus

K2

FSM_D5

2.5-V FSM data bus

M2

FSM_D6

2.5-V FSM data bus

L2

FSM_D7

2.5-V FSM data bus

M3

FSM_D8

2.5-V FSM data bus

M1

FSM_D9

2.5-V FSM data bus

N1

FSM_D10

2.5-V FSM data bus

N3

FSM_D11

2.5-V FSM data bus

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 3 of 5)

Board

Reference (U12)

Schematic Signal Name I/O Standard Description

Chapter 2: Board Components 2–9

MAX V CPLD 5M2210 System Controller

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

N2

FSM_D12

2.5-V FSM data bus

L3

FSM_D13

2.5-V FSM data bus

R1

FSM_D14

2.5-V FSM data bus

P2

FSM_D15

2.5-V FSM data bus

L15

HSMA_PRSNTN

2.5-V HSMC port A present

L6

JTAG_5M2210_TDI

2.5-V MAX V CPLD JTAG chain data in

M5

JTAG_5M2210_TDO

2.5-V MAX V CPLD JTAG chain data out

P3

JTAG_TCK

2.5-V JTAG chain clock

P11

M570_CLOCK

2.5-V

25-MHz clock to embedded USB-Blaster II for sending

FACTORY command

P12

M570_PCIE_JTAG_EN

2.5-V

Low signal to disable the embedded USB-Blaster II when PCI

Express is the master to the JTAG chain

B10

MAX5_BEN0

2.5-V FSM bus MAX V byte enable 0

A9

MAX5_BEN1

2.5-V FSM bus MAX V byte enable 1

C11

MAX5_BEN2

2.5-V FSM bus MAX V byte enable 2

C10

MAX5_BEN3

2.5-V FSM bus MAX V byte enable 3

P8

MAX5_CLK

2.5-V FSM bus MAX V clock

B12

MAX5_CSN

2.5-V FSM bus MAX V chip select

C12

MAX5_OEN

2.5-V FSM bus MAX V output enable

A10

MAX5_WEN

2.5-V FSM bus MAX V write enable

L13

MAX_CONF_DONEN

2.5-V Embedded USB-Blaster II configuration done LED

P14

MAX_ERROR

2.5-V FPGA configuration error LED

D14

MAX_LOAD

2.5-V FPGA configuration active LED

M9

MAX_RESETN

2.5-V MAX V reset push button

F11

MSEL0

2.5-V FPGA mode select 0

F12

MSEL1

2.5-V FPGA mode select 1

K12

MSEL2

2.5-V FPGA mode select 2

M14

MSEL3

2.5-V FPGA mode select 3

N13

MSEL4

2.5-V FPGA mode select 4

J15

OVERTEMP

2.5-V Temperature monitor fan enable

M7

PCIE_JTAG_EN

2.5-V DIP switch to enable the PCI Express JTAG master

L12

PGM_CONFIG

2.5-V Load the flash memory image identified by the PGM LEDs

M4

PGM_LED0

2.5-V Flash memory PGM select indicator 0

K13

PGM_LED1

2.5-V Flash memory PGM select indicator 1

L11

PGM_LED2

2.5-V Flash memory PGM select indicator 2

L4

PGM_SEL

2.5-V Toggles the

PGM_LED[2:0]

LED sequence

K14

SDI_FAULT

2.5-V SDI data transmission fault

N5

SDI_RX_BYPASS

2.5-V SDI equalization bypass

P6

SDI_RX_EN

2.5-V SDI receive enable

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 4 of 5)

Board

Reference (U12)

Schematic Signal Name I/O Standard Description

2–10 Chapter 2: Board Components

FPGA Configuration

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

FPGA Configuration

This section describes the FPGA, flash memory, and MAX V CPLD 5M2210 System

Controller device programming methods supported by the Cyclone V GX FPGA

development board.

The Cyclone V GX development board supports the following three configuration

methods:

■ Embedded USB-Blaster is the default method for configuring the FPGA using the

Quartus II Programmer in JTAG mode with the supplied USB cable.

■ Flash memory download for configuring the FPGA using stored images from the

flash memory on either power-up or pressing the program configuration

push button (S6).

■ External USB-Blaster for configuring the FPGA using an external USB-Blaster that

connects to the JTAG chain header (J13).

K5

SDI_SCL

2.5-V SDI clock

L16

SDI_SDA

2.5-V SDI data

N16

SDI_TX_EN

2.5-V SDI transmit enable

R12

SECURITY_MODE

2.5-V

DIP switch for the embedded USB-Blaster II to send FACTORY

command at power up

K16

SENSE_CS0N

2.5-V Power monitor chip select

H1

SENSE_SCK

2.5-V Power monitor SPI clock

G12

SENSE_SDI

2.5-V Power monitor SPI data in

C14

SENSE_SDO

2.5-V Power monitor SPI data out

J1

SI571_EN

2.5-V Si571 programmable VCXO enable

R8

USB_CFG0

2.5-V Embedded USB-Blaster II interface. Reserved for future use

T7

USB_CFG1

2.5-V Embedded USB-Blaster II interface. Reserved for future use

R4

USB_CFG2

2.5-V Embedded USB-Blaster II interface. Reserved for future use

R9

USB_CFG3

2.5-V Embedded USB-Blaster II interface. Reserved for future use

T11

USB_CFG4

2.5-V Embedded USB-Blaster II interface. Reserved for future use

T15

USB_CFG5

2.5-V Embedded USB-Blaster II interface. Reserved for future use

T13

USB_CFG6

2.5-V Embedded USB-Blaster II interface. Reserved for future use

T9

USB_CFG7

2.5-V Embedded USB-Blaster II interface. Reserved for future use

T10

USB_CFG8

2.5-V Embedded USB-Blaster II interface. Reserved for future use

T4

USB_CFG9

2.5-V Embedded USB-Blaster II interface. Reserved for future use

T8

USB_CFG10

2.5-V Embedded USB-Blaster II interface. Reserved for future use

T12

USB_CFG11

2.5-V Embedded USB-Blaster II interface. Reserved for future use

H5

USB_CLK

2.5-V Embedded USB-Blaster II interface clock

Table 2–4. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 5 of 5)

Board

Reference (U12)

Schematic Signal Name I/O Standard Description

Chapter 2: Board Components 2–11

FPGA Configuration

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

FPGA Programming over Embedded USB-Blaster

This configuration method implements a USB type-B connector (J12), a USB 2.0 PHY

device (U16), and an Altera MAX II CPLD EPM240M100C4N (U20) to allow FPGA

configuration using a USB cable. This USB cable connects directly between the USB

type-B connector on the board and a USB port of a PC running the Quartus II

software.

The embedded USB-Blaster in the MAX II CPLD EPM570F100C5N normally masters

the JTAG chain.

Figure 2–3 illustrates the JTAG chain.

The JTAG chain control DIP switch (SW5) controls the jumpers shown in Figure 2–3.

To connect a device or interface in the chain, their corresponding switch must be in

the OFF position. Slide all the switches in the ON position to only have the FPGA in

the chain.

1 The MAX V CPLD 5M2210 System Controller must be in the JTAG chain to use some

of the GUI interfaces.

Figure 2–3. JTAG Chain

Embedded

USB-Blaster II

GPIO

TCK

Cyclone V GX

FPGA

Analog

Switch

MAX V

System

Controller

HSMC

Port

GPIO

TMS

GPIO

TDO

GPIO

TDI

JTAG Master

GPIO

Enable

Disable

Enable

JTAG Slave

HSMC

TCK

TMS

TDI

TDO

TCK

2.5 V

TMS

TDI

TDO

TCK

TMS

TDI

TDO

JTAG Slave

Analog

Switch

Always

Enabled

(in JTAG chain)

DIP Switch

10-pin

JTAG Header

Flash

Memory

PCI Express

Edge

Connector

JTAG Master

PCI Express

Motherboard

TCK

TMS

TDI

TDO

Level

Shifter

2.5 V

2–12 Chapter 2: Board Components

FPGA Configuration

Cyclone V GX FPGA Development Board May 2013 Altera Corporation

Reference Manual

Table 2–5 lists the USB 2.0 PHY schematic signal names and their corresponding

Cyclone V GX device pin numbers.

Table 2–5. USB 2.0 PHY Schematic Signal Names and Functions (Part 1 of 2)

Board Reference

(U16)

Schematic

Signal Name

Cyclone V GX

Pin Number

I/O Standard Description

C1

24M_XTALIN

— 3.3-V Crystal oscillator input

C2

24M_XTALOUT

— 3.3-V Crystal oscillator output

E1

FX2_D_N

— 3.3-V USB 2.0 PHY data

E2

FX2_D_P

— 3.3-V USB 2.0 PHY data

H7

FX2_FLAGA

— 3.3-V Slave FIFO output status

G7

FX2_FLAGB

— 3.3-V Slave FIFO output status

H8

FX2_FLAGC

— 3.3-V Slave FIFO output status

G6

FX2_PA1

— 3.3-V USB 2.0 PHY port A interface

F8

FX2_PA2

— 3.3-V USB 2.0 PHY port A interface

F7

FX2_PA3

— 3.3-V USB 2.0 PHY port A interface

F6

FX2_PA4

— 3.3-V USB 2.0 PHY port A interface

C8

FX2_PA5

— 3.3-V USB 2.0 PHY port A interface

C7

FX2_PA6

— 3.3-V USB 2.0 PHY port A interface

C6

FX2_PA7

— 3.3-V USB 2.0 PHY port A interface

H3

FX2_PB0

— 3.3-V USB 2.0 PHY port B interface

F4

FX2_PB1

— 3.3-V USB 2.0 PHY port B interface

H4

FX2_PB2

— 3.3-V USB 2.0 PHY port B interface

G4

FX2_PB3

— 3.3-V USB 2.0 PHY port B interface

H5

FX2_PB4

— 3.3-V USB 2.0 PHY port B interface

G5

FX2_PB5

— 3.3-V USB 2.0 PHY port B interface

F5

FX2_PB6

— 3.3-V USB 2.0 PHY port B interface

H6

FX2_PB7

— 3.3-V USB 2.0 PHY port B interface

A8

FX2_PD0

— 3.3-V USB 2.0 PHY port D interface

A7

FX2_PD1

— 3.3-V USB 2.0 PHY port D interface

B6

FX2_PD2

— 3.3-V USB 2.0 PHY port D interface

A6

FX2_PD3

— 3.3-V USB 2.0 PHY port D interface

B3

FX2_PD4

— 3.3-V USB 2.0 PHY port D interface

A3

FX2_PD5

— 3.3-V USB 2.0 PHY port D interface

C3

FX2_PD6

— 3.3-V USB 2.0 PHY port D interface

A2

FX2_PD7

— 3.3-V USB 2.0 PHY port D interface

B8

FX2_RESETN

V21 3.3-V Embedded USB-Blaster hard reset

F3

FX2_SCL

— 3.3-V USB 2.0 PHY serial clock

G3

FX2_SDA

— 3.3-V USB 2.0 PHY serial data

A1

FX2_SLRDN

— 3.3-V Read strobe for slave FIFO

B1

FX2_SLWRN

— 3.3-V Write strobe for slave FIFO

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Altera Cyclone V GX FPGA Reference guide

Altera Cyclone V GX FPGA Reference guide

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