DIPSwitchSettings
CompatibilitywithMIL‐STDcircuits
ThedriversandreceiversforV.11signalsarecompatiblewiththeMIL‐STDbalancedspecificationsandthe
V.10interfaceissimilartoMIL‐STDunbalanced.MIL‐STD‐100signalsusethesamenegativeMARKcondition
asTIAcircuits,sothereisnoneedtoinverttheTDandRDsignals.MIL‐STD‐188‐114Aisset‐upforusercontrol
oftheMARKlevel,sotheneedfordatainversionattheFOMwillneedtobemadeonacase‐by‐casebasis.
IftheMIL‐STDinterfaceusesanyunbalancedsignals,suchasMIL‐STD‐188C(notethatthisstandardusesa
positiveMARK),thenprovisionswillneedtobemadetoexternallybiasonesideofthereceiversontheFOM
tousethemsingle‐ended.NotethattheMILstandardsareonlyanelectricalspecificationanddonotspecifya
pinoutorconnectortype,soacustomcablewillberequiredinmanycases.
Asynchronous,Isochronous,orSynchronousoperation
TheFOMistransparenttodataandclockingformats,sotherearenoswitchsettingsfordistinguishingthe
differentmodesofoperation.WhenapairofFOM‐1090unitsisusedasmodemlinkbetweentwoDTEs,allof
theinputsignalsaretransferredtothecrossed‐overcorrespondingoutputs(i.e.‐TTfromtheDTEisprovided
asRToutoftheFOM‐1090)attheoppositeend.WhentheFOMisusedinSendTimingapplications,certain
switchoptionsmaybeusedtoeliminateclockingissuesthatmayarise.Thoseoptionsareexplainedbelow.
SendDataRegenerationwhenusingSendTimingfromtheDCE
ThetypicalSendTimingset‐uphastheDCEsupplyingallclocks.TheSTsignalisgeneratedattheDCEandthen
carriedtotheremoteDTE.Inreturn,theremoteDTEthenclockstheSendDataoutofitselfontherisingedge
ofthesuppliedSTsignal.TheSendDataiscarriedbacktotheDCEwhereitisclockedin,samplingthedatabit
onthefallingedgeofthegeneratedSTclock.Alignmentproblemsariseduetopropagationdelaywhencertain
combinationsofdatarateandcabledistance(bothcopperandfiber)resultintheSendDatatransitions
occurringnearthefallingedgeoftheSTsignalattheDCE.
Asanexample,usingaroughnumberof4nsdelaypermeterofcable,25metersofcablewitha2.5mHzclock
willcausea180degreeshiftintheST‐SDrelationshipattheDCEinterface.(Thereisactually50metersof
propagationdelaysincetheclocktravels25metersinonedirectionandthedatatravels25metersinthe
other).ThisiswithouttakingintoaccountthedelaysofthelinedriversandreceiversintheDTE.
TheFOM‐1091regenerationoptionsmakeupforthisintwoways.ThefirstistocorrectforanySD‐ST
misalignmentduetopropagationdelayfromtheFOM‐1091totheDCEbydelayingtheSDsignaloutofthe
FOMbyonehalfofaSTclockcycle.ThesecondistheFOMhastheabilitytoretimetheincomingSDdata
internallywiththeincomingSTsignal,whichremovesanysamplingjitterfromtheSDsignalaswellas
correctingforpropagationdelays.
WhilethefallingedgeoftheSTsignalfromtheDCEisideallylocatedmid‐bitoftheSDsignalcomingintothe
DCE,itisnotnecessaryforittobemid‐bit.Infact,it’susuallynotmid‐bitduetodelays.Thisisoften
misunderstood.Theactualrequirementisthattheset‐uptimefortheregisterthattheSDsignalisbeing
loadedintobemetandthisisusuallyafractionoftheavailablebittime.Theonlytimethereisaproblemis
whenthefallingedgeoftheSTistooclosetotheSDtransitionsattheDCEinterfaceandthispreventstheset‐
uptimefrombeingmet.IftheSTfallingedgeisfarenoughawayfromtheSDtransitionedges(whenthenew
SDdatabithasmettheset‐uptime),theDCEwillstillclockthedatareliablyeventhoughitisn’tmid‐bit.Thisis
whymanySTtimingset‐upswillworkwithnoregenerationrequiredatall.Whentheedgesaretoocloseat
theDCEtheFOMwillneedtoretimethedataontheoppositeedgeoftheSTsignalbysettingswitch1.8to
ON.Thiswillallowthatwhenthepropagationdelaysaretakenintoaccounttheedgeshaveskewedenoughto
meettheset‐uptimeattheDCE.
Notethatininstallationswherethedataratemaybechangedorthecablelengthsmaychangeduetopatch
panelroutingofequipment,it’sentirelypossiblethatacombinationofswitchsettingsthatworksinone
scenariowillnotworkinanother.Theonlysolutiontothesesituationsistoinsertmoredelayinoneormore
oftheconfigurationsbyaddingtocablelengthuntilallofthescenarioswillworkwiththesameswitch
settings.