NXP MPC8541E Reference guide

MPC8555E PowerQUICC™ III

Integrated Processor

Family Reference Manual

Supports:

MPC8555E

MPC8541E

MPC8555ERM

Rev. 2

10/2006

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81829 Muenchen, Germany

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+49 89 92103 559 (German)

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Document Number: MPC8555ERM

Rev. 2, 10/2006

Part I—Overview I

Overview 1

Memory Map 2

Signal Descriptions 3

Reset, Clocking, and Initialization 4

Part II—e500 Core Complex and L2 Cache II

Core Complex Overview 5

Core Register Summary 6

L2 Look-Aside Cache/SRAM 7

Part III—Memory, Security, and I/O Interfaces III

e500 Coherency Module 8

DDR Memory Controller 9

Programmable Interrupt Controller 10

I

2

C Interface 11

DUART 12

Local Bus Controller 13

Three-Speed Ethernet Controllers 14

DMA Controller 15

PCI Bus Interface 16

Security Engine (SEC) 2.0 17

Part IV—Global Functions and Debug IV

Global Utilities 18

Performance Monitor 19

Debug Features and Watchpoint Facility 20

I Part I—Overview

1 Overview

2 Memory Map

3 Signal Descriptions

4 Reset, Clocking, and Initialization

II Part II—e500 Core Complex and L2 Cache

5 Core Complex Overview

6 Core Register Summary

7 L2 Look-Aside Cache/SRAM

III Part III—Memory, Security, and I/O Interfaces

8 e500 Coherency Module

9 DDR Memory Controller

10 Programmable Interrupt Controller

11 I

2

C Interface

12 DUART

13 Local Bus Controller

14 Three-Speed Ethernet Controllers

15 DMA Controller

16 PCI Bus Interface

17 Security Engine (SEC) 2.0

IV Part IV—Global Functions and Debug

18 Global Utilities

19 Performance Monitor

20 Debug Features and Watchpoint Facility

Part V—CPM Features V

Communications Processor Module Overview 21

CPM Interrupt Controller 22

Serial Interface with Time-Slot Assigner 23

CPM Multiplexing 24

Baud-Rate Generators (BRGs) 25

CPM Timers 26

SDMA Channels 27

Serial Communications Controllers (SCCs) 28

SCC UART Mode 29

SCC HDLC Mode 30

SCC BISYNC Mode 31

SCC Transparent Mode 32

SCC AppleTalk Mode 33

QUICC Multi-Channel Controller (QMC) 34

Universal Serial Bus Controller 35

Serial Management Controllers (SMCs) 36

Fast Communications Controllers (FCCs) 37

FCC HDLC Controller 38

FCC Transparent Controller 39

CPM Fast Ethernet Controller 40

ATM Controller 41

ATM A A L 2 42

Serial Peripheral Interface (SPI) 43

I

2

C Controller 44

Parallel I/O Ports 45

Appendix A—MPC8541E A

Appendix B—Revision History B

Glossary GLO

Index 1 Register Index (Memory-Mapped Registers) REG

Index 2 General Index IND

Index 3 CPM Index CPM

V Part V—CPM Features

21 Communications Processor Module Overview

22 CPM Interrupt Controller

23 Serial Interface with Time-Slot Assigner

24 CPM Multiplexing

25 Baud-Rate Generators (BRGs)

26 CPM Timers

27 SDMA Channels

28 Serial Communications Controllers (SCCs)

29 SCC UART Mode

30 SCC HDLC Mode

31 SCC BISYNC Mode

32 SCC Transparent Mode

33 SCC AppleTalk Mode

34 QUICC Multi-Channel Controller (QMC)

35 Universal Serial Bus Controller

36 Serial Management Controllers (SMCs)

37 Fast Communications Controllers (FCCs)

38 FCC HDLC Controller

39 FCC Transparent Controller

40 CPM Fast Ethernet Controller

41 ATM Controller

42 ATM AAL2

43 Serial Peripheral Interface (SPI)

44 I

2

C Controller

45 Parallel I/O Ports

A Appendix A—MPC8541E

B Appendix B—Revision History

GLO Glossary

REG Index 1 Register Index (Memory-Mapped Registers)

IND Index 2 General Index

CPM Index 3 CPM Index

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Freescale Semiconductor vii

Contents

Paragraph

Number Title

Page

Number

Contents

About This Book

Audience...........................................................................................................................cix

Organization......................................................................................................................cix

Suggested Reading......................................................................................................... cxiii

General Information................................................................................................... cxiii

Related Documentation.............................................................................................. cxiii

Conventions ....................................................................................................................cxiv

Signal Conventions......................................................................................................cxv

Acronyms and Abbreviations ..........................................................................................cxv

Part I

Overview

Chapter 1

Overview

1.1 Introduction...................................................................................................................... 1-1

1.2 MPC8555E Overview...................................................................................................... 1-2

1.2.1 Key Features................................................................................................................ 1-2

1.3 MPC8555E Architecture Overview................................................................................. 1-9

1.3.1 e500 Core Overview.................................................................................................... 1-9

1.3.2 Integrated Security Engine (SEC).............................................................................. 1-12

1.3.3 Communications Processor Module (CPM).............................................................. 1-13

1.3.4 On-Chip Memory Unit............................................................................................... 1-14

1.3.4.1 On-Chip Memory as Memory-Mapped SRAM..................................................... 1-15

1.3.4.2 On-Chip Memory as L2 Cache.............................................................................. 1-15

1.3.5 e500 Coherency Module (ECM)................................................................................ 1-16

1.3.6 DDR SDRAM Controller .......................................................................................... 1-16

1.3.7 Programmable Interrupt Controller (PIC).................................................................. 1-17

1.3.8 I

2

C Controllers........................................................................................................... 1-17

1.3.9 Boot Sequencer.......................................................................................................... 1-17

1.3.10 Dual Universal Asynchronous Receiver/Transmitter (DUART)...............................1-17

1.3.11 Local Bus Controller (LBC)...................................................................................... 1-18

1.3.12 Three-Speed Ethernet Controllers (10/100/1Gb)....................................................... 1-18

1.3.13 Integrated DMA......................................................................................................... 1-19

1.3.14 PCI Controller............................................................................................................1-19

1.3.15 Power Management ................................................................................................... 1-19

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Number

1.3.16 Clocking..................................................................................................................... 1-20

1.3.17 Address Map.............................................................................................................. 1-20

1.3.18 OCeaN Switch Fabric................................................................................................ 1-20

1.4 Data Processing Overview............................................................................................. 1-20

1.4.1 Processing Between the CPM and Local Bus............................................................ 1-21

1.4.2 Processing Across the On-Chip Fabric...................................................................... 1-22

1.4.3 Data Processing with the e500 Coherency Module...................................................1-23

1.5 Compatibility Issues ...................................................................................................... 1-23

1.5.1 Software.....................................................................................................................1-23

1.5.2 MPC8555E Hardware................................................................................................ 1-23

1.5.3 Communications Protocol Table................................................................................ 1-24

1.5.4 MPC8555E Configurations........................................................................................ 1-24

1.5.5 Pin Configurations..................................................................................................... 1-24

1.5.6 Communications Performance................................................................................... 1-24

1.6 Reference Manual Revision History.............................................................................. 1-25

Chapter 2

Memory Map

2.1 Local Memory Map Overview and Example .................................................................. 2-1

2.2 Address Translation and Mapping................................................................................... 2-3

2.2.1 SRAM Windows.......................................................................................................... 2-4

2.2.2 Window into Configuration Space............................................................................... 2-4

2.2.3 Local Access Windows................................................................................................ 2-4

2.2.3.1 Local Access Register Memory Map ...................................................................... 2-5

2.2.3.2 Local Access Window n Base Address Registers (LAWBAR0–LAWBAR7)........ 2-5

2.2.3.3 Local Access Window n Attributes Registers (LAWAR0–LAWAR7).................... 2-6

2.2.3.4 Precedence of Local Access Windows.................................................................... 2-7

2.2.3.5 Configuring Local Access Windows....................................................................... 2-7

2.2.3.6 Distinguishing Local Access Windows from Other Mapping Functions................ 2-7

2.2.3.7 Illegal Interaction Between Local Access Windows and DDR SDRAM

Chip Selects......................................................................................................... 2-7

2.2.4 Outbound Address Translation and Mapping Windows.............................................. 2-8

2.2.5 Inbound Address Translation and Mapping Windows ................................................ 2-8

2.2.5.1 PCI Inbound ATMU ................................................................................................2-8

2.2.5.2 Illegal Interaction Between Inbound ATMUs and Local Access Windows ............ 2-8

2.3 Configuration, Control, and Status Register Map............................................................ 2-8

2.3.1 Accessing CCSR Memory from the e500 Core........................................................... 2-9

2.3.2 Accessing CCSR Memory from External Masters.................................................... 2-10

2.3.3 Organization of CCSR Memory ................................................................................ 2-10

2.3.4 General Utilities Registers......................................................................................... 2-11

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Contents

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2.3.5 Interrupt Controller and CCSR.................................................................................. 2-12

2.3.6 Communications Processor Module and CCSR........................................................2-13

2.3.7 Device-Specific Utilities............................................................................................ 2-13

2.4 Complete CCSR Map .................................................................................................... 2-14

Chapter 3

Signal Descriptions

3.1 Signals Overview.............................................................................................................3-1

3.2 Configuration Signals Sampled at Reset ....................................................................... 3-13

3.3 Output Signal States During Reset ................................................................................ 3-15

Chapter 4

Reset, Clocking, and Initialization

4.1 Overview.......................................................................................................................... 4-1

4.2 External Signal Description............................................................................................. 4-1

4.2.1 System Control Signals................................................................................................ 4-1

4.2.2 Clock Signals............................................................................................................... 4-2

4.3 Memory Map/Register Definition ................................................................................... 4-3

4.3.1 Local Configuration Control........................................................................................ 4-3

4.3.1.1 Accessing Configuration, Control, and Status Registers......................................... 4-4

4.3.1.1.1 Updating CCSRBAR........................................................................................... 4-4

4.3.1.1.2 Configuration, Control, and Status Base Address Register

(CCSRBAR).................................................................................................... 4-5

4.3.1.2 Accessing Alternate Configuration Space............................................................... 4-5

4.3.1.2.1 Alternate Configuration Base Address Register (ALTCBAR)............................ 4-6

4.3.1.2.2 Alternate Configuration Attribute Register (ALTCAR)...................................... 4-6

4.3.1.3 Boot Page Translation.............................................................................................. 4-7

4.3.1.3.1 Boot Page Translation Register (BPTR).............................................................. 4-7

4.3.2 Boot Sequencer............................................................................................................4-8

4.4 Functional Description..................................................................................................... 4-8

4.4.1 Reset Operations.......................................................................................................... 4-8

4.4.1.1 Soft Reset................................................................................................................. 4-8

4.4.1.2 Hard Reset ...............................................................................................................4-8

4.4.2 Power-On Reset Sequence........................................................................................... 4-9

4.4.3 Power-On Reset Configuration.................................................................................. 4-11

4.4.3.1 System PLL Ratio.................................................................................................. 4-11

4.4.3.2 e500 Core PLL Ratio............................................................................................. 4-12

4.4.3.3 Boot ROM Location.............................................................................................. 4-12

4.4.3.4 Host/Agent Configuration .....................................................................................4-13

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4.4.3.5 CPU Boot Configuration ....................................................................................... 4-14

4.4.3.6 Boot Sequencer Configuration .............................................................................. 4-14

4.4.3.7 TSEC Width........................................................................................................... 4-15

4.4.3.8 TSEC1 Protocol..................................................................................................... 4-15

4.4.3.9 TSEC2 Protocol..................................................................................................... 4-16

4.4.3.10 PCI Clock Selection............................................................................................... 4-16

4.4.3.11 PCI Width Configuration....................................................................................... 4-17

4.4.3.12 PCI I/O Impedance................................................................................................ 4-17

4.4.3.13 PCI Arbiter Configuration..................................................................................... 4-18

4.4.3.14 PCI Debug Configuration...................................................................................... 4-18

4.4.3.15 Memory Debug Configuration .............................................................................. 4-19

4.4.3.16 DDR Debug Configuration.................................................................................... 4-19

4.4.3.17 PCI Output Hold Configuration............................................................................. 4-19

4.4.3.18 Local Bus Output Hold Configuration .................................................................. 4-20

4.4.3.19 General-Purpose POR Configuration.................................................................... 4-20

4.4.4 Clocking..................................................................................................................... 4-21

4.4.4.1 System Clock and PCI Clocks............................................................................... 4-21

4.4.4.2 Ethernet Clocks...................................................................................................... 4-22

4.4.4.3 Real Time Clock.................................................................................................... 4-22

Part II

e500 Core Complex and L2 Cache

Chapter 5

Core Complex Overview

5.1 Overview.......................................................................................................................... 5-1

5.1.1 Upward Compatibility ................................................................................................. 5-3

5.1.2 Core Complex Summary ............................................................................................. 5-3

5.2 e500 Processor and System Version Numbers................................................................. 5-4

5.3 Features............................................................................................................................ 5-5

5.4 Instruction Set................................................................................................................ 5-10

5.5 Instruction Flow.............................................................................................................5-12

5.5.1 Initial Instruction Fetch.............................................................................................. 5-12

5.5.2 Branch Detection and Prediction............................................................................... 5-12

5.5.3 e500 Execution Pipeline ............................................................................................ 5-13

5.6 Programming Model...................................................................................................... 5-15

5.7 On-Chip Cache Implementation.................................................................................... 5-17

5.8 Interrupts and Exception Handling................................................................................ 5-17

5.8.1 Exception Handling ................................................................................................... 5-17

5.8.2 Interrupt Classes ........................................................................................................ 5-18

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Freescale Semiconductor xi

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5.8.3 Interrupt Types........................................................................................................... 5-18

5.8.4 Upper Bound on Interrupt Latencies ......................................................................... 5-19

5.8.5 Interrupt Registers...................................................................................................... 5-19

5.9 Memory Management.................................................................................................... 5-21

5.9.1 Address Translation................................................................................................... 5-22

5.9.2 MMU Assist Registers (MAS0–MAS4 and MAS6) ................................................. 5-23

5.9.3 Process ID Registers (PID0–PID2)............................................................................ 5-24

5.9.4 TLB Coherency.......................................................................................................... 5-24

5.10 Memory Coherency ....................................................................................................... 5-24

5.10.1 Atomic Update Memory References ......................................................................... 5-24

5.10.2 Memory Access Ordering.......................................................................................... 5-25

5.10.3 Cache Control Instructions ........................................................................................ 5-25

5.10.4 Programmable Page Characteristics .......................................................................... 5-25

5.11 Core Complex Bus (CCB)............................................................................................. 5-25

5.12 Performance Monitoring................................................................................................ 5-26

5.12.1 Global Control Register............................................................................................. 5-26

5.12.2 Performance Monitor Counter Registers................................................................... 5-26

5.12.3 Local Control Registers............................................................................................. 5-26

5.13 Legacy Support of Power Architecture Technology...................................................... 5-27

5.13.1 Instruction Set Compatibility..................................................................................... 5-27

5.13.1.1 User Instruction Set ...............................................................................................5-27

5.13.1.2 Supervisor Instruction Set...................................................................................... 5-27

5.13.2 Memory Subsystem ................................................................................................... 5-28

5.13.3 Exception Handling ...................................................................................................5-28

5.13.4 Memory Management................................................................................................ 5-28

5.13.5 Reset........................................................................................................................... 5-28

5.13.6 Little-Endian Mode.................................................................................................... 5-29

5.14 PowerQUICC III Implementation Details..................................................................... 5-29

Chapter 6

Core Register Summary

6.1 Overview.......................................................................................................................... 6-1

6.1.1 Register Set..................................................................................................................6-1

6.2 Register Model for 32-Bit Implementations.................................................................... 6-3

6.2.1 Special-Purpose Registers (SPRs)............................................................................... 6-4

6.3 Registers for Computational Operations.......................................................................... 6-8

6.3.1 General-Purpose Registers (GPRs).............................................................................. 6-8

6.3.2 Integer Exception Register (XER)............................................................................... 6-8

6.4 Registers for Branch Operations...................................................................................... 6-9

6.4.1 Condition Register (CR)..............................................................................................6-9

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6.4.2 Link Register (LR)..................................................................................................... 6-11

6.4.3 Count Register (CTR)................................................................................................ 6-11

6.5 Processor Control Registers........................................................................................... 6-11

6.5.1 Machine State Register (MSR).................................................................................. 6-11

6.5.2 Processor ID Register (PIR) ...................................................................................... 6-13

6.5.3 Processor Version Register (PVR)............................................................................. 6-13

6.5.4 System Version Register (SVR)................................................................................. 6-14

6.6 Timer Registers..............................................................................................................6-14

6.6.1 Timer Control Register (TCR)................................................................................... 6-14

6.6.2 Timer Status Register (TSR)...................................................................................... 6-15

6.6.3 Time Base Registers ..................................................................................................6-16

6.6.4 Decrementer Register ................................................................................................6-16

6.6.5 Decrementer Auto-Reload Register (DECAR).......................................................... 6-17

6.7 Interrupt Registers..........................................................................................................6-17

6.7.1 Interrupt Registers Defined by the Embedded and Base Categories......................... 6-17

6.7.1.1 Save/Restore Register 0 (SRR0)............................................................................ 6-17

6.7.1.2 Save/Restore Register 1 (SRR1)............................................................................ 6-17

6.7.1.3 Critical Save/Restore Register 0 (CSRR0)............................................................ 6-17

6.7.1.4 Critical Save/Restore Register 1 (CSRR1)............................................................ 6-18

6.7.1.5 Data Exception Address Register (DEAR)............................................................ 6-18

6.7.1.6 Interrupt Vector Prefix Register (IVPR)................................................................ 6-18

6.7.1.7 Interrupt Vector Offset Registers (IVORn)............................................................ 6-18

6.7.1.8 Exception Syndrome Register (ESR) .................................................................... 6-19

6.7.2 Additional Interrupt Registers ................................................................................... 6-20

6.7.2.1 Machine Check Save/Restore Register 0 (MCSRR0)........................................... 6-20

6.7.2.2 Machine Check Save/Restore Register 1 (MCSRR1)........................................... 6-20

6.7.2.3 Machine Check Address Register (MCAR).......................................................... 6-21

6.7.2.4 Machine Check Syndrome Register (MCSR)........................................................ 6-21

6.8 Software-Use SPRs (SPRG0–SPRG7 and USPRG0) ................................................... 6-22

6.9 Branch Target Buffer (BTB) Registers.......................................................................... 6-23

6.9.1 Branch Buffer Entry Address Register (BBEAR).....................................................6-23

6.9.2 Branch Buffer Target Address Register (BBTAR) .................................................... 6-23

6.9.3 Branch Unit Control and Status Register (BUCSR).................................................. 6-24

6.10 Hardware Implementation-Dependent Registers........................................................... 6-25

6.10.1 Hardware Implementation-Dependent Register 0 (HID0)......................................... 6-25

6.10.2 Hardware Implementation-Dependent Register 1 (HID1)......................................... 6-26

6.11 L1 Cache Configuration Registers................................................................................. 6-28

6.11.1 L1 Cache Control and Status Register 0 (L1CSR0).................................................. 6-28

6.11.2 L1 Cache Control and Status Register 1 (L1CSR1).................................................. 6-29

6.11.3 L1 Cache Configuration Register 0 (L1CFG0) ......................................................... 6-30

6.11.4 L1 Cache Configuration Register 1 (L1CFG1) ......................................................... 6-31

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Freescale Semiconductor xiii

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6.12 MMU Registers.............................................................................................................. 6-32

6.12.1 Process ID Registers (PID0–PID2)............................................................................ 6-32

6.12.2 MMU Control and Status Register 0 (MMUCSR0)..................................................6-32

6.12.3 MMU Configuration Register (MMUCFG).............................................................. 6-32

6.12.4 TLB Configuration Registers (TLBnCFG)................................................................ 6-33

6.12.4.1 TLB0 Configuration Register 0 (TLB0CFG)........................................................ 6-33

6.12.4.2 TLB1 Configuration Register 1 (TLB1CFG)........................................................ 6-34

6.12.5 MMU Assist Registers............................................................................................... 6-34

6.12.5.1 MAS Register 0 (MAS0)....................................................................................... 6-34

6.12.5.2 MAS Register 1 (MAS1)....................................................................................... 6-35

6.12.5.3 MAS Register 2 (MAS2)....................................................................................... 6-36

6.12.5.4 MAS Register 3 (MAS3)....................................................................................... 6-37

6.12.5.5 MAS Register 4 (MAS4)....................................................................................... 6-37

6.12.5.6 MAS Register 6 (MAS6)....................................................................................... 6-38

6.13 Debug Registers.............................................................................................................6-39

6.13.1 Debug Control Registers (DBCR0–DBCR2)............................................................ 6-39

6.13.1.1 Debug Control Register 0 (DBCR0)...................................................................... 6-39

6.13.1.2 Debug Control Register 1 (DBCR1)...................................................................... 6-40

6.13.1.3 Debug Control Register 2 (DBCR2)...................................................................... 6-41

6.13.2 Debug Status Register (DBSR).................................................................................. 6-42

6.13.3 Instruction Address Compare Registers (IAC1–IAC2)............................................. 6-44

6.13.4 Data Address Compare Registers (DAC1–DAC2).................................................... 6-44

6.14 Signal Processing and Embedded Floating-Point Status and Control Register

(SPEFSCR)................................................................................................................ 6-44

6.14.1 Accumulator (ACC)................................................................................................... 6-46

6.15 Performance Monitor Registers (PMRs) ....................................................................... 6-47

6.15.1 Global Control Register 0 (PMGC0, UPMGC0)....................................................... 6-48

6.15.2 Local Control A Registers (PMLCa0–PMLCa3, UPMLCa0–UPMLCa3) ............... 6-48

6.15.3 Local Control B Registers (PMLCb0–PMLCb3, UPMLCb0–UPMLCb3) .............. 6-49

6.15.4 Performance Monitor Counter Registers (PMC0–PMC3, UPMC0–UPMC3)..........6-50

Chapter 7

L2 Look-Aside Cache/SRAM

7.1 L2 Cache Overview ......................................................................................................... 7-1

7.1.1 L2 Cache and SRAM Features .................................................................................... 7-2

7.2 Cache Organization.......................................................................................................... 7-3

7.3 Memory Map/Register Definition ................................................................................... 7-6

7.3.1 L2/SRAM Register Descriptions.................................................................................7-7

7.3.1.1 L2 Control Register (L2CTL).................................................................................. 7-7

7.3.1.2 L2 Cache External Write Address Registers 0–3 (L2CEWARn) .......................... 7-10

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7.3.1.3 L2 Cache External Write Control Registers 0–3 (L2CEWCRn)........................... 7-10

7.3.1.4 L2 Memory-Mapped SRAM Base Address Registers 0–1 (L2SRBARn) ............ 7-11

7.3.1.5 L2 Error Registers.................................................................................................. 7-12

7.3.1.5.1 Error Injection Registers.................................................................................... 7-12

7.3.1.5.2 Error Control and Capture Registers ................................................................. 7-14

7.4 External Writes to the L2 Cache (Cache Stashing)........................................................ 7-20

7.5 L2 Cache Timing ........................................................................................................... 7-21

7.6 L2 Cache and SRAM Coherency................................................................................... 7-22

7.6.1 L2 Cache Coherency Rules........................................................................................ 7-22

7.6.2 Memory-Mapped SRAM Coherency Rules .............................................................. 7-23

7.7 L2 Cache Locking.......................................................................................................... 7-23

7.7.1 Locking the Entire L2 Cache..................................................................................... 7-24

7.7.2 Locking Programmed Memory Ranges..................................................................... 7-24

7.7.3 Locking Selected Lines.............................................................................................. 7-24

7.7.4 Clearing Locks on Selected Lines ............................................................................. 7-25

7.7.5 Flash Clearing of Instruction and Data Locks........................................................... 7-25

7.7.6 Locks with Stale Data................................................................................................7-26

7.8 PLRU L2 Replacement Policy....................................................................................... 7-26

7.8.1 PLRU Bit Update Considerations.............................................................................. 7-27

7.8.2 Allocation of Lines .................................................................................................... 7-27

7.9 L2 Cache Operation....................................................................................................... 7-28

7.9.1 L2 Cache States ......................................................................................................... 7-28

7.9.2 Flash Invalidation of the L2 Cache............................................................................ 7-29

7.9.3 L2 State Transitions...................................................................................................7-29

7.10 Initialization/Application Information........................................................................... 7-33

7.10.1 Initialization............................................................................................................... 7-33

7.10.1.1 L2 Cache Initialization .......................................................................................... 7-33

7.10.1.2 Memory-Mapped SRAM Initialization ................................................................. 7-33

7.10.2 Managing Errors........................................................................................................ 7-33

7.10.2.1 ECC Errors............................................................................................................. 7-33

7.10.2.2 Tag Parity Errors.................................................................................................... 7-34

Part III

Memory, Security, and I/O Interfaces

Chapter 8

e500 Coherency Module

8.1 Introduction...................................................................................................................... 8-1

8.1.1 Overview...................................................................................................................... 8-1

8.1.2 Features........................................................................................................................ 8-2

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8.2 Memory Map/Register Definition ................................................................................... 8-2

8.2.1 Register Descriptions................................................................................................... 8-3

8.2.1.1 ECM CCB Address Configuration Register (EEBACR) ........................................ 8-3

8.2.1.2 ECM CCB Port Configuration Register (EEBPCR) ............................................... 8-4

8.2.1.3 ECM Error Detect Register (EEDR) ....................................................................... 8-4

8.2.1.4 ECM Error Enable Register (EEER)....................................................................... 8-5

8.2.1.5 ECM Error Attributes Capture Register (EEATR).................................................. 8-6

8.2.1.6 ECM Error Address Capture Register (EEADR)....................................................8-7

8.3 Functional Description..................................................................................................... 8-7

8.3.1 I/O Arbiter.................................................................................................................... 8-7

8.3.2 CCB Arbiter................................................................................................................. 8-8

8.3.3 Transaction Queue....................................................................................................... 8-8

8.3.4 Global Data Multiplexer.............................................................................................. 8-8

8.3.5 CCB Interface..............................................................................................................8-8

8.4 Initialization/Application Information............................................................................. 8-9

Chapter 9

DDR Memory Controller

9.1 Introduction...................................................................................................................... 9-1

9.2 Features............................................................................................................................ 9-2

9.2.1 Modes of Operation..................................................................................................... 9-3

9.3 External Signal Descriptions ........................................................................................... 9-3

9.3.1 Signals Overview......................................................................................................... 9-3

9.3.2 Detailed Signal Descriptions ....................................................................................... 9-4

9.3.2.1 Memory Interface Signals........................................................................................ 9-5

9.3.2.2 Clock Interface Signals............................................................................................ 9-8

9.3.2.3 Debug Signals.......................................................................................................... 9-8

9.4 Memory Map/Register Definition ................................................................................... 9-8

9.4.1 Register Descriptions................................................................................................... 9-9

9.4.1.1 Chip Select Memory Bounds (CSn_BNDS)............................................................ 9-9

9.4.1.2 Chip Select Configuration (CSn_CONFIG).......................................................... 9-10

9.4.1.3 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)................................. 9-11

9.4.1.4 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)................................. 9-12

9.4.1.5 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-13

9.4.1.6 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................ 9-14

9.4.1.7 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 9-15

9.4.1.8 DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL).............................9-16

9.4.1.9 Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI)........9-17

9.4.1.10 Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)........ 9-17

9.4.1.11 Memory Data Path Error Injection Mask ECC (ECC_ERR_INJECT)................. 9-18

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9.4.1.12 Memory Data Path Read Capture High (CAPTURE_DATA_HI)......................... 9-19

9.4.1.13 Memory Data Path Read Capture Low (CAPTURE_DATA_LO) ........................ 9-19

9.4.1.14 Memory Data Path Read Capture ECC (CAPTURE_ECC).................................. 9-20

9.4.1.15 Memory Error Detect (ERR_DETECT)................................................................ 9-20

9.4.1.16 Memory Error Disable (ERR_DISABLE)............................................................. 9-21

9.4.1.17 Memory Error Interrupt Enable (ERR_INT_EN).................................................. 9-22

9.4.1.18 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES).......................... 9-22

9.4.1.19 Memory Error Address Capture (CAPTURE_ADDRESS) ..................................9-23

9.4.1.20 Single-Bit ECC Memory Error Management (ERR_SBE)................................... 9-24

9.5 Functional Description................................................................................................... 9-24

9.5.1 DDR SDRAM Interface Operation............................................................................ 9-29

9.5.1.1 Supported DDR SDRAM Organizations............................................................... 9-29

9.5.2 DDR SDRAM Address Multiplexing........................................................................ 9-30

9.5.3 JEDEC Standard DDR SDRAM Interface Commands............................................. 9-31

9.5.4 SDRAM Interface Timing ......................................................................................... 9-33

9.5.4.1 Clock Distribution ................................................................................................. 9-36

9.5.5 DDR SDRAM Mode-Set Command Timing............................................................. 9-37

9.5.6 DDR SDRAM Registered DIMM Mode................................................................... 9-38

9.5.7 DDR SDRAM Source Synchronous Clock Control.................................................. 9-38

9.5.8 DDR SDRAM Write Timing Adjustments................................................................ 9-38

9.5.9 DDR SDRAM Refresh .............................................................................................. 9-39

9.5.9.1 DDR SDRAM Refresh Timing.............................................................................. 9-40

9.5.9.2 DDR SDRAM Refresh and Power-Saving Modes................................................ 9-41

9.5.9.2.1 Self-Refresh in Sleep Mode............................................................................... 9-42

9.5.10 DDR Data Beat Ordering........................................................................................... 9-42

9.5.11 Page Mode and Logical Bank Retention ................................................................... 9-43

9.5.12 Error Checking and Correcting (ECC) ...................................................................... 9-44

9.5.13 Error Management.....................................................................................................9-46

9.6 Initialization/Application Information........................................................................... 9-46

9.6.1 DDR SDRAM Initialization Sequence...................................................................... 9-47

Chapter 10

Programmable Interrupt Controller

10.1 Introduction.................................................................................................................... 10-1

10.1.1 Overview.................................................................................................................... 10-1

10.1.2 Features...................................................................................................................... 10-3

10.1.3 Interrupts to the Processor Core................................................................................. 10-3

10.1.4 Modes of Operation................................................................................................... 10-4

10.1.4.1 Mixed Mode (GCR[M] = 1).................................................................................. 10-4

10.1.4.2 Pass-Through Mode (GCR[M] = 0) ...................................................................... 10-5

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10.1.5 Interrupt Sources........................................................................................................ 10-5

10.1.5.1 Interrupt Routing—Mixed Mode........................................................................... 10-6

10.1.5.2 Internal Interrupt Sources...................................................................................... 10-6

10.2 External Signal Description........................................................................................... 10-6

10.2.1 Signal Overview ........................................................................................................ 10-7

10.2.2 Detailed Signal Descriptions .....................................................................................10-7

10.3 Memory Map/Register Definition ................................................................................. 10-8

10.3.1 Global Registers....................................................................................................... 10-14

10.3.1.1 Feature Reporting Register (FRR)....................................................................... 10-15

10.3.1.2 Global Configuration Register (GCR)................................................................. 10-15

10.3.1.3 Vendor Identification Register (VIR) .................................................................. 10-16

10.3.1.4 Processor Initialization Register (PIR)................................................................ 10-16

10.3.1.5 IPI Vector/Priority Registers (IPIVPRn) ............................................................. 10-17

10.3.1.6 Spurious Vector Register (SVR)..........................................................................10-18

10.3.2 Global Timer Registers............................................................................................ 10-18

10.3.2.1 Timer Frequency Reporting Register (TFRR)..................................................... 10-19

10.3.2.2 Global Timer Current Count Registers (GTCCRn) ............................................. 10-19

10.3.2.3 Global Timer Base Count Registers (GTBCRn).................................................. 10-20

10.3.2.4 Global Timer Vector/Priority Registers (GTVPRn)............................................. 10-20

10.3.2.5 Global Timer Destination Registers (GTDRn) .................................................... 10-21

10.3.2.6 Timer Control Register (TCR)............................................................................. 10-22

10.3.3 Summary Registers.................................................................................................. 10-24

10.3.3.1 IRQ_OUT Summary Register 0 (IRQSR0)......................................................... 10-24

10.3.3.2 IRQ_OUT Summary Register 1 (IRQSR1)......................................................... 10-25

10.3.3.3 Critical Interrupt Summary Register 0 (CISR0).................................................. 10-26

10.3.3.4 Critical Interrupt Summary Register 1 (CISR1).................................................. 10-26

10.3.4 Performance Monitor Mask Registers (PMMRs).................................................... 10-27

10.3.4.1 Performance Monitor Mask Register (Lower) (PMnMR0)................................. 10-27

10.3.4.2 Performance Monitor Mask Registers (Upper) (PMnMR1)................................ 10-28

10.3.5 Message Registers.................................................................................................... 10-28

10.3.5.1 Message Registers (MSGR0–MSGR3)............................................................... 10-28

10.3.5.2 Message Enable Register (MER)......................................................................... 10-29

10.3.5.3 Message Status Register (MSR).......................................................................... 10-29

10.3.6 Interrupt Source Configuration Registers................................................................ 10-30

10.3.6.1 External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ..................... 10-30

10.3.6.2 External Interrupt Destination Registers (EIDR0–EIDR11) ............................... 10-31

10.3.6.3 Internal Interrupt Vector/Priority Registers (IIVPR0–IIVPR31)......................... 10-32

10.3.6.4 Internal Interrupt Destination Registers (IIDR0–IIDR31) ..................................10-33

10.3.6.5 Messaging Interrupt Vector/Priority Registers (MIVPR0–MIVPR3) ................. 10-34

10.3.6.6 Messaging Interrupt Destination Registers (MIDR0–MIDR3)........................... 10-35

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10.3.7 Per-CPU Registers................................................................................................... 10-36

10.3.7.1 Interprocessor Interrupt Dispatch Register (IPIDR0–IPIDR3) ........................... 10-37

10.3.7.2 Processor Current Task Priority Register (CTPR)............................................... 10-38

10.3.7.3 Who Am I Register (WHOAMI)......................................................................... 10-39

10.3.7.4 Processor Interrupt Acknowledge Register (IACK)............................................ 10-39

10.3.7.5 Processor End of Interrupt Register (EOI) .......................................................... 10-40

10.4 Functional Description................................................................................................. 10-41

10.4.1 Flow of Interrupt Control......................................................................................... 10-41

10.4.1.1 Interrupt Source Priority...................................................................................... 10-42

10.4.1.2 Processor Current Task Priority........................................................................... 10-43

10.4.1.3 Interrupt Acknowledge........................................................................................ 10-43

10.4.2 Nesting of Interrupts................................................................................................ 10-43

10.4.3 Processor Initialization ............................................................................................ 10-44

10.4.4 Spurious Vector Generation..................................................................................... 10-44

10.4.5 Messaging Interrupts................................................................................................ 10-44

10.4.6 Global Timers .......................................................................................................... 10-44

10.4.7 Reset of the PIC....................................................................................................... 10-45

10.5 Initialization/Application Information......................................................................... 10-45

10.5.1 Programming Guidelines......................................................................................... 10-45

10.5.1.1 PIC Registers....................................................................................................... 10-45

10.5.1.2 Changing Interrupt Source Configuration........................................................... 10-47

Chapter 11

I

2

C Interface

11.1 Introduction.................................................................................................................... 11-1

11.1.1 Overview.................................................................................................................... 11-2

11.1.2 Features...................................................................................................................... 11-2

11.1.3 Modes of Operation................................................................................................... 11-2

11.2 External Signal Descriptions ......................................................................................... 11-3

11.2.1 Signal Overview ........................................................................................................ 11-3

11.2.2 Detailed Signal Descriptions ..................................................................................... 11-3

11.3 Memory Map/Register Definition ................................................................................. 11-4

11.3.1 Register Descriptions................................................................................................. 11-5

11.3.1.1 I

2

C Address Register (I2CADR)........................................................................... 11-5

11.3.1.2 I

2

C Frequency Divider Register (I2CFDR)........................................................... 11-6

11.3.1.3 I

2

C Control Register (I2CCR)............................................................................... 11-7

11.3.1.4 I

2

C Status Register (I2CSR).................................................................................. 11-9

11.3.1.5 I

2

C Data Register (I2CDR).................................................................................. 11-10

11.3.1.6 Digital Filter Sampling Rate Register (I2CDFSRR)............................................11-11

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11.4 Functional Description..................................................................................................11-11

11.4.1 Transaction Protocol.................................................................................................11-11

11.4.1.1 START Condition ................................................................................................ 11-12

11.4.1.2 Slave Address Transmission................................................................................ 11-12

11.4.1.3 Repeated START Condition ................................................................................ 11-13

11.4.1.4 STOP Condition................................................................................................... 11-13

11.4.1.5 Protocol Implementation Details......................................................................... 11-13

11.4.1.5.1 Transaction Monitoring—Implementation Details.......................................... 11-13

11.4.1.5.2 Control Transfer—Implementation Details..................................................... 11-14

11.4.1.6 Address Compare—Implementation Details....................................................... 11-15

11.4.2 Arbitration Procedure .............................................................................................. 11-15

11.4.2.1 Arbitration Control .............................................................................................. 11-15

11.4.3 Handshaking ............................................................................................................ 11-16

11.4.4 Clock Control........................................................................................................... 11-16

11.4.4.1 Clock Synchronization......................................................................................... 11-16

11.4.4.2 Input Synchronization and Digital Filter............................................................. 11-16

11.4.4.2.1 Input Signal Synchronization .......................................................................... 11-16

11.4.4.2.2 Filtering of SCL and SDA Lines..................................................................... 11-17

11.4.4.3 Clock Stretching .................................................................................................. 11-17

11.4.5 Boot Sequencer Mode.............................................................................................. 11-17

11.4.5.1 EEPROM Calling Address.................................................................................. 11-18

11.4.5.2 EEPROM Data Format........................................................................................ 11-18

11.5 Initialization/Application Information......................................................................... 11-20

11.5.1 Initialization Sequence............................................................................................. 11-20

11.5.2 Generation of START .............................................................................................. 11-21

11.5.3 Post-Transfer Software Response............................................................................ 11-21

11.5.4 Generation of STOP................................................................................................. 11-22

11.5.5 Generation of Repeated START .............................................................................. 11-22

11.5.6 Generation of SCL When SDA Low....................................................................... 11-22

11.5.7 Slave Mode Interrupt Service Routine..................................................................... 11-22

11.5.7.1 Slave Transmitter and Received Acknowledge................................................... 11-23

11.5.7.2 Loss of Arbitration and Forcing of Slave Mode.................................................. 11-23

11.5.8 Interrupt Service Routine Flowchart........................................................................ 11-23

Chapter 12

DUART

12.1 Overview........................................................................................................................ 12-1

12.1.1 Features...................................................................................................................... 12-1

12.1.2 Modes of Operation................................................................................................... 12-2

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12.2 External Signal Descriptions ......................................................................................... 12-3

12.2.1 Signal Overview ........................................................................................................ 12-3

12.2.2 Detailed Signal Descriptions .....................................................................................12-3

12.3 Memory Map/Register Definition ................................................................................. 12-4

12.3.1 Register Descriptions................................................................................................. 12-6

12.3.1.1 Receiver Buffer Registers (URBR0, URBR1) (ULCR[DLAB] = 0).................... 12-6

12.3.1.2 Transmitter Holding Registers (UTHR0, UTHR1) (ULCR[DLAB] = 0)............. 12-6

12.3.1.3 Divisor Most and Least Significant Byte Registers (UDMB and UDLB)

(ULCR[DLAB] = 1).......................................................................................... 12-7

12.3.1.4 Interrupt Enable Register (UIER) (ULCR[DLAB] = 0)........................................ 12-9

12.3.1.5 Interrupt ID Registers (UIIR0, UIIR1) (ULCR[DLAB] = 0)................................ 12-9

12.3.1.6 FIFO Control Registers (UFCR0, UFCR1) (ULCR[DLAB] = 0)....................... 12-11

12.3.1.7 Line Control Registers (ULCR0, ULCR1).......................................................... 12-12

12.3.1.8 Modem Control Registers (UMCR0, UMCR1)................................................... 12-14

12.3.1.9 Line Status Registers (ULSR0, ULSR1)............................................................. 12-14

12.3.1.10 Modem Status Registers (UMSR0, UMSR1)...................................................... 12-16

12.3.1.11 Scratch Registers (USCR0, USCR1)................................................................... 12-17

12.3.1.12 Alternate Function Registers (UAFR0, UAFR1) (ULCR[DLAB] = 1).............. 12-17

12.3.1.13 DMA Status Registers (UDSR0, UDSR1) .......................................................... 12-18

12.4 Functional Description................................................................................................. 12-19

12.4.1 Serial Interface......................................................................................................... 12-20

12.4.1.1 START Bit ........................................................................................................... 12-20

12.4.1.2 Data Transfer ....................................................................................................... 12-21

12.4.1.3 Parity Bit.............................................................................................................. 12-21

12.4.1.4 STOP Bit.............................................................................................................. 12-21

12.4.2 Baud-Rate Generator Logic..................................................................................... 12-21

12.4.3 Local Loopback Mode............................................................................................. 12-22

12.4.4 Errors .......................................................................................................................12-22

12.4.4.1 Framing Error ...................................................................................................... 12-22

12.4.4.2 Parity Error .......................................................................................................... 12-22

12.4.4.3 Overrun Error....................................................................................................... 12-22

12.4.5 FIFO Mode ..............................................................................................................12-22

12.4.5.1 FIFO Interrupts....................................................................................................12-23

12.4.5.2 DMA Mode Select............................................................................................... 12-23

12.4.5.3 Interrupt Control Logic........................................................................................ 12-23

12.5 DUART Initialization/Application Information .......................................................... 12-24

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