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NXP MPC8535E, MPC8536E Reference guide

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Updates to MPC8536E Reference Manual, Rev. 1, as of 08/07/2015
Freescale Semiconductor
Updates to MPC8536E Reference Manual, Rev. 1, as of 08/07/2015
This section provides updates to the MPC8536E Reference Manual, Rev. 1. We are providing known
corrections, but do not guarantee that the list is exhaustive. For convenience, the section number and page
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Section, Page No. Changes
14.5.2, 14-16 In Table 14-4, “Module Memory Map,” updated the reset values for both
eTSEC_ID1 (was 0x0124_0000, now 0x0124_0106) and eTSEC_ID2 (was
0x0030_00F0, now 0x00F8_00F0).
MPC8536E PowerQUICC III™
Integrated Processor
Reference Manual
Supports
MPC8536E
MPC8535E
MPC8536ERM
Rev. 1
05/2009
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MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Freescale Semiconductor iii
Contents
Paragraph
Number Title
Page
Number
Co nt ents
About This Book
Audience...........................................................................................................................cix
Organizations....................................................................................................................cix
Suggested Reading...........................................................................................................cxii
General Information.....................................................................................................cxii
Related Documentation................................................................................................cxii
Conventions ................................................................................................................... cxiii
Signal Conventions.........................................................................................................cxiv
Register Access Conventions..........................................................................................cxiv
Acronyms and Abbreviations .........................................................................................cxiv
Part I
Overview
Chapter 1
Overview
1.1 Introduction...................................................................................................................... 1-1
1.2 MPC8536E Overview......................................................................................................1-2
1.2.1 Key Features ................................................................................................................1-2
1.3 MPC8536E Architecture Overview................................................................................. 1-3
1.3.1 e500 Core and Memory Unit .......................................................................................1-3
1.3.2 e500 Coherency Module (ECM) and Address Map .................................................... 1-3
1.3.3 Integrated Security Engine (SEC)................................................................................ 1-4
1.3.4 High-Speed Interface Blocks (SerDes)........................................................................ 1-4
1.3.4.1 Eight-Lane SerDes................................................................................................... 1-5
1.3.4.2 Two-Lane SerDes .................................................................................................... 1-5
1.3.5 Enhanced Three-Speed Ethernet Controllers (eTSEC) ............................................... 1-5
1.3.6 Universal Serial Bus (USB) Dual-Role Controllers .................................................... 1-6
1.3.6.1 Host Mode Operation .............................................................................................. 1-6
1.3.6.2 Device Mode Operation........................................................................................... 1-6
1.3.7 DDR SDRAM Controller ............................................................................................ 1-7
1.3.8 Power Management Controller.................................................................................... 1-7
1.3.9 PCI Express Controller................................................................................................ 1-8
1.3.10 Programmable Interrupt Controller (PIC).................................................................... 1-8
1.3.11 Enhanced Secure Digital Host Controller (eSDHC).................................................... 1-8
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Number
1.3.12 eSPI Interface............................................................................................................... 1-8
1.3.13 Serial ATA (SATA) Controllers ................................................................................... 1-9
1.3.14 DMA Controller, I
2
C, DUART, eLBC ........................................................................ 1-9
1.4 MPC8536E Application Examples................................................................................ 1-11
1.4.1 Multi-Function Printer............................................................................................... 1-11
1.4.2 Network Attached Storage......................................................................................... 1-12
1.4.3 Gaming Kiosk............................................................................................................ 1-13
1.4.4 Network Controller.................................................................................................... 1-14
Chapter 2
Memory Map
2.1 Local Memory Map Overview and Example .................................................................. 2-1
2.2 Address Translation and Mapping................................................................................... 2-3
2.2.1 SRAM Windows.......................................................................................................... 2-4
2.2.2 Window into Configuration Space...............................................................................2-4
2.2.3 Local Access Windows................................................................................................ 2-4
2.2.3.1 Local Access Register Memory Map ...................................................................... 2-5
2.2.3.2 Local Access IP Block Revision Register 1 (LAIPBRR1)......................................2-6
2.2.3.3 Local Access IP Block Revision Register 2 (LAIPBRR2)......................................2-6
2.2.3.4 Local Access Window n Base Address Registers (LAWBAR0–LAWBAR9)........2-7
2.2.3.5 Local Access Window n Attributes Registers (LAWAR0–LAWAR9).................... 2-7
2.2.3.6 Precedence of Local Access Windows.................................................................... 2-8
2.2.3.7 Configuring Local Access Windows.......................................................................2-8
2.2.3.8 Distinguishing Local Access Windows from Other Mapping Functions................ 2-9
2.2.3.9 Illegal Interaction Between Local Access Windows and DDR
SDRAM Chip Selects.......................................................................................... 2-9
2.2.4 Outbound Address Translation and Mapping Windows.............................................. 2-9
2.2.5 Inbound Address Translation and Mapping Windows .............................................. 2-10
2.2.5.1 PCI Inbound ATMU ..............................................................................................2-10
2.2.5.2 PCI Express Inbound ATMU.................................................................................2-10
2.2.5.3 Illegal Interaction Between Inbound ATMUs and Local Access Windows.......... 2-10
2.3 Configuration, Control, and Status Register Map.......................................................... 2-10
2.3.1 Accessing CCSR Memory from the Local Processor................................................ 2-11
2.3.2 Accessing CCSR Memory from External Masters.................................................... 2-11
2.3.3 Organization of CCSR Memory ................................................................................ 2-11
2.3.4 General Utilities Registers.........................................................................................2-12
2.3.5 Interrupt Controller and CCSR.................................................................................. 2-13
2.3.6 Device-Specific Utilities............................................................................................2-13
2.4 Complete CCSR Map .................................................................................................... 2-14
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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Chapter 3
Signal Descriptions
3.1 Signals Overview.............................................................................................................3-1
3.2 Configuration Signals Sampled at Reset ....................................................................... 3-15
3.3 Output Signal States During Reset ................................................................................ 3-17
Chapter 4
Reset, Clocking, and Initialization
4.1 Overview..........................................................................................................................4-1
4.2 External Signal Descriptions ........................................................................................... 4-1
4.2.1 System Control Signals................................................................................................ 4-2
4.2.2 Clock Signals............................................................................................................... 4-3
4.3 Memory Map/Register Definition ................................................................................... 4-3
4.3.1 Local Configuration Control........................................................................................ 4-4
4.3.1.1 Accessing Configuration, Control, and Status Registers.........................................4-4
4.3.1.1.1 Updating CCSRBAR........................................................................................... 4-4
4.3.1.1.2 Configuration, Control, and Status Registers Base Address
Register (CCSRBAR)...................................................................................... 4-5
4.3.1.2 Accessing Alternate Configuration Space............................................................... 4-5
4.3.1.2.1 Alternate Configuration Base Address Register (ALTCBAR)............................4-6
4.3.1.2.2 Alternate Configuration Attribute Register (ALTCAR)...................................... 4-6
4.3.1.3 Boot Page Translation.............................................................................................. 4-7
4.3.1.3.1 Boot Page Translation Register (BPTR).............................................................. 4-7
4.3.2 Boot Sequencer............................................................................................................ 4-8
4.4 Functional Description..................................................................................................... 4-8
4.4.1 Reset Operations.......................................................................................................... 4-8
4.4.1.1 Soft Reset.................................................................................................................4-8
4.4.1.2 Hard Reset ...............................................................................................................4-8
4.4.2 Power-On Reset Sequence........................................................................................... 4-9
4.4.3 Power-On Reset Configuration.................................................................................. 4-11
4.4.3.1 System PLL Ratio.................................................................................................. 4-11
4.4.3.2 e500 Core PLL Ratio.............................................................................................4-12
4.4.3.3 DDR PLL Ratio Configuration.............................................................................. 4-13
4.4.3.4 System Speed Configuration ................................................................................. 4-13
4.4.3.5 Core Speed Configuration ..................................................................................... 4-14
4.4.3.6 Boot ROM Location .............................................................................................. 4-14
4.4.3.7 Host/Agent Configuration ..................................................................................... 4-15
4.4.3.8 SerDes1 I/O Port Selection.................................................................................... 4-16
4.4.3.9 SerDes2 I/O Port Selection.................................................................................... 4-17
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4.4.3.10 CPU Boot Configuration ....................................................................................... 4-17
4.4.3.11 Boot Sequencer Configuration .............................................................................. 4-18
4.4.3.12 DDR SDRAM Type............................................................................................... 4-19
4.4.3.13 Serdes 2 Reference Clock Configuration .............................................................. 4-19
4.4.3.14 eTSEC1 width........................................................................................................ 4-20
4.4.3.15 eTSEC3 Width....................................................................................................... 4-20
4.4.3.16 eTSEC1 Protocol ................................................................................................... 4-21
4.4.3.17 eTSEC3 Protocol ................................................................................................... 4-21
4.4.3.18 PCI Clock Selection............................................................................................... 4-22
4.4.3.19 PCI Speed Configuration....................................................................................... 4-22
4.4.3.20 PCI I/O Impedance ................................................................................................ 4-22
4.4.3.21 PCI Arbiter Configuration ..................................................................................... 4-23
4.4.3.22 Memory Debug Configuration .............................................................................. 4-23
4.4.3.23 DDR Debug Configuration.................................................................................... 4-23
4.4.3.24 General-Purpose POR Configuration .................................................................... 4-24
4.4.3.25 Engineering Use POR Configuration .................................................................... 4-24
4.4.4 Clocking.....................................................................................................................4-24
4.4.4.1 System Clock/PCI Clock/DDR Clock................................................................... 4-24
4.4.4.2 PCI Express and SGMII Clocks............................................................................ 4-25
4.4.4.2.1 Minimum Frequency Requirements.................................................................. 4-26
4.4.4.3 Ethernet Clocks...................................................................................................... 4-26
4.4.4.4 Real Time Clock.................................................................................................... 4-26
4.5 Initialization/Applications Information ......................................................................... 4-27
4.5.1 System Boot............................................................................................................... 4-27
4.5.1.1 eSDHC Boot.......................................................................................................... 4-27
4.5.1.1.1 Overview ........................................................................................................... 4-27
4.5.1.1.2 Features.............................................................................................................. 4-28
4.5.1.1.3 SD/MMC Card Data Structure .......................................................................... 4-29
4.5.1.1.4 eSDHC Controller Initial Configuration ...........................................................4-33
4.5.1.1.5 eSDHC Controller Boot Sequence .................................................................... 4-33
4.5.1.1.6 eSDHC Boot Error Handling............................................................................. 4-34
4.5.1.2 eSPI Boot ROM..................................................................................................... 4-35
4.5.1.2.1 Overview ........................................................................................................... 4-35
4.5.1.2.2 Features.............................................................................................................. 4-36
4.5.1.2.3 EEPROM Data Structure................................................................................... 4-36
4.5.1.2.4 eSPI Controller Configuration........................................................................... 4-40
4.5.1.3 Default e500 Addressing During System Boot .....................................................4-41
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
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Part II
e500 Core Complex and L2 Cache
Chapter 5
e500 Core Integration Details
5.1 e500 Core Overview........................................................................................................ 5-1
5.2 e500 Core Integration and the Core Complex Bus (CCB) .............................................. 5-3
5.3 Summary of Core Integratation Details........................................................................... 5-4
5.3.1 Processor Version Register (PVR) and System Version Register (SVR) ....................5-6
Chapter 6
L2 Look-Aside Cache/SRAM
6.1 L2 Cache Overview ......................................................................................................... 6-1
6.1.1 L2 Cache and SRAM Features .................................................................................... 6-2
6.2 L2 Cache and SRAM Organization ................................................................................. 6-4
6.2.1 Accessing the On-Chip Array as an L2 Cache ............................................................ 6-5
6.2.2 Accessing the On-Chip Array as an SRAM ................................................................ 6-5
6.2.3 Connection of the On-Chip Memory to the System.................................................... 6-7
6.3 Memory Map/Register Definition ................................................................................... 6-8
6.3.1 L2/SRAM Register Descriptions............................................................................... 6-10
6.3.1.1 L2 Control Register (L2CTL)................................................................................ 6-10
6.3.1.2 L2 Cache External Write Registers ....................................................................... 6-13
6.3.1.2.1 L2 Cache External Write Address Registers 0–3 (L2CEWARn)......................6-13
6.3.1.2.2 L2 Cache External Write Address Registers Extended Address 0–3
(L2CEWAREAn)........................................................................................... 6-14
6.3.1.2.3 L2 Cache External Write Control Registers 0–3 (L2CEWCRn)....................... 6-14
6.3.1.3 L2 Memory-Mapped SRAM Registers ................................................................. 6-15
6.3.1.3.1 L2 Memory-Mapped SRAM Base Address Registers 0–1 (L2SRBARn) ........ 6-16
6.3.1.3.2 L2 Memory-Mapped SRAM Base Address Registers Extended Address 0–1
(L2SRBAREAn)............................................................................................ 6-17
6.3.1.4 L2 Error Registers.................................................................................................. 6-17
6.3.1.4.1 Error Injection Registers.................................................................................... 6-18
6.3.1.4.2 Error Control and Capture Registers ................................................................. 6-20
6.4 External Writes to the L2 Cache (Cache Stashing)........................................................ 6-25
6.4.1 Stash-Only Cache Regions ........................................................................................ 6-26
6.5 L2 Cache Timing ........................................................................................................... 6-27
6.6 L2 Cache and SRAM Coherency................................................................................... 6-27
6.6.1 L2 Cache Coherency Rules........................................................................................ 6-28
6.6.2 Memory-Mapped SRAM Coherency Rules .............................................................. 6-29
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6.7 L2 Cache Locking.......................................................................................................... 6-29
6.7.1 Locking the Entire L2 Cache..................................................................................... 6-29
6.7.2 Locking Programmed Memory Ranges..................................................................... 6-30
6.7.3 Locking Selected Lines.............................................................................................. 6-30
6.7.4 Clearing Locks on Selected Lines ............................................................................. 6-30
6.7.5 Flash Clearing of Instruction and Data Locks ...........................................................6-31
6.7.6 Locks with Stale Data................................................................................................ 6-31
6.8 PLRU L2 Replacement Policy....................................................................................... 6-31
6.8.1 PLRU Bit Update Considerations.............................................................................. 6-32
6.8.2 Allocation of Lines .................................................................................................... 6-32
6.9 L2 Cache Operation....................................................................................................... 6-33
6.9.1 Initialization............................................................................................................... 6-33
6.9.1.1 L2 Cache Initialization .......................................................................................... 6-33
6.9.1.2 Memory-Mapped SRAM Initialization ................................................................. 6-33
6.9.2 Flash Invalidation of the L2 Cache............................................................................ 6-34
6.9.3 Managing Errors ........................................................................................................ 6-34
6.9.3.1 ECC Errors............................................................................................................. 6-34
6.9.3.2 Tag Parity Errors.................................................................................................... 6-34
6.9.4 L2 Cache States ......................................................................................................... 6-34
6.9.5 L2 State Transitions ................................................................................................... 6-35
6.9.6 Error Checking and Correcting (ECC) ...................................................................... 6-39
Part III
Memory, Security, and I/O Interfaces
Chapter 7
e500 Coherency Module
7.1 Introduction...................................................................................................................... 7-1
7.1.1 Overview...................................................................................................................... 7-2
7.1.2 Features........................................................................................................................7-2
7.2 Memory Map/Register Definition ................................................................................... 7-3
7.2.1 Register Descriptions................................................................................................... 7-3
7.2.1.1 ECM CCB Address Configuration Register (EEBACR) ........................................ 7-3
7.2.1.2 ECM CCB Port Configuration Register (EEBPCR) ...............................................7-4
7.2.1.3 ECM IP Block Revision Register 1 (EIPBRR1) .....................................................7-5
7.2.1.4 ECM IP Block Revision Register 2 (EIPBRR2) .....................................................7-5
7.2.1.5 ECM Error Detect Register (EEDR) ....................................................................... 7-6
7.2.1.6 ECM Error Enable Register (EEER)....................................................................... 7-7
7.2.1.7 ECM Error Attributes Capture Register (EEATR)..................................................7-7
7.2.1.8 ECM Error Low Address Capture Register (EELADR) .........................................7-8
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7.2.1.9 ECM Error High Address Capture Register (EEHADR) ........................................ 7-9
7.3 Functional Description..................................................................................................... 7-9
7.3.1 I/O Arbiter....................................................................................................................7-9
7.3.2 CCB Arbiter.................................................................................................................7-9
7.3.3 Transaction Queue ..................................................................................................... 7-10
7.3.4 Global Data Multiplexor............................................................................................ 7-10
7.3.5 CCB Interface ............................................................................................................ 7-10
7.4 Initialization/Application Information...........................................................................7-10
Chapter 8
DDR Memory Controller
8.1 Introduction...................................................................................................................... 8-1
8.2 Features............................................................................................................................ 8-2
8.2.1 Modes of Operation ..................................................................................................... 8-3
8.3 External Signal Descriptions ........................................................................................... 8-3
8.3.1 Signals Overview......................................................................................................... 8-3
8.3.2 Detailed Signal Descriptions ....................................................................................... 8-6
8.3.2.1 Memory Interface Signals........................................................................................ 8-6
8.3.2.2 Clock Interface Signals.......................................................................................... 8-10
8.3.2.3 Debug Signals........................................................................................................ 8-10
8.4 Memory Map/Register Definition ................................................................................. 8-10
8.4.1 Register Descriptions................................................................................................. 8-12
8.4.1.1 Chip Select Memory Bounds (CSn_BNDS)..........................................................8-12
8.4.1.2 Chip Select Configuration (CSn_CONFIG).......................................................... 8-13
8.4.1.3 Chip Select Configuration 2 (CSn_CONFIG_2)...................................................8-15
8.4.1.4 DDR SDRAM Timing Configuration 3 (TIMING_CFG_3).................................8-16
8.4.1.5 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0).................................8-17
8.4.1.6 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1).................................8-19
8.4.1.7 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2).................................8-21
8.4.1.8 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 8-23
8.4.1.9 DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)...................... 8-26
8.4.1.10 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................8-29
8.4.1.11 DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)..................... 8-29
8.4.1.12 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)................. 8-30
8.4.1.13 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 8-33
8.4.1.14 DDR SDRAM Data Initialization (DDR_DATA_INIT) .......................................8-33
8.4.1.15 DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL).............................8-34
8.4.1.16 DDR Initialization Address (DDR_INIT_ADDR)................................................ 8-34
8.4.1.17 DDR Initialization Enable Extended Address (DDR_INIT_EXT_ADDR)..........8-35
8.4.1.18 DDR SDRAM Timing Configuration 4 (TIMING_CFG_4).................................8-36
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8.4.1.19 DDR SDRAM Timing Configuration 5 (TIMING_CFG_5).................................8-37
8.4.1.20 DDR ZQ Calibration Control (DDR_ZQ_CNTL) ................................................8-39
8.4.1.21 DDR Write Leveling Control (DDR_WRLVL_CNTL)........................................ 8-40
8.4.1.22 DDR Self Refresh Counter (DDR_SR_CNTR) .................................................... 8-43
8.4.1.23 DDR SDRAM Register Control Word 1 (DDR_SDRAM_RCW_1).................... 8-44
8.4.1.24 DDR SDRAM Register Control Word 2 (DDR_SDRAM_RCW_2).................... 8-45
8.4.1.25 DDR Debug Status Register 1 (DDRDSR_1) .......................................................8-46
8.4.1.26 DDR Debug Status Register 2 (DDRDSR_2) .......................................................8-47
8.4.1.27 DDR Control Driver Register 1 (DDRCDR_1).....................................................8-47
8.4.1.28 DDR Control Driver Register 2 (DDRCDR_2).....................................................8-50
8.4.1.29 DDR IP Block Revision 1 (DDR_IP_REV1)........................................................8-50
8.4.1.30 DDR IP Block Revision 2 (DDR_IP_REV2)........................................................8-51
8.4.1.31 Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI)........ 8-51
8.4.1.32 Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)........ 8-52
8.4.1.33 Memory Data Path Error Injection Mask ECC (ERR_INJECT)...........................8-52
8.4.1.34 Memory Data Path Read Capture High (CAPTURE_DATA_HI)......................... 8-53
8.4.1.35 Memory Data Path Read Capture Low (CAPTURE_DATA_LO) ........................ 8-54
8.4.1.36 Memory Data Path Read Capture ECC (CAPTURE_ECC)..................................8-54
8.4.1.37 Memory Error Detect (ERR_DETECT)................................................................ 8-54
8.4.1.38 Memory Error Disable (ERR_DISABLE)............................................................. 8-56
8.4.1.39 Memory Error Interrupt Enable (ERR_INT_EN).................................................. 8-57
8.4.1.40 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES).......................... 8-58
8.4.1.41 Memory Error Address Capture (CAPTURE_ADDRESS) .................................. 8-58
8.4.1.42 Memory Error Extended Address Capture (CAPTURE_EXT_ADDRESS)......... 8-59
8.4.1.43 Single-Bit ECC Memory Error Management (ERR_SBE)...................................8-59
8.5 Functional Description................................................................................................... 8-60
8.5.1 DDR SDRAM Interface Operation............................................................................ 8-64
8.5.1.1 Supported DDR SDRAM Organizations............................................................... 8-64
8.5.2 DDR SDRAM Address Multiplexing........................................................................ 8-66
8.5.3 JEDEC Standard DDR SDRAM Interface Commands............................................. 8-71
8.5.4 DDR SDRAM Interface Timing................................................................................ 8-72
8.5.4.1 Clock Distribution ................................................................................................. 8-76
8.5.5 DDR SDRAM Mode-Set Command Timing............................................................. 8-76
8.5.6 DDR SDRAM Registered DIMM Mode................................................................... 8-77
8.5.7 DDR SDRAM Write Timing Adjustments................................................................ 8-78
8.5.8 DDR SDRAM Refresh .............................................................................................. 8-79
8.5.8.1 DDR SDRAM Refresh Timing.............................................................................. 8-80
8.5.8.2 DDR SDRAM Refresh and Power-Saving Modes................................................8-80
8.5.8.2.1 Self-Refresh in Sleep Mode............................................................................... 8-82
8.5.9 DDR Data Beat Ordering........................................................................................... 8-83
8.5.10 Page Mode and Logical Bank Retention ................................................................... 8-83
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8.5.11 Error Checking and Correcting (ECC) ...................................................................... 8-84
8.5.12 Error Management..................................................................................................... 8-86
8.6 Initialization/Application Information...........................................................................8-87
8.6.1 Programming Differences between Memory Types.................................................. 8-89
8.6.2 DDR SDRAM Initialization Sequence...................................................................... 8-94
8.6.3 Using Forced Self-Refresh Mode to Implement a Battery-Backed
RAM System ......................................................................................................... 8-94
8.6.3.1 Hardware Based Self-Refresh................................................................................ 8-94
8.6.3.2 Software Based Self-Refresh................................................................................. 8-95
8.6.3.3 Bypassing Re-initialization During Battery-Backed Operation ............................ 8-95
Chapter 9
Programmable Interrupt Controller (PIC)
9.1 Introduction...................................................................................................................... 9-1
9.1.1 Overview...................................................................................................................... 9-1
9.1.2 Interrupts to the Processor Core................................................................................... 9-4
9.1.3 Modes of Operation ..................................................................................................... 9-4
9.1.3.1 Mixed Mode (GCR[M] = 1) .................................................................................... 9-5
9.1.3.2 Pass-Through Mode (GCR[M] = 0) ........................................................................ 9-5
9.1.4 Interrupt Sources..........................................................................................................9-5
9.1.4.1 Interrupt Routing—Mixed Mode.............................................................................9-6
9.1.4.2 Interrupt Destinations .............................................................................................. 9-6
9.1.4.3 Internal Interrupt Sources ........................................................................................ 9-6
9.2 External Signal Descriptions ........................................................................................... 9-7
9.2.1 Signal Overview .......................................................................................................... 9-8
9.2.2 Detailed Signal Descriptions ....................................................................................... 9-8
9.3 Memory Map/Register Definition ................................................................................... 9-9
9.3.1 Global Registers......................................................................................................... 9-19
9.3.1.1 Block Revision Register 1 (BRR1)........................................................................ 9-19
9.3.1.2 Block Revision Register 2 (BRR2)........................................................................ 9-19
9.3.1.3 Feature Reporting Register (FRR)......................................................................... 9-20
9.3.1.4 Global Configuration Register (GCR)................................................................... 9-21
9.3.1.5 Vendor Identification Register (VIR) ....................................................................9-21
9.3.1.6 Processor Core Initialization Register (PIR) .........................................................9-22
9.3.1.7 Interprocessor Interrupt Vector/Priority Registers (IPIVPR0–IPIVPR3).............. 9-22
9.3.1.8 Spurious Vector Register (SVR)............................................................................ 9-23
9.3.2 Global Timer Registers.............................................................................................. 9-23
9.3.2.1 Timer Frequency Reporting Register (TFRRA–TFRRB) ..................................... 9-24
9.3.2.2 Global Timer Current Count Registers (GTCCRA0–GTCCRA3,
GTCCRB0–GTCCRB3)..................................................................................... 9-24
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9.3.2.3 Global Timer Base Count Registers (GTBCRA0–GTBCRA3,
GTBCRB0–GTBCRB3)..................................................................................... 9-25
9.3.2.4 Global Timer Vector/Priority Registers (GTVPRA0–GTVPRA3,
GTVPRB0–GTVPRB3)..................................................................................... 9-25
9.3.2.5 Global Timer Destination Registers (GTDRA0–GTDRA3, GTDRB0–GTDRB3) 9-26
9.3.2.6 Timer Control Registers (TCRA–TCRB).............................................................. 9-27
9.3.3 IRQ_OUT and Critical Interrupt Summary Registers............................................... 9-28
9.3.3.1 External Interrupt Summary Register (ERQSR) ................................................... 9-29
9.3.3.2 IRQ_OUT
Summary Register 0 (IRQSR0)...........................................................9-29
9.3.3.3 IRQ_OUT
Summary Register 1 (IRQSR1)...........................................................9-30
9.3.3.4 IRQ_OUT Summary Register 2 (IRQSR2)...........................................................9-31
9.3.3.5 Critical Interrupt Summary Register 0 (CISR0)....................................................9-31
9.3.3.6 Critical Interrupt Summary Register 1 (CISR1)....................................................9-32
9.3.3.7 Critical Interrupt Summary Register 2 (CISR2)....................................................9-32
9.3.4 Performance Monitor Mask Registers (PMMRs)......................................................9-32
9.3.4.1 Performance Monitor Mask Registers 0 (PM0MR0–PM3MR0) .......................... 9-33
9.3.4.2 Performance Monitor Mask Registers 1 (PM0MR1–PM3MR1) .......................... 9-34
9.3.4.3 Performance Monitor Mask Registers 2 (PM0MR2–PM3MR2) .......................... 9-34
9.3.5 Message Registers...................................................................................................... 9-34
9.3.5.1 Message Registers (MSGR0–MSGR7)................................................................. 9-35
9.3.5.2 Message Enable Register (MER)........................................................................... 9-35
9.3.5.3 Message Status Register (MSR) ............................................................................ 9-36
9.3.6 Shared Message Signaled Registers .......................................................................... 9-36
9.3.6.1 Shared Message Signaled Interrupt Registers (MSIR0–MSIR7).......................... 9-37
9.3.6.2 Shared Message Signaled Interrupt Status Register (MSISR)............................... 9-37
9.3.6.3 Shared Message Signaled Interrupt Index Register (MSIIR)................................ 9-38
9.3.6.4 Shared Message Signaled Interrupt Vector/Priority Register (MSIVPRs)............ 9-38
9.3.6.5 Shared Message Signaled Interrupt Destination Registers 0–7 (MSIDRn)........... 9-39
9.3.7 Interrupt Source Configuration Registers.................................................................. 9-40
9.3.7.1 External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ....................... 9-41
9.3.7.2 External Interrupt Destination Registers (EIDR0–EIDR11) .................................9-42
9.3.7.3 Internal Interrupt Vector/Priority Registers (IIVPRn)...........................................9-43
9.3.7.4 Internal Interrupt Destination Registers (IIDRn)...................................................9-44
9.3.7.5 Messaging Interrupt Vector/Priority Registers (MIVPRn).................................... 9-45
9.3.7.6 Messaging Interrupt Destination Registers (MIDR0–MIDR7)............................. 9-46
9.3.8 Per-CPU (Private Access) Registers.......................................................................... 9-46
9.3.8.1 Interprocessor Interrupt Dispatch Register (IPIDR0–IPIDR3) .............................9-48
9.3.8.2 Processor Core Current Task Priority Registers 0–1 (CTPR0–CTPR1) ............... 9-49
9.3.8.3 Who Am I Registers 0–1 (WHOAMI0–WHOAMI1)...........................................9-50
9.3.8.4 Processor Core Interrupt Acknowledge Registers 0–1 (IACK0–IACK1)............. 9-50
9.3.8.5 Processor Core End of Interrupt Registers (EOI0–EOI1) .....................................9-51
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9.4 Functional Description................................................................................................... 9-52
9.4.1 Flow of Interrupt Control........................................................................................... 9-52
9.4.1.1 Interrupts Routed to cint
or IRQ_OUT.................................................................. 9-52
9.4.1.2 Interrupts Routed to int.......................................................................................... 9-52
9.4.1.2.1 Interrupt Source Priority.................................................................................... 9-54
9.4.1.2.2 Interrupt Acknowledge...................................................................................... 9-54
9.4.1.2.3 Spurious Vector Generation............................................................................... 9-55
9.4.1.2.4 Nesting of Interrupts.......................................................................................... 9-55
9.4.2 Interprocessor Interrupts............................................................................................ 9-55
9.4.3 Message Interrupts..................................................................................................... 9-56
9.4.4 Shared Message Signaled Interrupts.......................................................................... 9-56
9.4.5 PCI Express INTx/IRQn Sharing .............................................................................. 9-56
9.4.6 Global Timers ............................................................................................................ 9-57
9.4.7 Resets.........................................................................................................................9-57
9.4.8 Resetting the PIC ....................................................................................................... 9-58
9.4.8.1 Processor Core Initialization..................................................................................9-58
9.5 Initialization/Application Information...........................................................................9-58
9.5.1 Programming Guidelines........................................................................................... 9-58
9.5.1.1 PIC Registers ......................................................................................................... 9-58
9.5.1.2 Changing Interrupt Source Configuration ............................................................. 9-60
Chapter 10
Security Engine (SEC) 3.0
10.1 SEC Architecture Overview .......................................................................................... 10-3
10.1.1 Descriptor Overview.................................................................................................. 10-4
10.1.2 Polychannel Overview............................................................................................... 10-5
10.1.3 Controller Overview .................................................................................................. 10-6
10.1.4 Execution Units (EUs) Overview.............................................................................. 10-7
10.1.4.1 Public Key Execution Unit (PKEU)...................................................................... 10-7
10.1.4.1.1 Elliptic Curve Operations..................................................................................10-7
10.1.4.1.2 Modular Exponentiation Operations ................................................................. 10-8
10.1.4.2 Data Encryption Standard Execution Unit (DEU).................................................10-8
10.1.4.3 Advanced Encryption Standard Execution Unit (AESU)...................................... 10-9
10.1.4.4 Arc Four Execution Unit (AFEU) ....................................................................... 10-10
10.1.4.5 Message Digest Execution Unit (MDEU) ........................................................... 10-10
10.1.4.6 Kasumi Execution Unit (KEU)............................................................................ 10-10
10.1.4.7 Cyclical Redundancy Check Unit (CRCU).........................................................10-10
10.1.4.8 Random Number Generator Unit (RNGU).......................................................... 10-11
10.2 Configuration of Internal Memory Space.................................................................... 10-11
10.3 Descriptors................................................................................................................... 10-19
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10.3.1 Descriptor Structure................................................................................................. 10-20
10.3.2 Descriptor Format: Header Dword.......................................................................... 10-20
10.3.2.1 Selecting Execution Units—EU_SEL0 and EU_SEL1.......................................10-22
10.3.2.2 Selecting Descriptor Type—DESC_TYPE .........................................................10-23
10.3.3 Descriptor Format: Pointer Dwords......................................................................... 10-25
10.3.4 Link Table Format ................................................................................................... 10-26
10.3.4.1 Example of Link Table Operation ....................................................................... 10-29
10.3.5 Descriptor Types...................................................................................................... 10-30
10.4 Polychannel..................................................................................................................10-32
10.4.1 Channel Operation................................................................................................... 10-32
10.4.1.1 Channel Descriptor Processing............................................................................ 10-32
10.4.1.2 Channel Arbitration ............................................................................................. 10-33
10.4.1.3 Channel Host Notification................................................................................... 10-34
10.4.2 Channel Interrupts.................................................................................................... 10-34
10.4.2.1 Channel Done Interrupt ....................................................................................... 10-35
10.4.2.2 Channel Error Interrupt........................................................................................ 10-35
10.4.3 Polychannel Registers.............................................................................................. 10-35
10.4.3.1 Traffic Counters...................................................................................................10-35
10.4.3.1.1 Fetch FIFO Enqueue Counter.......................................................................... 10-35
10.4.3.1.2 Descriptor Finished Counter............................................................................ 10-36
10.4.3.1.3 Data Bytes In Counter ..................................................................................... 10-36
10.4.3.1.4 Data Bytes Out Counter................................................................................... 10-37
10.4.4 Channel Registers .................................................................................................... 10-37
10.4.4.1 Channel Configuration Register (CCR)............................................................... 10-37
10.4.4.2 Channel Status Register (CSR)............................................................................ 10-41
10.4.4.3 Current Descriptor Pointer Register (CDPR) ...................................................... 10-43
10.4.4.4 Fetch FIFO Enqueue Register (FFER)................................................................ 10-44
10.4.5 Channel Buffers and Tables..................................................................................... 10-45
10.4.5.1 Descriptor Buffer (DB)........................................................................................ 10-45
10.4.5.2 Scatter and Gather Link Tables (SLT, GLT)........................................................ 10-45
10.5 Controller..................................................................................................................... 10-46
10.5.1 Bus Transfers ........................................................................................................... 10-46
10.5.1.1 Host-Controlled Access....................................................................................... 10-46
10.5.1.2 Channel-Controlled Access ................................................................................. 10-47
10.5.1.2.1 Channel Controlled Read—Detailed Description ........................................... 10-47
10.5.1.2.2 System Bus Master Write—Detailed Description........................................... 10-48
10.5.2 Arbitration Algorithms ............................................................................................ 10-48
10.5.2.1 Round-Robin Arbitration.....................................................................................10-48
10.5.2.2 Weighted Priority Arbitration.............................................................................. 10-48
10.5.3 Controller Interrupts ................................................................................................ 10-49
10.5.3.1 Controller Interrupt Conditions and Interrupt Generation................................... 10-49
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10.5.3.2 Blocking of Interrupts.......................................................................................... 10-49
10.5.3.3 Interrupt Handling ............................................................................................... 10-49
10.5.4 Controller Registers................................................................................................. 10-50
10.5.4.1 EU Assignment Status Register (EUASR).......................................................... 10-50
10.5.4.2 Interrupt Enable, Interrupt Status, and Interrupt Clear Registers (IER, ISR, ICR).......
10-50
10.5.4.2.1 Interrupt Enable Register (IER)....................................................................... 10-53
10.5.4.2.2 Interrupt Status Register (ISR) ........................................................................ 10-53
10.5.4.3 Interrupt Clear Register (ICR)............................................................................. 10-54
10.5.4.4 ID Register........................................................................................................... 10-54
10.5.4.5 IP Block Revision Register.................................................................................. 10-54
10.5.4.6 Master Control Register (MCR).......................................................................... 10-55
10.6 Power Saving Mode..................................................................................................... 10-57
10.7 Execution Units............................................................................................................10-57
10.7.1 Advanced Encryption Standard Execution Unit (AESU)........................................ 10-57
10.7.1.1 ICV Checking in AESU....................................................................................... 10-58
10.7.1.2 AESU Mode Register .......................................................................................... 10-58
10.7.1.3 AESU Key Size Register..................................................................................... 10-61
10.7.1.4 AESU Data Size Register.................................................................................... 10-61
10.7.1.5 AESU Reset Control Register ............................................................................. 10-62
10.7.1.6 AESU Status Register.......................................................................................... 10-62
10.7.1.7 AESU Interrupt Status Register........................................................................... 10-64
10.7.1.8 AESU Interrupt Mask Register............................................................................ 10-66
10.7.1.9 AESU ICV Size Register..................................................................................... 10-67
10.7.1.10 AESU End of Message Register.......................................................................... 10-68
10.7.1.11 AESU Context Registers ..................................................................................... 10-68
10.7.1.11.1 Context for Confidentiality Cipher Modes......................................................10-68
10.7.1.11.2 Context for Data Integrity Cipher Modes........................................................ 10-71
10.7.1.11.3 Context for Confidentiality and Data Integrity Cipher Modes........................ 10-74
10.7.1.12 AESU Key Registers ........................................................................................... 10-87
10.7.1.12.1 AESU FIFOs.................................................................................................... 10-88
10.7.2 ARC4 Execution Unit (AFEU)................................................................................ 10-88
10.7.2.1 AFEU Mode Register.......................................................................................... 10-89
10.7.2.2 AFEU Key Size Register..................................................................................... 10-89
10.7.2.3 AFEU Context/Data Size Register ...................................................................... 10-90
10.7.2.4 AFEU Reset Control Register ............................................................................. 10-91
10.7.2.5 AFEU Status Register.......................................................................................... 10-91
10.7.2.6 AFEU Interrupt Status Register........................................................................... 10-92
10.7.2.7 AFEU Interrupt Mask Register............................................................................ 10-94
10.7.2.8 AFEU End of Message Register.......................................................................... 10-96
10.7.2.9 AFEU Context ..................................................................................................... 10-96
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10.7.2.9.1 Writing AFEU Context.................................................................................... 10-96
10.7.2.9.2 Reading AFEU Context................................................................................... 10-97
10.7.2.10 AFEU Key Registers ........................................................................................... 10-97
10.7.2.10.1 AFEU FIFOs.................................................................................................... 10-97
10.7.3 Cyclical Redundancy Check Unit (CRCU)............................................................. 10-98
10.7.3.1 ICV Checking in CRCU...................................................................................... 10-98
10.7.3.2 CRCU Mode Register.......................................................................................... 10-98
10.7.3.3 CRCU Key Size Register..................................................................................... 10-99
10.7.3.4 CRCU Data Size Register.................................................................................. 10-100
10.7.3.5 CRCU Reset Control Register........................................................................... 10-100
10.7.3.6 CRCU Control Register..................................................................................... 10-101
10.7.3.7 CRCU Status Register ....................................................................................... 10-101
10.7.3.8 CRCU Interrupt Status Register ........................................................................ 10-102
10.7.3.9 CRCU Interrupt Mask Register ......................................................................... 10-104
10.7.3.10 CRCU ICV Size Register .................................................................................. 10-106
10.7.3.11 CRCU End of Message Register ....................................................................... 10-106
10.7.3.12 CRCU Context Register .................................................................................... 10-106
10.7.3.13 CRCU Key Register .......................................................................................... 10-108
10.7.3.14 CRCU FIFO....................................................................................................... 10-108
10.7.4 Data Encryption Standard Execution Unit (DEU)................................................. 10-108
10.7.4.1 DEU Mode Register .......................................................................................... 10-109
10.7.4.2 DEU Key Size Register ..................................................................................... 10-110
10.7.4.3 DEU Data Size Register (DEUDSR)................................................................. 10-110
10.7.4.4 DEU Reset Control Register...............................................................................10-111
10.7.4.5 DEU Status Register.......................................................................................... 10-112
10.7.4.6 DEU Interrupt Status Register........................................................................... 10-113
10.7.4.7 DEU Interrupt Mask Register............................................................................ 10-115
10.7.4.8 DEU End of Message Register.......................................................................... 10-116
10.7.4.9 DEU IV Register................................................................................................ 10-117
10.7.4.10 DEU Key Registers............................................................................................ 10-117
10.7.4.11 DEU FIFOs........................................................................................................ 10-117
10.7.5 Kasumi Execution Unit (KEU).............................................................................. 10-117
10.7.5.1 KEU Mode Register (KEUMR) ........................................................................ 10-118
10.7.5.2 KEU Key Size Register (KEUKSR).................................................................. 10-119
10.7.5.3 KEU Data Size Register (KEUDSR)................................................................. 10-120
10.7.5.4 KEU Reset Control Register (KEURCR).......................................................... 10-121
10.7.5.5 KEU Status Register (KEUSR) ......................................................................... 10-122
10.7.5.6 KEU Interrupt Status Register (KEUISR)......................................................... 10-123
10.7.5.7 KEU Interrupt Mask Register (KEUIMR) ........................................................ 10-125
10.7.5.8 KEU Data Out Register (f9 MAC) (KEUDOR)................................................ 10-127
10.7.5.9 KEU End of Message Register (KEUEMR) .....................................................10-127
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10.7.5.10 KEU IV_1 Register (KEUIV1) ......................................................................... 10-128
10.7.5.11 KEU ICV_In Register (KEUICV)..................................................................... 10-129
10.7.5.12 KEU IV_2 Register (FRESH) (KEUIV2) ......................................................... 10-129
10.7.5.13 KEU Context Data Registers (KEUCn) ............................................................ 10-129
10.7.5.14 KEU Key Data Registers_1 and _2 (Confidentiality Key) (KEUKDn)............ 10-130
10.7.5.15 KEU Key Data Registers _3 and _4 (Integrity Key) (KEUKDn) ..................... 10-130
10.7.5.16 KEU FIFOs........................................................................................................10-131
10.7.6 Message Digest Execution Unit (MDEU) ............................................................. 10-132
10.7.6.1 ICV Checking in MDEU ................................................................................... 10-132
10.7.6.2 MDEU Mode Register....................................................................................... 10-132
10.7.6.3 Recommended Settings for MDEU Mode Register .......................................... 10-135
10.7.6.4 MDEU Key Size Register.................................................................................. 10-136
10.7.6.5 MDEU Data Size Register................................................................................. 10-137
10.7.6.6 MDEU Reset Control Register.......................................................................... 10-137
10.7.6.7 MDEU Status Register ...................................................................................... 10-138
10.7.6.8 MDEU Interrupt Status Register........................................................................ 10-139
10.7.6.9 MDEU Interrupt Mask Register ........................................................................ 10-141
10.7.6.10 MDEU ICV Size Register ................................................................................. 10-142
10.7.6.11 MDEU End of Message Register ...................................................................... 10-143
10.7.6.12 MDEU Context Registers.................................................................................. 10-143
10.7.6.13 MDEU Key Registers........................................................................................ 10-146
10.7.6.14 MDEU FIFOs .................................................................................................... 10-146
10.7.7 Public Key Execution Units (PKEU)..................................................................... 10-146
10.7.7.1 PKEU Mode Register........................................................................................ 10-147
10.7.7.2 PKEU Key Size Register................................................................................... 10-147
10.7.7.3 PKEU AB Size Register.................................................................................... 10-148
10.7.7.4 PKEU Data Size Register.................................................................................. 10-149
10.7.7.5 PKEU Reset Control Register ........................................................................... 10-149
10.7.7.6 PKEU Status Register........................................................................................ 10-150
10.7.7.7 PKEU Interrupt Status Register......................................................................... 10-151
10.7.7.8 PKEU Interrupt Mask Register.......................................................................... 10-153
10.7.7.9 PKEU End of Message Register........................................................................ 10-154
10.7.7.10 PKEU Parameter Memories .............................................................................. 10-154
10.7.7.10.1 PKEU Parameter Memory A......................................................................... 10-154
10.7.7.10.2 PKEU Parameter Memory B......................................................................... 10-155
10.7.7.10.3 PKEU Parameter Memory E ......................................................................... 10-155
10.7.7.10.4 PKEU Parameter Memory N......................................................................... 10-155
10.7.8 Random Number Generator Unit (RNGU)............................................................10-155
10.7.8.1 RNGU Mode Register ....................................................................................... 10-156
10.7.8.2 RNGU Data Size Register ................................................................................. 10-156
10.7.8.3 RNGU Reset Control Register........................................................................... 10-156
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10.7.8.4 RNGU Status Register....................................................................................... 10-157
10.7.8.5 RNGU Interrupt Status Register........................................................................ 10-158
10.7.8.6 RNGU Interrupt Mask Register......................................................................... 10-159
10.7.8.7 RNGU End of Message Register....................................................................... 10-160
10.7.8.8 RNGU Entropy Registers.................................................................................. 10-161
10.7.8.9 RNGU FIFO ...................................................................................................... 10-161
Chapter 11
I
2
C Interfaces
11.1 Introduction....................................................................................................................11-1
11.1.1 Overview.................................................................................................................... 11-2
11.1.2 Features...................................................................................................................... 11-2
11.1.3 Modes of Operation ................................................................................................... 11-2
11.2 External Signal Descriptions ......................................................................................... 11-3
11.2.1 Signal Overview ........................................................................................................ 11-3
11.2.2 Detailed Signal Descriptions ..................................................................................... 11-3
11.3 Memory Map/Register Definition ................................................................................. 11-4
11.3.1 Register Descriptions................................................................................................. 11-5
11.3.1.1 I
2
C Address Register (I2CADR)........................................................................... 11-6
11.3.1.2 I
2
C Frequency Divider Register (I2CFDR)........................................................... 11-6
11.3.1.3 I
2
C Control Register (I2CCR)............................................................................... 11-7
11.3.1.4 I
2
C Status Register (I2CSR).................................................................................. 11-9
11.3.1.5 I
2
C Data Register (I2CDR).................................................................................. 11-10
11.3.1.6 Digital Filter Sampling Rate Register (I2CDFSRR)............................................11-11
11.4 Functional Description..................................................................................................11-11
11.4.1 Transaction Protocol.................................................................................................11-11
11.4.1.1 START Condition................................................................................................ 11-12
11.4.1.2 Slave Address Transmission................................................................................ 11-12
11.4.1.3 Repeated START Condition ................................................................................ 11-13
11.4.1.4 STOP Condition................................................................................................... 11-13
11.4.1.5 Protocol Implementation Details......................................................................... 11-13
11.4.1.5.1 Transaction Monitoring—Implementation Details.......................................... 11-14
11.4.1.5.2 Control Transfer—Implementation Details..................................................... 11-14
11.4.1.6 Address Compare—Implementation Details....................................................... 11-15
11.4.2 Arbitration Procedure .............................................................................................. 11-15
11.4.2.1 Arbitration Control .............................................................................................. 11-15
11.4.3 Handshaking ............................................................................................................ 11-16
11.4.4 Clock Control........................................................................................................... 11-16
11.4.4.1 Clock Synchronization......................................................................................... 11-16
11.4.4.2 Input Synchronization and Digital Filter............................................................. 11-16
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11.4.4.2.1 Input Signal Synchronization .......................................................................... 11-16
11.4.4.2.2 Filtering of SCL and SDA Lines ..................................................................... 11-17
11.4.4.3 Clock Stretching .................................................................................................. 11-17
11.4.5 Boot Sequencer Mode.............................................................................................. 11-17
11.4.5.1 EEPROM Calling Address .................................................................................. 11-18
11.4.5.2 EEPROM Data Format........................................................................................ 11-19
11.5 Initialization/Application Information......................................................................... 11-21
11.5.1 Initialization Sequence............................................................................................. 11-21
11.5.2 Generation of START .............................................................................................. 11-21
11.5.3 Post-Transfer Software Response............................................................................ 11-22
11.5.4 Generation of STOP................................................................................................. 11-22
11.5.5 Generation of Repeated START.............................................................................. 11-23
11.5.6 Generation of SCL When SDA Low....................................................................... 11-23
11.5.7 Slave Mode Interrupt Service Routine..................................................................... 11-23
11.5.7.1 Slave Transmitter and Received Acknowledge................................................... 11-23
11.5.7.2 Loss of Arbitration and Forcing of Slave Mode.................................................. 11-24
11.5.8 Interrupt Service Routine Flowchart........................................................................ 11-24
Chapter 12
DUART
12.1 Overview........................................................................................................................12-1
12.1.1 Features......................................................................................................................12-1
12.1.2 Modes of Operation ................................................................................................... 12-2
12.2 External Signal Descriptions ......................................................................................... 12-3
12.3 Memory Map/Register Definition ................................................................................. 12-3
12.3.1 Register Descriptions................................................................................................. 12-5
12.3.1.1 Receiver Buffer Registers (URBRn) (ULCR[DLAB] = 0)...................................12-5
12.3.1.2 Transmitter Holding Registers (UTHRn) (ULCR[DLAB] = 0)............................ 12-5
12.3.1.3 Divisor Most and Least Significant Byte Registers (UDMB and UDLB)
(ULCR[DLAB] = 1).......................................................................................... 12-6
12.3.1.4 Interrupt Enable Register (UIER) (ULCR[DLAB] = 0)........................................ 12-7
12.3.1.5 Interrupt ID Registers (UIIRn) (ULCR[DLAB] = 0)............................................ 12-8
12.3.1.6 FIFO Control Registers (UFCRn) (ULCR[DLAB] = 0).....................................12-10
12.3.1.7 Alternate Function Registers (UAFRn) (ULCR[DLAB] = 1)............................. 12-11
12.3.1.8 Line Control Registers (ULCRn)......................................................................... 12-11
12.3.1.9 Modem Control Registers (UMCRn) .................................................................. 12-14
12.3.1.10 Line Status Registers (ULSRn) ........................................................................... 12-15
12.3.1.11 Modem Status Registers (UMSRn) ..................................................................... 12-16
12.3.1.12 Scratch Registers (USCRn) ................................................................................. 12-17
12.3.1.13 DMA Status Registers (UDSRn)......................................................................... 12-17
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