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MPC8572E PowerQUICC™ III
Integrated Host Processor
Family Reference Manual
Supports
MPC8572E
MPC8572
MPC8572ERM
Rev. 2
05/2008
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Document Number: MPC8572ERM
Rev. 2, 05/2008
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Part I—Overview I
Overview 1
Memory Map 2
Signal Descriptions 3
Reset, Clocking, and Initialization 4
Part II—e500 Core Complex and L2 Cache II
Core Complex Overview 5
Core Register Summary 6
L2 Look-Aside Cache/SRAM 7
Part III—Memory, Security, and I/O Interfaces III
e500 Coherency Module 8
DDR Memory Controllers 9
Programmable Interrupt Controller (PIC) 10
Security Engine (SEC) 3.0 11
I2C Interfaces 12
DUART 13
Enhanced Local Bus Controller 14
Enhanced Three-Speed Ethernet Controllers 15
10/100 Fast Ethernet Controller 16
Pattern Matcher (PM) 1.1 17
Table Lookup Unit 18
DMA Controllers 19
Serial RapidIO Interface 20
PCI Express Interface Controller 21
General Purpose I/O (GPIO) 22
Part IV—Global Functions and Debug IV
Global Utilities 22
Device Performance Monitor 23
Debug Features and Watchpoint Facility 24
Revision History A
Glossary GLO
Index IND
I Part I—Overview
1 Overview
2 Memory Map
3 Signal Descriptions
4 Reset, Clocking, and Initialization
II Part II—e500 Core Complex and L2 Cache
5 Core Complex Overview
6 Core Register Summary
7 L2 Look-Aside Cache/SRAM
III Part III—Memory, Security, and I/O Interfaces
8 e500 Coherency Module
9 DDR Memory Controllers
10 Programmable Interrupt Controller (PIC)
11 Security Engine (SEC) 3.0
12 I2C Interfaces
13 DUART
14 Enhanced Local Bus Controller
15 Enhanced Three-Speed Ethernet Controllers
16 10/100 Fast Ethernet Controller
17 Pattern Matcher (PM) 1.1
18 Table Lookup Unit
19 DMA Controllers
20 Serial RapidIO Interface
21 PCI Express Interface Controller
22 General Purpose I/O (GPIO)
IV Part IV—Global Functions and Debug
23 Global Utilities
24 Device Performance Monitor
25 Debug Features and Watchpoint Facility
A Revision History
GLO Glossary
IND Index
MPC8572E PowerQUICC™ III Integrated Host Processor Family Reference Manual, Rev. 2
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Contents
Paragraph
Number Title
Page
Number
Co nt ents
About This Book
Audience .....................................................................................................................cxxvii
Organization ................................................................................................................cxxvii
Suggested Reading ........................................................................................................cxxx
General Information.......................................................................................................cxxx
Related Documentation..................................................................................................cxxx
Conventions .................................................................................................................cxxxi
Signal Conventions .....................................................................................................cxxxii
Acronyms and Abbreviations .....................................................................................cxxxii
Part I
Overview
Chapter 1
Overview
1.1 Introduction......................................................................................................................1-1
1.2 MPC8572E Overview......................................................................................................1-2
1.2.1 Key Features ................................................................................................................1-2
1.3 MPC8572E Architecture Overview................................................................................. 1-3
1.3.1 e500 Core Overview.................................................................................................... 1-3
1.3.2 On-Chip Memory Unit................................................................................................. 1-4
1.3.3 e500 Coherency Module (ECM)..................................................................................1-4
1.3.4 DDR SDRAM Controllers........................................................................................... 1-4
1.3.5 Programmable Interrupt Controller (PIC).................................................................... 1-5
1.3.6 Integrated Security Engine (SEC)................................................................................ 1-5
1.3.7 I
2
C Controllers............................................................................................................. 1-6
1.3.8 Boot Sequencer............................................................................................................ 1-6
1.3.9 Dual Universal Asynchronous Receiver/Transmitter (DUART).................................1-6
1.3.10 Enhanced Local Bus Controller................................................................................... 1-7
1.3.11 Enhanced Three-Speed Ethernet Controllers (eTSECs).............................................. 1-7
1.3.12 10/100 Fast Ethernet Maintenance Interface (FEC) ....................................................1-9
1.3.13 Pattern Matching Engine (PME) with DEFLATE Engine...........................................1-9
1.3.14 Table Lookup Unit (TLU)............................................................................................1-9
1.3.15 OceaN Switch Fabric.................................................................................................1-10
1.3.16 Integrated DMA......................................................................................................... 1-10
1.3.17 High Speed I/O Interfaces.......................................................................................... 1-11
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1.3.18 Serial RapidIO Interface............................................................................................ 1-11
1.3.18.1 RapidIO Message Unit .......................................................................................... 1-11
1.3.19 PCI Express Interfaces...............................................................................................1-12
1.3.20 Power Management ................................................................................................... 1-12
1.3.21 Clocking..................................................................................................................... 1-12
1.3.22 Address Map..............................................................................................................1-13
1.3.23 Processing Across the On-Chip Fabric...................................................................... 1-13
1.3.24 Data Processing with the e500 Coherency Module...................................................1-13
1.4 MPC8572E Application Examples................................................................................ 1-14
1.4.1 Dual-Core Device Application .................................................................................. 1-14
1.4.2 Virtual Private Network (VPN) Access Router.........................................................1-16
1.4.3 High-Performance Communication System
Using Distributed Processing ................................................................................ 1-16
1.4.4 High-Performance Communication System.............................................................. 1-17
1.4.5 RAID Controller Application .................................................................................... 1-17
1.4.6 SerDes Application.................................................................................................... 1-18
1.4.7 DSP Farm Application............................................................................................... 1-18
Chapter 2
Memory Map
2.1 Local Memory Map Overview and Example .................................................................. 2-1
2.2 Address Translation and Mapping................................................................................... 2-3
2.2.1 SRAM Windows..........................................................................................................2-4
2.2.2 Window into Configuration Space............................................................................... 2-4
2.2.3 Local Access Windows................................................................................................ 2-4
2.2.3.1 Local Access Register Memory Map ...................................................................... 2-5
2.2.3.2 Local Access IP Block Revision Register 1 (LAIPBRR1)......................................2-6
2.2.3.3 Local Access IP Block Revision Register 2 (LAIPBRR2)......................................2-6
2.2.3.4 Local Access Window n Base Address Registers (LAWBAR0–LAWBAR11)...... 2-7
2.2.3.5 Local Access Window n Attributes Registers (LAWAR0–LAWAR11)..................2-8
2.2.3.6 Precedence of Local Access Windows....................................................................2-9
2.2.3.7 Configuring Local Access Windows.......................................................................2-9
2.2.3.8 Distinguishing Local Access Windows from Other Mapping Functions................ 2-9
2.2.3.9 Illegal Interaction Between Local Access Windows and DDR
SDRAM Chip Selects.......................................................................................... 2-9
2.2.4 Outbound Address Translation and Mapping Windows............................................ 2-10
2.2.5 Inbound Address Translation and Mapping Windows ..............................................2-10
2.2.5.1 Serial RapidIO Inbound ATMU............................................................................. 2-10
2.2.5.2 PCI Express Inbound ATMU................................................................................. 2-10
2.2.5.3 Illegal Interaction Between Inbound ATMUs and Local Access Windows.......... 2-11
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2.3 Configuration, Control, and Status Register Map.......................................................... 2-11
2.3.1 Accessing CCSR Memory from the Local Processor................................................ 2-12
2.3.2 Accessing CCSR Memory from External Masters.................................................... 2-13
2.3.3 Organization of CCSR Memory ................................................................................ 2-13
2.3.4 General Utilities Registers.........................................................................................2-14
2.3.5 Interrupt Controller and CCSR.................................................................................. 2-15
2.3.6 Serial RapidIO and CCSR ......................................................................................... 2-16
2.3.7 Device-Specific Utilities............................................................................................ 2-16
2.3.8 Accessing Reserved Registers and Bits..................................................................... 2-17
2.4 Complete CCSR Map .................................................................................................... 2-17
Chapter 3
Signal Descriptions
3.1 Signals Overview.............................................................................................................3-1
3.2 Configuration Signals Sampled at Reset ....................................................................... 3-23
3.3 Output Signal States During Reset ................................................................................ 3-25
Chapter 4
Reset, Clocking, and Initialization
4.1 Overview..........................................................................................................................4-1
4.2 External Signal Descriptions ........................................................................................... 4-1
4.2.1 System Control Signals................................................................................................ 4-2
4.2.2 Clock Signals............................................................................................................... 4-3
4.3 Memory Map/Register Definition ................................................................................... 4-4
4.3.1 Local Configuration Control........................................................................................ 4-4
4.3.1.1 Accessing Configuration, Control, and Status Registers.........................................4-5
4.3.1.1.1 Updating CCSRBAR........................................................................................... 4-5
4.3.1.1.2 Configuration, Control, and Status Base Address Register (CCSRBAR)........... 4-6
4.3.1.2 Accessing Alternate Configuration Space............................................................... 4-6
4.3.1.2.1 Alternate Configuration Base Address Register (ALTCBAR)............................4-7
4.3.1.2.2 Alternate Configuration Attribute Register (ALTCAR)...................................... 4-7
4.3.1.3 Boot Page Translation.............................................................................................. 4-8
4.3.1.3.1 Boot Page Translation Register (BPTR).............................................................. 4-9
4.3.2 Boot Sequencer............................................................................................................ 4-9
4.4 Functional Description..................................................................................................... 4-9
4.4.1 Reset Operations.......................................................................................................... 4-9
4.4.1.1 Soft Reset.................................................................................................................4-9
4.4.1.2 Hard Reset ............................................................................................................. 4-10
4.4.2 Power-On Reset Sequence......................................................................................... 4-10
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4.4.3 Power-On Reset Configuration.................................................................................. 4-12
4.4.3.1 System PLL Ratio.................................................................................................. 4-13
4.4.3.2 DDR PLL Ratio..................................................................................................... 4-13
4.4.3.3 e500 Core PLL Ratios ........................................................................................... 4-14
4.4.3.4 Boot ROM Location .............................................................................................. 4-15
4.4.3.5 Host/Agent Configuration ..................................................................................... 4-16
4.4.3.6 I/O Port Selection .................................................................................................. 4-17
4.4.3.7 CPU Boot Configuration ....................................................................................... 4-19
4.4.3.8 Boot Sequencer Configuration .............................................................................. 4-20
4.4.3.9 DDR SDRAM Type............................................................................................... 4-21
4.4.3.10 FEC Configuration................................................................................................. 4-21
4.4.3.11 eTSEC SGMII Mode............................................................................................. 4-21
4.4.3.12 SGMII SerDes Reference Clock Configuration....................................................4-22
4.4.3.13 eTSEC1 and eTSEC2 Width.................................................................................. 4-23
4.4.3.14 eTSEC3 and eTSEC4 Width.................................................................................. 4-24
4.4.3.15 eTSEC1 Protocol ................................................................................................... 4-24
4.4.3.16 eTSEC2 Protocol ................................................................................................... 4-25
4.4.3.17 eTSEC3 Protocol ................................................................................................... 4-25
4.4.3.18 eTSEC4 Protocol ................................................................................................... 4-26
4.4.3.19 RapidIO Device ID................................................................................................ 4-27
4.4.3.20 RapidIO System Size............................................................................................. 4-27
4.4.3.21 Memory Debug Configuration .............................................................................. 4-28
4.4.3.22 DDR Debug Configuration.................................................................................... 4-28
4.4.3.23 General-Purpose POR Configuration .................................................................... 4-28
4.4.3.24 eLBC FCM ECC Configuration............................................................................ 4-29
4.4.3.25 SerDes1 Enable...................................................................................................... 4-29
4.4.3.26 SGMII SerDes Enable ........................................................................................... 4-29
4.4.3.27 Engineering Use POR Configuration .................................................................... 4-30
4.4.4 Clocking.....................................................................................................................4-30
4.4.4.1 System Clock and DDR Controller Complex Clock............................................. 4-30
4.4.4.2 RapidIO and PCI Express Clocks.......................................................................... 4-31
4.4.4.3 SGMII Clocks........................................................................................................ 4-31
4.4.4.3.1 Minimum Frequency Requirements.................................................................. 4-32
4.4.4.4 Ethernet Clocks...................................................................................................... 4-32
4.4.4.5 Real Time Clock.................................................................................................... 4-32
Part II
e500 Core Complex and L2 Cache
Chapter 5
Core Complex Overview
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Contents
Paragraph
Number Title
Page
Number
5.1 Overview..........................................................................................................................5-1
5.1.1 Upward Compatibility .................................................................................................5-3
5.1.2 Core Complex Summary ............................................................................................. 5-3
5.2 e500 Processor and System Version Numbers.................................................................5-4
5.3 Features............................................................................................................................5-5
5.3.1 e500v2 Differences.................................................................................................... 5-10
5.4 Instruction Set................................................................................................................ 5-11
5.5 Instruction Flow.............................................................................................................5-13
5.5.1 Initial Instruction Fetch..............................................................................................5-13
5.5.2 Branch Detection and Prediction............................................................................... 5-13
5.5.3 e500 Execution Pipeline............................................................................................ 5-14
5.6 Programming Model...................................................................................................... 5-16
5.7 On-Chip Cache Implementation.................................................................................... 5-18
5.8 Interrupts and Exception Handling................................................................................ 5-18
5.8.1 Exception Handling ................................................................................................... 5-18
5.8.2 Interrupt Classes ........................................................................................................ 5-19
5.8.3 Interrupt Types........................................................................................................... 5-19
5.8.4 Upper Bound on Interrupt Latencies .........................................................................5-20
5.8.5 Interrupt Registers...................................................................................................... 5-20
5.9 Memory Management.................................................................................................... 5-22
5.9.1 Address Translation ................................................................................................... 5-24
5.9.2 MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7).....................................5-25
5.9.3 Process ID Registers (PID0–PID2)............................................................................ 5-26
5.9.4 TLB Coherency.......................................................................................................... 5-26
5.10 Memory Coherency ....................................................................................................... 5-26
5.10.1 Atomic Update Memory References ......................................................................... 5-27
5.10.2 Memory Access Ordering.......................................................................................... 5-27
5.10.3 Cache Control Instructions ........................................................................................ 5-27
5.10.4 Programmable Page Characteristics .......................................................................... 5-27
5.11 Core Complex Bus (CCB)............................................................................................. 5-27
5.12 Performance Monitoring................................................................................................ 5-28
5.12.1 Global Control Register............................................................................................. 5-28
5.12.2 Performance Monitor Counter Registers................................................................... 5-28
5.12.3 Local Control Registers ............................................................................................. 5-29
5.13 Legacy Support of Power Architecture Technology...................................................... 5-29
5.13.1 Instruction Set Compatibility..................................................................................... 5-29
5.13.1.1 User Instruction Set ............................................................................................... 5-29
5.13.1.2 Supervisor Instruction Set...................................................................................... 5-30
5.13.2 Memory Subsystem ................................................................................................... 5-30
5.13.3 Exception Handling ................................................................................................... 5-30
5.13.4 Memory Management................................................................................................ 5-30
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5.13.5 Reset...........................................................................................................................5-30
5.13.6 Little-Endian Mode....................................................................................................5-31
5.14 PowerQUICC III Implementation Details ..................................................................... 5-31
Chapter 6
Core Register Summary
6.1 Overview..........................................................................................................................6-1
6.1.1 Register Set.................................................................................................................. 6-1
6.2 Register Model for 32-Bit Implementations.................................................................... 6-3
6.2.1 Special-Purpose Registers (SPRs) ............................................................................... 6-4
6.3 Registers for Computational Operations.......................................................................... 6-8
6.3.1 General-Purpose Registers (GPRs).............................................................................. 6-8
6.3.2 Integer Exception Register (XER)............................................................................... 6-8
6.4 Registers for Branch Operations...................................................................................... 6-9
6.4.1 Condition Register (CR).............................................................................................. 6-9
6.4.2 Link Register (LR)..................................................................................................... 6-11
6.4.3 Count Register (CTR)................................................................................................ 6-11
6.5 Processor Control Registers........................................................................................... 6-11
6.5.1 Machine State Register (MSR).................................................................................. 6-11
6.5.2 Processor ID Register (PIR) ...................................................................................... 6-13
6.5.3 Processor Version Register (PVR)............................................................................. 6-13
6.5.4 System Version Register (SVR)................................................................................. 6-14
6.6 Timer Registers..............................................................................................................6-14
6.6.1 Timer Control Register (TCR)................................................................................... 6-14
6.6.2 Timer Status Register (TSR)...................................................................................... 6-15
6.6.3 Time Base Registers .................................................................................................. 6-16
6.6.4 Decrementer Register ................................................................................................ 6-16
6.6.5 Decrementer Auto-Reload Register (DECAR)..........................................................6-17
6.7 Interrupt Registers..........................................................................................................6-17
6.7.1 Interrupt Registers Defined by the Embedded and Base Categories......................... 6-17
6.7.1.1 Save/Restore Register 0 (SRR0)............................................................................ 6-17
6.7.1.2 Save/Restore Register 1 (SRR1)............................................................................ 6-17
6.7.1.3 Critical Save/Restore Register 0 (CSRR0)............................................................ 6-17
6.7.1.4 Critical Save/Restore Register 1 (CSRR1)............................................................ 6-18
6.7.1.5 Data Exception Address Register (DEAR)............................................................ 6-18
6.7.1.6 Interrupt Vector Prefix Register (IVPR)................................................................ 6-18
6.7.1.7 Interrupt Vector Offset Registers (IVORn)............................................................6-18
6.7.1.8 Exception Syndrome Register (ESR) ....................................................................6-19
6.7.2 Additional Interrupt Registers ...................................................................................6-20
6.7.2.1 Machine Check Save/Restore Register 0 (MCSRR0) ...........................................6-20
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6.7.2.2 Machine Check Save/Restore Register 1 (MCSRR1) ...........................................6-20
6.7.2.3 Machine Check Address Register (MCAR/MCARU) .......................................... 6-21
6.7.2.4 Machine Check Syndrome Register (MCSR)........................................................ 6-21
6.8 Software-Use SPRs (SPRG0–SPRG7 and USPRG0) ................................................... 6-22
6.9 Branch Target Buffer (BTB) Registers.......................................................................... 6-23
6.9.1 Branch Buffer Entry Address Register (BBEAR).....................................................6-23
6.9.2 Branch Buffer Target Address Register (BBTAR).................................................... 6-23
6.9.3 Branch Unit Control and Status Register (BUCSR)..................................................6-24
6.10 Hardware Implementation-Dependent Registers........................................................... 6-25
6.10.1 Hardware Implementation-Dependent Register 0 (HID0).........................................6-25
6.10.2 Hardware Implementation-Dependent Register 1 (HID1).........................................6-26
6.11 L1 Cache Configuration Registers................................................................................. 6-28
6.11.1 L1 Cache Control and Status Register 0 (L1CSR0) .................................................. 6-28
6.11.2 L1 Cache Control and Status Register 1 (L1CSR1) .................................................. 6-29
6.11.3 L1 Cache Configuration Register 0 (L1CFG0) .........................................................6-30
6.11.4 L1 Cache Configuration Register 1 (L1CFG1) .........................................................6-31
6.12 MMU Registers..............................................................................................................6-32
6.12.1 Process ID Registers (PID0–PID2)............................................................................ 6-32
6.12.2 MMU Control and Status Register 0 (MMUCSR0)..................................................6-32
6.12.3 MMU Configuration Register (MMUCFG).............................................................. 6-32
6.12.4 TLB Configuration Registers (TLBnCFG)................................................................ 6-33
6.12.4.1 TLB0 Configuration Register 0 (TLB0CFG)........................................................ 6-33
6.12.4.2 TLB1 Configuration Register 1 (TLB1CFG)........................................................ 6-34
6.12.5 MMU Assist Registers............................................................................................... 6-34
6.12.5.1 MAS Register 0 (MAS0)....................................................................................... 6-34
6.12.5.2 MAS Register 1 (MAS1)....................................................................................... 6-35
6.12.5.3 MAS Register 2 (MAS2)....................................................................................... 6-36
6.12.5.4 MAS Register 3 (MAS3)....................................................................................... 6-37
6.12.5.5 MAS Register 4 (MAS4)....................................................................................... 6-38
6.12.5.6 MAS Register 6 (MAS6)....................................................................................... 6-38
6.12.5.7 MAS Register 7 (MAS7)....................................................................................... 6-39
6.13 Debug Registers.............................................................................................................6-39
6.13.1 Debug Control Registers (DBCR0–DBCR2)............................................................6-39
6.13.1.1 Debug Control Register 0 (DBCR0)......................................................................6-39
6.13.1.2 Debug Control Register 1 (DBCR1)...................................................................... 6-41
6.13.1.3 Debug Control Register 2 (DBCR2)...................................................................... 6-42
6.13.2 Debug Status Register (DBSR)..................................................................................6-43
6.13.3 Instruction Address Compare Registers (IAC1–IAC2).............................................6-45
6.13.4 Data Address Compare Registers (DAC1–DAC2).................................................... 6-45
6.14 Signal Processing and Embedded Floating-Point Status
and Control Register (SPEFSCR).............................................................................. 6-45
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6.14.1 Accumulator (ACC)................................................................................................... 6-47
6.15 Performance Monitor Registers (PMRs) ....................................................................... 6-48
6.15.1 Global Control Register 0 (PMGC0, UPMGC0)....................................................... 6-49
6.15.2 Local Control A Registers (PMLCa0–PMLCa3, UPMLCa0–UPMLCa3)............... 6-50
6.15.3 Local Control B Registers (PMLCb0–PMLCb3, UPMLCb0–UPMLCb3) ..............6-51
6.15.4 Performance Monitor Counter Registers (PMC0–PMC3, UPMC0–UPMC3).......... 6-52
Chapter 7
L2 Look-Aside Cache/SRAM
7.1 L2 Cache Overview ......................................................................................................... 7-1
7.1.1 L2 Cache and SRAM Features .................................................................................... 7-1
7.2 L2 Cache and SRAM Organization................................................................................. 7-4
7.2.1 Accessing the On-Chip Array as an L2 Cache............................................................ 7-5
7.2.2 Accessing the On-Chip Array as an SRAM ................................................................ 7-5
7.2.3 Connection of the On-Chip Memory to the System.................................................... 7-7
7.3 Memory Map/Register Definition ................................................................................... 7-8
7.3.1 L2/SRAM Register Descriptions................................................................................. 7-9
7.3.1.1 L2 Control Register (L2CTL).................................................................................. 7-9
7.3.1.2 L2 Cache Way Allocation for Processors Register (L2CWAP) ............................ 7-13
7.3.1.3 L2 Cache External Write Registers ....................................................................... 7-15
7.3.1.3.1 L2 Cache External Write Address Registers 0–3 (L2CEWARn)...................... 7-15
7.3.1.3.2 L2 Cache External Write Address Registers Extended Address
(L2CEWAREAn)........................................................................................... 7-16
7.3.1.3.3 L2 Cache External Write Control Registers 0–3 (L2CEWCRn)....................... 7-16
7.3.1.4 L2 Memory-Mapped SRAM Registers ................................................................. 7-17
7.3.1.4.1 L2 Memory-Mapped SRAM Base Address Registers 0–1 (L2SRBARn)........ 7-18
7.3.1.4.2 L2 Memory-Mapped SRAM Base Address Registers Extended Address 0–1
(L2SRBAREAn)............................................................................................ 7-19
7.3.1.5 L2 Error Registers.................................................................................................. 7-19
7.3.1.5.1 Error Injection Registers.................................................................................... 7-20
7.3.1.5.2 Error Control and Capture Registers ................................................................. 7-22
7.4 External Writes to the L2 Cache (Cache Stashing)........................................................ 7-27
7.4.1 Stash-Only Cache Regions ........................................................................................ 7-28
7.5 L2 Cache Timing ...........................................................................................................7-28
7.6 L2 Cache and SRAM Coherency................................................................................... 7-29
7.6.1 L2 Cache Coherency Rules........................................................................................ 7-29
7.6.2 Memory-Mapped SRAM Coherency Rules .............................................................. 7-31
7.7 L2 Cache Locking.......................................................................................................... 7-31
7.7.1 Locking the Entire L2 Cache..................................................................................... 7-31
7.7.2 Locking Programmed Memory Ranges..................................................................... 7-32
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7.7.3 Locking Selected Lines.............................................................................................. 7-32
7.7.4 Clearing Locks on Selected Lines ............................................................................. 7-32
7.7.5 Flash Clearing of Instruction and Data Locks ........................................................... 7-32
7.7.6 Locks with Stale Data................................................................................................ 7-33
7.8 PLRU L2 Replacement Policy....................................................................................... 7-33
7.8.1 PLRU Bit Update Considerations.............................................................................. 7-34
7.8.2 Allocation of Lines .................................................................................................... 7-34
7.9 L2 Cache Operation....................................................................................................... 7-35
7.9.1 Initialization............................................................................................................... 7-35
7.9.1.1 L2 Cache Initialization .......................................................................................... 7-35
7.9.1.2 Memory-Mapped SRAM Initialization ................................................................. 7-35
7.9.2 Flash Invalidation of the L2 Cache............................................................................ 7-36
7.9.3 Managing Errors ........................................................................................................ 7-36
7.9.3.1 ECC Errors............................................................................................................. 7-36
7.9.3.2 Tag Parity Errors.................................................................................................... 7-36
7.9.4 L2 Cache States ......................................................................................................... 7-36
7.9.5 L2 State Transitions ................................................................................................... 7-37
7.9.6 Error Checking and Correcting (ECC) ...................................................................... 7-41
Part III
Memory, Security, and I/O Interfaces
Chapter 8
e500 Coherency Module
8.1 Introduction......................................................................................................................8-1
8.1.1 Overview......................................................................................................................8-2
8.1.2 Features........................................................................................................................ 8-2
8.2 Memory Map/Register Definition ................................................................................... 8-3
8.2.1 Register Descriptions................................................................................................... 8-3
8.2.1.1 ECM CCB Address Configuration Register (EEBACR) ........................................ 8-3
8.2.1.2 ECM CCB Port Configuration Register (EEBPCR) ...............................................8-4
8.2.1.3 ECM IP Block Revision Register 1 (EIPBRR1) .....................................................8-5
8.2.1.4 ECM IP Block Revision Register 2 (EIPBRR2) .....................................................8-6
8.2.1.5 ECM Error Detect Register (EEDR) ....................................................................... 8-6
8.2.1.6 ECM Error Enable Register (EEER)....................................................................... 8-7
8.2.1.7 ECM Error Attributes Capture Register (EEATR)..................................................8-8
8.2.1.8 ECM Error Low Address Capture Register (EELADR) ......................................... 8-9
8.2.1.9 ECM Error High Address Capture Register (EEHADR) ........................................ 8-9
8.3 Functional Description................................................................................................... 8-10
8.3.1 I/O Arbiter..................................................................................................................8-10
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8.3.2 CCB Arbiter............................................................................................................... 8-10
8.3.3 Transaction Queue ..................................................................................................... 8-10
8.3.4 Global Data Multiplexor............................................................................................ 8-11
8.3.5 CCB Interface ............................................................................................................ 8-11
8.4 Initialization/Application Information........................................................................... 8-11
Chapter 9
DDR Memory Controllers
9.1 Introduction......................................................................................................................9-1
9.2 Features............................................................................................................................9-2
9.2.1 Modes of Operation ..................................................................................................... 9-3
9.3 External Signal Descriptions ........................................................................................... 9-3
9.3.1 Signals Overview......................................................................................................... 9-3
9.3.2 Detailed Signal Descriptions ....................................................................................... 9-6
9.3.2.1 Memory Interface Signals........................................................................................ 9-7
9.3.2.2 Clock Interface Signals.......................................................................................... 9-11
9.3.2.3 Debug Signals........................................................................................................ 9-11
9.4 Memory Map/Register Definition ................................................................................. 9-11
9.4.1 Register Descriptions................................................................................................. 9-13
9.4.1.1 Chip Select Memory Bounds (CSn_BNDS).......................................................... 9-13
9.4.1.2 Chip Select Configuration (CSn_CONFIG)..........................................................9-14
9.4.1.3 Chip Select Configuration 2 (CSn_CONFIG_2)...................................................9-17
9.4.1.4 DDR SDRAM Timing Configuration 3 (TIMING_CFG_3).................................9-17
9.4.1.5 DDR SDRAM Timing Configuration 0 (TIMING_CFG_0).................................9-19
9.4.1.6 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1).................................9-21
9.4.1.7 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2).................................9-23
9.4.1.8 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-25
9.4.1.9 DDR SDRAM Control Configuration 2 (DDR_SDRAM_CFG_2)...................... 9-28
9.4.1.10 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................9-30
9.4.1.11 DDR SDRAM Mode 2 Configuration (DDR_SDRAM_MODE_2)..................... 9-31
9.4.1.12 DDR SDRAM Mode Control Register (DDR_SDRAM_MD_CNTL)................. 9-32
9.4.1.13 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 9-34
9.4.1.14 DDR SDRAM Data Initialization (DDR_DATA_INIT) .......................................9-35
9.4.1.15 DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL).............................9-35
9.4.1.16 DDR Initialization Address (DDR_INIT_ADDR)................................................9-36
9.4.1.17 DDR Initialization Enable Extended Address (DDR_INIT_EXT_ADDR).......... 9-36
9.4.1.18 DDR SDRAM Timing Configuration 4 (TIMING_CFG_4).................................9-37
9.4.1.19 DDR SDRAM Timing Configuration 5 (TIMING_CFG_5).................................9-39
9.4.1.20 DDR ZQ Calibration Control (DDR_ZQ_CNTL) ................................................9-40
9.4.1.21 DDR Write Leveling Control (DDR_WRLVL_CNTL)........................................ 9-42
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9.4.1.22 DDR Debug Status Register 1 (DDRDSR_1) ....................................................... 9-45
9.4.1.23 DDR Debug Status Register 2 (DDRDSR_2) ....................................................... 9-46
9.4.1.24 DDR Control Driver Register 1 (DDRCDR_1).....................................................9-46
9.4.1.25 DDR Control Driver Register 2 (DDRCDR_2).....................................................9-49
9.4.1.26 DDR IP Block Revision 1 (DDR_IP_REV1)........................................................9-50
9.4.1.27 DDR IP Block Revision 2 (DDR_IP_REV2)........................................................9-50
9.4.1.28 Memory Data Path Error Injection Mask High (DATA_ERR_INJECT_HI)........ 9-51
9.4.1.29 Memory Data Path Error Injection Mask Low (DATA_ERR_INJECT_LO)........9-51
9.4.1.30 Memory Data Path Error Injection Mask ECC (ERR_INJECT)...........................9-52
9.4.1.31 Memory Data Path Read Capture High (CAPTURE_DATA_HI)......................... 9-52
9.4.1.32 Memory Data Path Read Capture Low (CAPTURE_DATA_LO)........................9-53
9.4.1.33 Memory Data Path Read Capture ECC (CAPTURE_ECC)..................................9-53
9.4.1.34 Memory Error Detect (ERR_DETECT)................................................................ 9-54
9.4.1.35 Memory Error Disable (ERR_DISABLE)............................................................. 9-55
9.4.1.36 Memory Error Interrupt Enable (ERR_INT_EN).................................................. 9-56
9.4.1.37 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES).......................... 9-57
9.4.1.38 Memory Error Address Capture (CAPTURE_ADDRESS) ..................................9-58
9.4.1.39 Memory Error Extended Address Capture (CAPTURE_EXT_ADDRESS).........9-59
9.4.1.40 Single-Bit ECC Memory Error Management (ERR_SBE)...................................9-59
9.5 Functional Description................................................................................................... 9-60
9.5.1 DDR SDRAM Interface Operation............................................................................ 9-64
9.5.1.1 Supported DDR SDRAM Organizations............................................................... 9-64
9.5.2 DDR SDRAM Address Multiplexing........................................................................ 9-66
9.5.3 JEDEC Standard DDR SDRAM Interface Commands .............................................9-70
9.5.4 DDR SDRAM Interface Timing................................................................................ 9-72
9.5.4.1 Clock Distribution ................................................................................................. 9-75
9.5.5 DDR SDRAM Mode-Set Command Timing.............................................................9-76
9.5.6 DDR SDRAM Registered DIMM Mode................................................................... 9-77
9.5.7 DDR SDRAM Write Timing Adjustments................................................................ 9-77
9.5.8 DDR SDRAM Refresh .............................................................................................. 9-78
9.5.8.1 DDR SDRAM Refresh Timing.............................................................................. 9-79
9.5.8.2 DDR SDRAM Refresh and Power-Saving Modes................................................9-79
9.5.8.2.1 Self-Refresh in Sleep Mode............................................................................... 9-81
9.5.9 DDR Data Beat Ordering........................................................................................... 9-82
9.5.10 Page Mode and Logical Bank Retention ................................................................... 9-82
9.5.11 Error Checking and Correcting (ECC) ...................................................................... 9-83
9.5.12 Error Management..................................................................................................... 9-85
9.6 Initialization/Application Information...........................................................................9-86
9.6.1 Programming Differences Between Memory Types..................................................9-88
9.6.2 DDR SDRAM Initialization Sequence...................................................................... 9-93
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9.6.3 Using Forced Self-Refresh Mode to Implement a Battery-Backed
RAM System ......................................................................................................... 9-93
9.6.3.1 Hardware Based Self-Refresh................................................................................ 9-93
9.6.3.2 Software Based Self-Refresh................................................................................. 9-93
9.6.3.3 Bypassing Re-initialization During Battery-Backed Operation............................9-94
Chapter 10
Programmable Interrupt Controller (PIC)
10.1 Introduction....................................................................................................................10-1
10.1.1 Overview....................................................................................................................10-1
10.1.2 The PIC in Multiple-Processor Implementations...................................................... 10-4
10.1.3 Interrupts to the Processor Core................................................................................. 10-4
10.1.4 Modes of Operation ................................................................................................... 10-5
10.1.4.1 Mixed Mode (GCR[M] = 1).................................................................................. 10-5
10.1.4.2 Pass-Through Mode (GCR[M] = 0) ......................................................................10-5
10.1.5 Interrupt Sources........................................................................................................ 10-6
10.1.5.1 Interrupt Routing—Mixed Mode........................................................................... 10-6
10.1.5.2 Interrupt Destinations ............................................................................................ 10-7
10.1.5.3 Internal Interrupt Sources ...................................................................................... 10-7
10.2 External Signal Descriptions ......................................................................................... 10-9
10.2.1 Signal Overview ........................................................................................................ 10-9
10.2.2 Detailed Signal Descriptions ..................................................................................... 10-9
10.3 Memory Map/Register Definition ............................................................................... 10-10
10.3.1 Global Registers....................................................................................................... 10-20
10.3.1.1 Block Revision Register 1 (BRR1)...................................................................... 10-20
10.3.1.2 Block Revision Register 2 (BRR2)...................................................................... 10-21
10.3.1.3 Feature Reporting Register (FRR)....................................................................... 10-21
10.3.1.4 Global Configuration Register (GCR)................................................................. 10-22
10.3.1.5 Vendor Identification Register (VIR) ..................................................................10-23
10.3.1.6 Processor Core Initialization Register (PIR) .......................................................10-23
10.3.1.7 Interprocessor Interrupt Vector/Priority Registers (IPIVPR0–IPIVPR3)............10-24
10.3.1.8 Spurious Vector Register (SVR).......................................................................... 10-25
10.3.2 Global Timer Registers............................................................................................ 10-25
10.3.2.1 Timer Frequency Reporting Register (TFRRA–TFRRB) ................................... 10-25
10.3.2.2 Global Timer Current Count Registers (GTCCRA0–GTCCRA3,
GTCCRB0–GTCCRB3)................................................................................... 10-26
10.3.2.3 Global Timer Base Count Registers (GTBCRA0–GTBCRA3,
GTBCRB0–GTBCRB3)................................................................................... 10-26
10.3.2.4 Global Timer Vector/Priority Registers (GTVPRA0–GTVPRA3,
GTVPRB0–GTVPRB3)................................................................................... 10-27
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10.3.2.5 Global Timer Destination Registers (GTDRA0–GTDRA3,
GTDRB0–GTDRB3)........................................................................................ 10-28
10.3.2.6 Timer Control Registers (TCRA–TCRB)............................................................ 10-28
10.3.3 IRQ_OUT and Critical Interrupt Summary Registers.............................................10-30
10.3.3.1 External Interrupt Summary Register (ERQSR) .................................................10-31
10.3.3.2 IRQ_OUT Summary Register 0 (IRQSR0)......................................................... 10-31
10.3.3.3 IRQ_OUT Summary Register 1 (IRQSR1)......................................................... 10-32
10.3.3.4 IRQ_OUT Summary Register 2 (IRQSR2)......................................................... 10-33
10.3.3.5 Critical Interrupt Summary Register 0 (CISR0).................................................. 10-33
10.3.3.6 Critical Interrupt Summary Register 1 (CISR1).................................................. 10-34
10.3.3.7 Critical Interrupt Summary Register 2 (CISR2).................................................. 10-34
10.3.4 Performance Monitor Mask Registers (PMMRs)....................................................10-34
10.3.4.1 Performance Monitor Mask Registers 0 (PM0MR0–PM3MR0) ........................ 10-35
10.3.4.2 Performance Monitor Mask Registers 1 (PM0MR1–PM3MR1) ........................ 10-36
10.3.4.3 Performance Monitor Mask Registers 2 (PM0MR2–PM3MR2) ........................ 10-36
10.3.5 Message Registers.................................................................................................... 10-36
10.3.5.1 Message Registers (MSGR0–MSGR7)............................................................... 10-37
10.3.5.2 Message Enable Register (MER)......................................................................... 10-37
10.3.5.3 Message Status Register (MSR).......................................................................... 10-38
10.3.6 Shared Message Signaled Registers ........................................................................ 10-38
10.3.6.1 Shared Message Signaled Interrupt Registers (MSIR0–MSIR7)........................ 10-39
10.3.6.2 Shared Message Signaled Interrupt Status Register (MSISR)............................. 10-39
10.3.6.3 Shared Message Signaled Interrupt Index Register (MSIIR)..............................10-40
10.3.6.4 Shared Message Signaled Interrupt Vector/Priority Register (MSIVPRs)..........10-40
10.3.6.5 Shared Message Signaled Interrupt Destination Registers 0–7 (MSIDRn)......... 10-41
10.3.7 Interrupt Source Configuration Registers................................................................ 10-42
10.3.7.1 External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ..................... 10-43
10.3.7.2 External Interrupt Destination Registers (EIDR0–EIDR11) ...............................10-44
10.3.7.3 Internal Interrupt Vector/Priority Registers (IIVPRn).........................................10-45
10.3.7.4 Internal Interrupt Destination Registers (IIDRn).................................................10-46
10.3.7.5 Messaging Interrupt Vector/Priority Registers (MIVPRn).................................. 10-47
10.3.7.6 Messaging Interrupt Destination Registers (MIDR0–MIDR7)........................... 10-48
10.3.8 Per-CPU (Private Access) Registers........................................................................ 10-49
10.3.8.1 Interprocessor Interrupt Dispatch Register (IPIDR0–IPIDR3) ........................... 10-50
10.3.8.2 Processor Core Current Task Priority Registers 0–1 (CTPR0–CTPR1) .............10-51
10.3.8.3 Who Am I Registers 0–1 (WHOAMI0–WHOAMI1).........................................10-52
10.3.8.4 Processor Core Interrupt Acknowledge Registers 0–1 (IACK0–IACK1)...........10-52
10.3.8.5 Processor Core End of Interrupt Registers (EOI0–EOI1) ...................................10-53
10.4 Functional Description................................................................................................. 10-54
10.4.1 Flow of Interrupt Control......................................................................................... 10-54
10.4.1.1 Interrupts Routed to cint or IRQ_OUT................................................................ 10-54
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10.4.1.2 Interrupts Routed to int........................................................................................ 10-54
10.4.1.2.1 Nesting of Interrupts........................................................................................ 10-56
10.4.1.2.2 Interrupt Source Priority.................................................................................. 10-56
10.4.1.2.3 Interrupt Acknowledge....................................................................................10-57
10.4.1.2.4 Spurious Vector Generation............................................................................. 10-57
10.4.2 Interprocessor Interrupts.......................................................................................... 10-57
10.4.3 Message Interrupts................................................................................................... 10-58
10.4.4 Shared Message Signaled Interrupts........................................................................ 10-58
10.4.5 PCI Express INTx.................................................................................................... 10-58
10.4.6 Global Timers .......................................................................................................... 10-59
10.4.7 Resets....................................................................................................................... 10-60
10.4.8 Resetting the PIC..................................................................................................... 10-60
10.4.8.1 Processor Core Initialization................................................................................ 10-60
10.5 Initialization/Application Information......................................................................... 10-60
10.5.1 Programming Guidelines......................................................................................... 10-60
10.5.1.1 PIC Registers....................................................................................................... 10-60
10.5.1.2 Changing Interrupt Source Configuration ........................................................... 10-62
Chapter 11
Security Engine (SEC) 3.0
11.1 Architecture Overview................................................................................................... 11-3
11.1.1 Descriptors................................................................................................................. 11-5
11.1.2 Polychannel................................................................................................................ 11-6
11.1.3 Controller................................................................................................................... 11-7
11.1.3.1 Channel-Controlled Access to EUs ....................................................................... 11-8
11.1.3.2 Host-Controlled Access to EUs............................................................................. 11-8
11.1.4 Execution Units (EUs)............................................................................................... 11-9
11.1.4.1 Common EU Interface........................................................................................... 11-9
11.1.4.2 Public Key Execution Unit (PKEU)...................................................................... 11-9
11.1.4.2.1 Elliptic Curve Operations.................................................................................. 11-9
11.1.4.2.2 Modular Exponentiation Operations ............................................................... 11-10
11.1.4.3 Data Encryption Standard Execution Unit (DEU)............................................... 11-10
11.1.4.4 Advanced Encryption Standard Execution Unit (AESU).....................................11-11
11.1.4.5 Arc Four Execution Unit (AFEU) ....................................................................... 11-12
11.1.4.6 Message Digest Execution Unit (MDEU)........................................................... 11-12
11.1.4.7 Kasumi Execution Unit (KEU)............................................................................ 11-12
11.1.4.8 Cyclical Redundancy Check Unit (CRCU)......................................................... 11-13
11.1.4.9 Random Number Generator (RNGU).................................................................. 11-13
11.2 Configuration of Internal Memory Space.................................................................... 11-13
11.3 Descriptor Overview.................................................................................................... 11-21
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11.3.1 Descriptor Structure................................................................................................. 11-22
11.3.2 Descriptor Format: Header Dword .......................................................................... 11-23
11.3.2.1 Selecting Execution Units—EU_SEL0 and EU_SEL1....................................... 11-25
11.3.2.2 Selecting Descriptor Type—DESC_TYPE ......................................................... 11-26
11.3.3 Descriptor Format: Pointer Dwords......................................................................... 11-27
11.3.4 Link Table Format ................................................................................................... 11-29
11.4 Descriptor Types .......................................................................................................... 11-32
11.5 Polychannel.................................................................................................................. 11-35
11.5.1 Arbitration Among Channels................................................................................... 11-36
11.5.1.1 Arbitration for Use of the Controller................................................................... 11-36
11.5.1.2 Arbitration for Use of Execution Units ............................................................... 11-36
11.5.1.3 Arbitration Algorithms ........................................................................................ 11-37
11.5.1.3.1 Round-Robin Arbitration................................................................................. 11-37
11.5.1.3.2 Priority Arbitration .......................................................................................... 11-37
11.5.2 Polychannel Registers.............................................................................................. 11-38
11.5.2.1 Traffic Counters................................................................................................... 11-38
11.5.2.1.1 Fetch FIFO Enqueue Counter.......................................................................... 11-38
11.5.2.1.2 Descriptor Finished Counter............................................................................ 11-38
11.5.2.1.3 Data Bytes In Counter ..................................................................................... 11-38
11.5.2.1.4 Data Bytes Out Counter................................................................................... 11-39
11.5.3 Channel Interrupts.................................................................................................... 11-39
11.5.3.1 Channel Done Interrupt ....................................................................................... 11-40
11.5.3.2 Channel Error Interrupt........................................................................................ 11-40
11.5.4 Channel Registers .................................................................................................... 11-40
11.5.4.1 Channel Configuration Register (CCR)............................................................... 11-41
11.5.4.2 Channel Status Register (CSR)............................................................................ 11-44
11.5.4.3 Current Descriptor Pointer Register (CDPR) ...................................................... 11-47
11.5.4.4 Fetch FIFO (FF)................................................................................................... 11-47
11.5.4.5 Descriptor Buffer (DB)........................................................................................ 11-48
11.5.4.6 Scatter and Gather Link Tables (SLT, GLT)........................................................ 11-48
11.6 Controller..................................................................................................................... 11-49
11.6.1 Bus Transfers ........................................................................................................... 11-49
11.6.1.1 System Bus Master Read..................................................................................... 11-50
11.6.1.2 System Bus Master Write .................................................................................... 11-51
11.6.2 Controller Interrupts ................................................................................................ 11-51
11.6.2.1 Controller Primary Interrupt................................................................................ 11-51
11.6.2.2 Controller Secondary Interrupt............................................................................ 11-52
11.6.3 Controller Registers................................................................................................. 11-52
11.6.3.1 EU Assignment Status Register (EUASR).......................................................... 11-52
11.6.3.2 Interrupt Enable Register (IER)........................................................................... 11-53
11.6.3.3 Interrupt Status Register (ISR) ............................................................................ 11-56
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11.6.3.4 Interrupt Clear Register (ICR)............................................................................. 11-57
11.6.3.5 ID Register........................................................................................................... 11-59
11.6.3.6 IP Block Revision Register.................................................................................. 11-59
11.6.3.7 Master Control Register (MCR).......................................................................... 11-60
11.6.4 Snooping by Caches................................................................................................. 11-61
11.7 Execution Units............................................................................................................ 11-62
11.7.1 Advanced Encryption Standard Execution Unit (AESU)........................................ 11-62
11.7.1.1 AESU Mode Register .......................................................................................... 11-63
11.7.1.2 AESU Key Size Register..................................................................................... 11-67
11.7.1.3 AESU Data Size Register.................................................................................... 11-68
11.7.1.4 AESU Reset Control Register ............................................................................. 11-68
11.7.1.5 AESU Status Register.......................................................................................... 11-70
11.7.1.6 AESU Interrupt Status Register........................................................................... 11-71
11.7.1.7 AESU Interrupt Mask Register............................................................................ 11-73
11.7.1.8 ICV Size Register ................................................................................................ 11-74
11.7.1.9 AESU ICV Size Register..................................................................................... 11-75
11.7.1.10 AESU End_of_Message Register........................................................................ 11-75
11.7.1.11 AESU Context Registers ..................................................................................... 11-75
11.7.1.11.1 Context for CBC, CBC-RBP, OFB, and CFB128 Cipher Modes.................... 11-76
11.7.1.11.2 Context for Counter Cipher Mode................................................................... 11-76
11.7.1.11.3 Context for SRT Cipher Mode......................................................................... 11-77
11.7.1.11.4 Context and Operation for XCBC-MAC Cipher Mode................................... 11-78
11.7.1.11.5 Context and Operation for CMAC (OMAC1) Cipher Mode .......................... 11-79
11.7.1.11.6 Context for CCM Cipher Mode....................................................................... 11-80
11.7.1.11.7 Context and Operation for GCM Cipher Mode............................................... 11-83
11.7.1.11.8 AESU Key Registers ....................................................................................... 11-92
11.7.1.11.9 AESU FIFOs.................................................................................................... 11-92
11.7.2 ARC Four Execution Unit (AFEU) ......................................................................... 11-92
11.7.2.1 AFEU Mode Register .......................................................................................... 11-93
11.7.2.2 AFEU Key Size Register..................................................................................... 11-94
11.7.2.3 AFEU Context/Data Size Register ...................................................................... 11-94
11.7.2.4 AFEU Reset Control Register ............................................................................. 11-95
11.7.2.5 AFEU Status Register.......................................................................................... 11-96
11.7.2.6 AFEU Interrupt Status Register........................................................................... 11-97
11.7.2.7 AFEU Interrupt Mask Register............................................................................ 11-98
11.7.2.8 AFEU End of Message Register........................................................................ 11-100
11.7.2.9 AFEU Context ................................................................................................... 11-100
11.7.2.9.1 Writing AFEU Context.................................................................................. 11-100
11.7.2.9.2 Reading AFEU Context................................................................................. 11-101
11.7.2.10 AFEU Key Registers ......................................................................................... 11-101
11.7.2.10.1 AFEU FIFOs.................................................................................................. 11-101
/
