NXP MPC8560ADS Reference guide

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Reference guide

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MPC8560 PowerQUICC III™
Integrated Communications
Processor Reference Manual
MPC8560RM
Rev. 1
07/2004
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© Freescale Semiconductor, Inc. 2004.
MPC8560RM
Rev. 1
07/2004
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I
III
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14
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1
2
3
4
IV
17
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II
5
6
7
Part I—Overview
Overview
Memory Map
Signal Descriptions
Reset, Clocking, and Initialization
Part II—e500 Core Complex and L2 Cache
e500 Core Complex Overview
e500 Register Summary
L2 Look-Aside Cache/SRAM
Part III—Memory and I/O Interfaces
e500 Coherency Module
DDR Memory Controller
Programmable Interrupt Controller
I
2
C Interface
Local Bus Controller
Three-Speed Ethernet Controllers
DMA Controller
PCI/PCI-X Bus Interface
RapidIO Interface
Part IV—Global Functions and Debug
Global Utilities
Performance Monitor
Debug Features and Watchpoint Facility
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IV
17
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Part I—Overview
Overview
Memory Map
Signal Descriptions
Reset, Clocking, and Initialization
Part II—e500 Core Complex and L2 Cache
e500 Core Complex Overview
e500 Register Summary
L2 Look-Aside Cache/SRAM
Part III—Memory and I/O Interfaces
e500 Coherency Module
DDR Memory Controller
Programmable Interrupt Controller
I
2
C Interface
Local Bus Controller
Three-Speed Ethernet Controllers
DMA Controller
PCI/PCI-X Bus Interface
RapidIO Interface
Part IV—Global Functions and Debug
Global Utilities
Performance Monitor
Debug Features and Watchpoint Facility
V
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A
GLO
REG
IND
CPM
Part V—CPM Features
Communications Processor Module Overview
CPM Interrupt Controller
Serial Interface with Time-Slot Assigner
CPM Multiplexing
Baud-Rate Generators (BRGs)
CPM Timers
SDMA Channels
Serial Communications Controllers (SCCs)
SCC UART Mode
SCC HDLC Mode
SCC BISYNC Mode
SCC Transparent Mode
SCC AppleTalk Mode
Multi-Channel Controllers (MCCs)
Fast Communications Controllers (FCCs)
ATM Controller
AAL1 Circuit Emulation Service
AAL2
Transmission Convergence Layer
Inverse Multiplexing for ATM (IMA)
CPM Ethernet Controller
FCC HDLC Controller
FCC Transparent Controller
Serial Peripheral Interface (SPI)
CPM I
2
C Controller
Parallel I/O Ports
Appendix A—Revision History
Glossary of Terms and Abbreviations
Register Index (Memory-Mapped Registers)
General Index
CPM Index
V
20
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24
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35
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A
GLO
REG
IND
CPM
Part V—CPM Features
Communications Processor Module Overview
CPM Interrupt Controller
Serial Interface with Time-Slot Assigner
CPM Multiplexing
Baud-Rate Generators (BRGs)
CPM Timers
SDMA Channels
Serial Communications Controllers (SCCs)
SCC UART Mode
SCC HDLC Mode
SCC BISYNC Mode
SCC Transparent Mode
SCC AppleTalk Mode
Multi-Channel Controllers (MCCs)
Fast Communications Controllers (FCCs)
ATM Controller
AAL1 Circuit Emulation Service
AAL2
Transmission Convergence Layer
Inverse Multiplexing for ATM (IMA)
CPM Ethernet Controller
FCC HDLC Controller
FCC Transparent Controller
Serial Peripheral Interface (SPI)
CPM I
2
C Controller
Parallel I/O Ports
Appendix A—Revision History
Glossary of Terms and Abbreviations
Register Index (Memory-Mapped Registers)
General Index
CPM Index
MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual, Rev. 1
Freescale Semiconductor vii
Contents
Paragraph
Number Title
Page
Number
Contents
About This Book
Audience........................................................................................................................cxvii
Organization...................................................................................................................cxvii
Suggested Reading.........................................................................................................cxxii
General Information...............................................................................................cxxii
Related Documentation .........................................................................................cxxii
Conventions................................................................................................................. cxxiii
Signal Conventions.......................................................................................................cxxiv
Acronyms and Abbreviations .......................................................................................cxxiv
Part I
Overview
Chapter 1
Overview
1.1 Introduction...................................................................................................................... 1-1
1.2 MPC8560 Overview ........................................................................................................ 1-1
1.2.1 Key Features................................................................................................................ 1-2
1.3 MPC8560 Architecture Overview ................................................................................... 1-9
1.3.1 e500 Core Overview.................................................................................................... 1-9
1.3.2 Communications Processor Module (CPM).............................................................. 1-14
1.3.3 On-Chip Memory Unit............................................................................................... 1-15
1.3.3.1 On-Chip Memory as Memory-Mapped SRAM..................................................... 1-16
1.3.3.2 On-Chip Memory as L2 Cache.............................................................................. 1-16
1.3.4 e500 Coherency Module (ECM)................................................................................ 1-17
1.3.5 DDR SDRAM Controller .......................................................................................... 1-17
1.3.6 Programmable Interrupt Controller (PIC).................................................................. 1-18
1.3.7 I
2
C Controller ............................................................................................................ 1-18
1.3.8 Boot Sequencer.......................................................................................................... 1-19
1.3.9 Local Bus Controller (LBC)...................................................................................... 1-19
1.3.10 Three-Speed Ethernet Controllers (10/100/1Gb)....................................................... 1-20
1.3.11 Integrated DMA......................................................................................................... 1-20
1.3.12 PCI Controller............................................................................................................1-20
1.3.13 RapidIO Controller....................................................................................................1-21
1.3.13.1 RapidIO Message Unit .......................................................................................... 1-21
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Contents
Paragraph
Number Title
Page
Number
1.3.14 Power Management ................................................................................................... 1-21
1.3.15 Clocking..................................................................................................................... 1-22
1.3.16 Address Map.............................................................................................................. 1-22
1.3.17 OCeaN Switch Fabric................................................................................................ 1-22
1.4 Data Processing Overview............................................................................................. 1-23
1.4.1 Processing Between the CPM and Local Bus............................................................ 1-23
1.4.2 Processing Across the On-Chip Fabric......................................................................1-24
1.4.3 Data Processing with the e500 Coherency Module................................................... 1-25
1.5 MPC8560 Application Examples .................................................................................. 1-25
1.5.1 Device Configurations............................................................................................... 1-26
1.5.1.1 Single-Processor System ....................................................................................... 1-26
1.5.1.2 Multiprocessor System .......................................................................................... 1-27
1.5.1.3 High-Performance System..................................................................................... 1-28
1.5.2 Examples of Communications Systems..................................................................... 1-28
1.5.2.1 Remote Access Server........................................................................................... 1-29
1.5.2.2 Regional Office Router.......................................................................................... 1-30
1.5.2.3 LAN-to-WAN Bridge Router ................................................................................ 1-31
1.5.2.4 Cellular Base Station ............................................................................................. 1-32
1.5.2.5 3G Wireless Base Station ...................................................................................... 1-33
1.5.2.6 Telecommunications Switch Controller ................................................................ 1-34
1.5.2.7 SONET Transmission Controller...........................................................................1-35
1.5.2.8 Frame Relay Card..................................................................................................1-36
1.5.2.9 ATM Protocol Converter ....................................................................................... 1-36
1.6 Compatibility Issues ...................................................................................................... 1-37
1.6.1 Software..................................................................................................................... 1-37
1.6.2 MPC8560 Hardware.................................................................................................. 1-37
1.6.3 Differences Between MPC8560 and MPC8260........................................................ 1-37
1.6.4 Communications Protocol Table................................................................................ 1-38
1.6.5 MPC8560 Configurations.......................................................................................... 1-38
1.6.6 Pin Configurations..................................................................................................... 1-38
1.6.7 Communications Performance................................................................................... 1-38
Chapter 2
Memory Map
2.1 Local Memory Map Overview and Example .................................................................. 2-1
2.2 Address Translation and Mapping................................................................................... 2-3
2.2.1 SRAM Windows.......................................................................................................... 2-4
2.2.2 Window into Configuration Space...............................................................................2-4
2.2.3 Local Access Windows................................................................................................ 2-4
MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual, Rev. 1
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Contents
Paragraph
Number Title
Page
Number
2.2.3.1 Local Access Register Memory Map ...................................................................... 2-5
2.2.3.2 Local Access Window n Base Address Registers
(LAWBAR0–LAWBAR7)................................................................................... 2-6
2.2.3.3 Local Access Window n Attributes Registers
(LAWAR0–LAWAR7)......................................................................................... 2-6
2.2.3.4 Precedence of Local Access Windows.................................................................... 2-7
2.2.3.5 Configuring Local Access Windows.......................................................................2-7
2.2.3.6 Distinguishing Local Access Windows from Other Mapping Functions................ 2-8
2.2.3.7 Illegal Interaction Between Local Access Windows and DDR
SDRAM Chip Selects.......................................................................................... 2-8
2.2.4 Outbound Address Translation and Mapping Windows..............................................2-8
2.2.5 Inbound Address Translation and Mapping Windows ................................................ 2-9
2.2.5.1 RapidIO Inbound ATMU......................................................................................... 2-9
2.2.5.2 PCI/PCI-X Inbound ATMU..................................................................................... 2-9
2.2.5.3 Illegal Interaction Between Inbound ATMUs and Local Access
Windows.............................................................................................................. 2-9
2.3 Configuration, Control, and Status Register Map.......................................................... 2-10
2.3.1 Accessing CCSR Memory from External Masters.................................................... 2-11
2.3.2 Organization of CCSR Memory ................................................................................ 2-11
2.3.3 General Utilities Registers.........................................................................................2-13
2.3.4 Interrupt Controller and CCSR.................................................................................. 2-14
2.3.5 Communications Processor Module and CCSR........................................................ 2-15
2.3.6 RapidIO and CCSR.................................................................................................... 2-15
2.3.7 Device-Specific Utilities............................................................................................2-16
2.4 Complete CCSR Map .................................................................................................... 2-17
Chapter 3
Signal Descriptions
3.1 Signals Overview.............................................................................................................3-1
3.2 Configuration Signals Sampled at Reset .......................................................................3-14
3.3 Output Signal States During Reset ................................................................................ 3-16
Chapter 4
Reset, Clocking, and Initialization
4.1 Overview.......................................................................................................................... 4-1
4.2 External Signal Descriptions ........................................................................................... 4-1
4.2.1 System Control Signals................................................................................................ 4-2
4.2.2 Clock Signals............................................................................................................... 4-3
MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual, Rev. 1
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Contents
Paragraph
Number Title
Page
Number
4.3 Memory Map/Register Definition ................................................................................... 4-3
4.3.1 Local Configuration Control........................................................................................4-3
4.3.1.1 Accessing Configuration, Control, and Status Registers......................................... 4-4
4.3.1.1.1 Updating CCSRBAR........................................................................................... 4-4
4.3.1.1.2 Configuration, Control, and Status Base Address Register
(CCSRBAR)....................................................................................................4-5
4.3.1.2 Accessing Alternate Configuration Space............................................................... 4-5
4.3.1.2.1 Alternate Configuration Base Address Register (ALTCBAR)............................ 4-6
4.3.1.2.2 Alternate Configuration Attribute Register (ALTCAR)...................................... 4-6
4.3.1.3 Boot Page Translation.............................................................................................. 4-7
4.3.1.3.1 Boot Page Translation Register (BPTR)..............................................................4-8
4.3.2 Boot Sequencer............................................................................................................ 4-8
4.4 Functional Description..................................................................................................... 4-8
4.4.1 Reset Operations.......................................................................................................... 4-8
4.4.1.1 Soft Reset................................................................................................................. 4-9
4.4.1.2 Hard Reset ...............................................................................................................4-9
4.4.2 Power-On Reset Sequence........................................................................................... 4-9
4.4.3 Power-On Reset Configuration.................................................................................. 4-11
4.4.3.1 System PLL Ratio.................................................................................................. 4-12
4.4.3.2 e500 Core PLL Ratio............................................................................................. 4-13
4.4.3.3 Boot ROM Location.............................................................................................. 4-14
4.4.3.4 Host/Agent Configuration ..................................................................................... 4-14
4.4.3.5 CPU Boot Configuration .......................................................................................4-15
4.4.3.6 Boot Sequencer Configuration ..............................................................................4-16
4.4.3.7 TSEC Width........................................................................................................... 4-16
4.4.3.8 TSEC1 Protocol..................................................................................................... 4-17
4.4.3.9 TSEC2 Protocol..................................................................................................... 4-17
4.4.3.10 RapidIO Transmit Clock Source............................................................................ 4-17
4.4.3.11 RapidIO Device ID................................................................................................4-18
4.4.3.12 PCI Width Configuration....................................................................................... 4-18
4.4.3.13 PCI I/O Impedance ................................................................................................ 4-19
4.4.3.14 PCI Arbiter Configuration..................................................................................... 4-19
4.4.3.15 PCI Debug Configuration...................................................................................... 4-19
4.4.3.16 PCI-X Configuration ............................................................................................. 4-20
4.4.3.17 Memory Debug Configuration .............................................................................. 4-20
4.4.3.18 DDR Debug Configuration.................................................................................... 4-20
4.4.3.19 PCI/PCI-X Output Hold Configuration................................................................. 4-21
4.4.3.20 Local Bus Output Hold Configuration .................................................................. 4-22
4.4.3.21 General-Purpose POR Configuration.................................................................... 4-22
4.4.4 Clocking..................................................................................................................... 4-22
MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual, Rev. 1
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Contents
Paragraph
Number Title
Page
Number
4.4.4.1 System Clock/PCI Clock....................................................................................... 4-23
4.4.4.2 RapidIO Clocks ..................................................................................................... 4-23
4.4.4.3 Ethernet Clocks...................................................................................................... 4-24
4.4.4.4 Real Time Clock.................................................................................................... 4-24
Part II
e500 Core Complex and L2 Cache
Chapter 5
Core Complex Overview
5.1 Overview.......................................................................................................................... 5-1
5.1.1 Upward Compatibility ................................................................................................. 5-3
5.1.2 Core Complex Summary ............................................................................................. 5-3
5.2 e500 Processor and System Version Numbers................................................................. 5-4
5.3 Features............................................................................................................................5-5
5.4 Instruction Set................................................................................................................ 5-11
5.5 Instruction Flow.............................................................................................................5-13
5.5.1 Initial Instruction Fetch.............................................................................................. 5-14
5.5.2 Branch Detection and Prediction............................................................................... 5-14
5.5.3 e500 Execution Pipeline ............................................................................................ 5-14
5.6 Programming Model...................................................................................................... 5-17
5.7 On-Chip Cache Implementation.................................................................................... 5-19
5.8 Interrupts and Exception Handling................................................................................ 5-19
5.8.1 Exception Handling ................................................................................................... 5-19
5.8.2 Interrupt Classes ........................................................................................................ 5-20
5.8.3 Interrupt Types........................................................................................................... 5-20
5.8.4 Upper Bound on Interrupt Latencies .........................................................................5-21
5.8.5 Interrupt Registers...................................................................................................... 5-21
5.9 Memory Management.................................................................................................... 5-23
5.9.1 Address Translation................................................................................................... 5-25
5.9.2 MMU Assist Registers (MAS1–MAS4 and MAS6)................................................. 5-26
5.9.3 Process ID Registers (PID0–PID2)............................................................................ 5-26
5.9.4 TLB Coherency.......................................................................................................... 5-26
5.10 Memory Coherency .......................................................................................................5-27
5.10.1 Atomic Update Memory References ......................................................................... 5-27
5.10.2 Memory Access Ordering..........................................................................................5-27
5.10.3 Cache Control Instructions ........................................................................................ 5-27
5.10.4 Programmable Page Characteristics .......................................................................... 5-28
5.11 Core Complex Bus (CCB)............................................................................................. 5-28
5.12 Performance Monitoring................................................................................................ 5-28
MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual, Rev. 1
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Contents
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Number Title
Page
Number
5.12.1 Global Control Register............................................................................................. 5-29
5.12.2 Performance Monitor Counter Registers................................................................... 5-29
5.12.3 Local Control Registers............................................................................................. 5-29
5.13 Legacy Support of PowerPC Architecture..................................................................... 5-30
5.13.1 Instruction Set Compatibility..................................................................................... 5-30
5.13.1.1 User Instruction Set ............................................................................................... 5-30
5.13.1.2 Supervisor Instruction Set...................................................................................... 5-30
5.13.2 Memory Subsystem ................................................................................................... 5-31
5.13.3 Exception Handling ................................................................................................... 5-31
5.13.4 Memory Management................................................................................................ 5-31
5.13.5 Reset........................................................................................................................... 5-31
5.13.6 Little-Endian Mode....................................................................................................5-32
5.14 PowerQUICC III Implementation Details..................................................................... 5-32
Chapter 6
Core Register Summary
6.1 Overview.......................................................................................................................... 6-1
6.1.1 Register Set.................................................................................................................. 6-1
6.2 Register Model for 32-Bit Implementations.................................................................... 6-3
6.2.1 Special-Purpose Registers (SPRs)...............................................................................6-4
6.3 Registers for Computational Operations..........................................................................6-7
6.3.1 General-Purpose Registers (GPRs).............................................................................. 6-8
6.3.2 Integer Exception Register (XER)...............................................................................6-8
6.4 Registers for Branch Operations...................................................................................... 6-8
6.4.1 Condition Register (CR).............................................................................................. 6-9
6.4.2 Link Register (LR)..................................................................................................... 6-10
6.4.3 Count Register (CTR)................................................................................................ 6-11
6.5 Processor Control Registers........................................................................................... 6-11
6.5.1 Machine State Register (MSR).................................................................................. 6-11
6.5.2 Processor ID Register (PIR) ...................................................................................... 6-13
6.5.3 Processor Version Register (PVR)............................................................................. 6-13
6.5.4 System Version Register (SVR)................................................................................. 6-14
6.6 Timer Registers..............................................................................................................6-14
6.6.1 Timer Control Register (TCR)................................................................................... 6-14
6.6.2 Timer Status Register (TSR)...................................................................................... 6-15
6.6.3 Time Base Registers .................................................................................................. 6-16
6.6.4 Decrementer Register ................................................................................................ 6-16
6.6.5 Decrementer Auto-Reload Register (DECAR).......................................................... 6-16
6.7 Interrupt Registers..........................................................................................................6-17
MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual, Rev. 1
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6.7.1 Interrupt Registers Defined by Book E...................................................................... 6-17
6.7.1.1 Save/Restore Register 0 (SRR0)............................................................................ 6-17
6.7.1.2 Save/Restore Register 1 (SRR1)............................................................................ 6-17
6.7.1.3 Critical Save/Restore Register 0 (CSRR0)............................................................ 6-17
6.7.1.4 Critical Save/Restore Register 1 (CSRR1)............................................................ 6-18
6.7.1.5 Data Exception Address Register (DEAR)............................................................ 6-18
6.7.1.6 Interrupt Vector Prefix Register (IVPR)................................................................ 6-18
6.7.1.7 Interrupt Vector Offset Registers (IVORn)............................................................ 6-18
6.7.1.8 Exception Syndrome Register (ESR) ....................................................................6-19
6.7.2 EIS-Defined Interrupt Registers ................................................................................ 6-20
6.7.2.1 Machine Check Save/Restore Register 0 (MCSRR0)........................................... 6-20
6.7.2.2 Machine Check Save/Restore Register 1 (MCSRR1)........................................... 6-21
6.7.2.3 Machine Check Address Register (MCAR).......................................................... 6-21
6.7.2.4 Machine Check Syndrome Register (MCSR)........................................................ 6-21
6.8 Software-Use SPRs (SPRG0–SPRG7 and USPRG0) ................................................... 6-23
6.9 Branch Target Buffer (BTB) Registers..........................................................................6-23
6.9.1 Branch Buffer Entry Address Register (BBEAR)..................................................... 6-23
6.9.2 Branch Buffer Target Address Register (BBTAR) .................................................... 6-24
6.9.3 Branch Unit Control and Status Register (BUCSR).................................................. 6-24
6.10 Hardware Implementation-Dependent Registers........................................................... 6-25
6.10.1 Hardware Implementation-Dependent Register 0 (HID0)......................................... 6-25
6.10.2 Hardware Implementation-Dependent Register 1 (HID1)......................................... 6-26
6.11 L1 Cache Configuration Registers................................................................................. 6-28
6.11.1 L1 Cache Control and Status Register 0 (L1CSR0)..................................................6-28
6.11.2 L1 Cache Control and Status Register 1 (L1CSR1)..................................................6-29
6.11.3 L1 Cache Configuration Register 0 (L1CFG0) .........................................................6-30
6.11.4 L1 Cache Configuration Register 1 (L1CFG1) .........................................................6-31
6.12 MMU Registers.............................................................................................................. 6-32
6.12.1 Process ID Registers (PID0–PID2)............................................................................ 6-32
6.12.2 MMU Control and Status Register 0 (MMUCSR0).................................................. 6-32
6.12.3 MMU Configuration Register (MMUCFG).............................................................. 6-32
6.12.4 TLB Configuration Registers (TLBnCFG)................................................................ 6-33
6.12.4.1 TLB0 Configuration Register 0 (TLB0CFG)........................................................ 6-33
6.12.4.2 TLB1 Configuration Register 1 (TLB1CFG)........................................................ 6-34
6.12.5 MMU Assist Registers............................................................................................... 6-35
6.12.5.1 MAS Register 0 (MAS0)....................................................................................... 6-35
6.12.5.2 MAS Register 1 (MAS1)....................................................................................... 6-35
6.12.5.3 MAS Register 2 (MAS2)....................................................................................... 6-36
6.12.5.4 MAS Register 3 (MAS3)....................................................................................... 6-37
6.12.5.5 MAS Register 4 (MAS4)....................................................................................... 6-38
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6.12.5.6 MAS Register 6 (MAS6)....................................................................................... 6-39
6.13 Debug Registers.............................................................................................................6-39
6.13.1 Debug Control Registers (DBCR0–DBCR2)............................................................ 6-39
6.13.1.1 Debug Control Register 0 (DBCR0)...................................................................... 6-39
6.13.1.2 Debug Control Register 1 (DBCR1)...................................................................... 6-41
6.13.1.3 Debug Control Register 2 (DBCR2)...................................................................... 6-42
6.13.2 Debug Status Register (DBSR).................................................................................. 6-43
6.13.3 Instruction Address Compare Registers (IAC1–IAC2)............................................. 6-44
6.13.4 Data Address Compare Registers (DAC1–DAC2).................................................... 6-45
6.14 Signal Processing and Embedded Floating-Point Status and
Control Register (SPEFSCR) .................................................................................... 6-45
6.14.1 Accumulator (ACC)................................................................................................... 6-47
6.15 Performance Monitor Registers (PMRs) ....................................................................... 6-48
6.15.1 Global Control Register 0 (PMGC0, UPMGC0)....................................................... 6-49
6.15.2 Local Control A Registers
(PMLCa0–PMLCa3, UPMLCa0–UPMLCa3)...................................................... 6-49
6.15.3 Local Control B Registers
(PMLCb0–PMLCb3, UPMLCb0–UPMLCb3)..................................................... 6-50
6.15.4 Performance Monitor Counter Registers
(PMC0–PMC3, UPMC0–UPMC3)....................................................................... 6-51
Chapter 7
L2 Look-Aside Cache/SRAM
7.1 L2 Cache Overview ......................................................................................................... 7-1
7.1.1 L2 Cache and SRAM Features .................................................................................... 7-2
7.2 Cache Organization.......................................................................................................... 7-3
7.3 Memory Map/Register Definition ................................................................................... 7-6
7.3.1 L2/SRAM Register Descriptions................................................................................. 7-7
7.3.1.1 L2 Control Register (L2CTL).................................................................................. 7-7
7.3.1.2 L2 Cache External Write Address Registers 0–3 (L2CEWARn) .......................... 7-10
7.3.1.3 L2 Cache External Write Control Registers 0–3 (L2CEWCRn)........................... 7-11
7.3.1.4 L2 Memory-Mapped SRAM Base Address Registers 0–1
(L2SRBARn)..................................................................................................... 7-12
7.3.1.5 L2 Error Registers.................................................................................................. 7-13
7.3.1.5.1 Error Injection Registers.................................................................................... 7-13
7.3.1.5.2 Error Control and Capture Registers ................................................................. 7-15
7.4 External Writes to the L2 Cache (Cache Stashing)........................................................ 7-21
7.5 L2 Cache Timing ........................................................................................................... 7-22
7.6 L2 Cache and SRAM Coherency................................................................................... 7-23
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7.6.1 L2 Cache Coherency Rules........................................................................................ 7-23
7.6.2 Memory-Mapped SRAM Coherency Rules .............................................................. 7-24
7.7 L2 Cache Locking.......................................................................................................... 7-24
7.7.1 Locking the Entire L2 Cache..................................................................................... 7-25
7.7.2 Locking Programmed Memory Ranges..................................................................... 7-25
7.7.3 Locking Selected Lines.............................................................................................. 7-25
7.7.4 Clearing Locks on Selected Lines ............................................................................. 7-26
7.7.5 Flash Clearing of Instruction and Data Locks........................................................... 7-27
7.7.6 Locks with Stale Data................................................................................................ 7-27
7.8 PLRU L2 Replacement Policy.......................................................................................7-27
7.8.1 PLRU Bit Update Considerations..............................................................................7-28
7.8.2 Allocation of Lines ....................................................................................................7-29
7.9 L2 Cache Operation....................................................................................................... 7-29
7.9.1 L2 Cache States ......................................................................................................... 7-29
7.9.2 Flash Invalidation of the L2 Cache............................................................................ 7-30
7.9.3 L2 State Transitions................................................................................................... 7-30
7.10 Initialization/Application Information........................................................................... 7-34
7.10.1 Initialization............................................................................................................... 7-35
7.10.1.1 L2 Cache Initialization .......................................................................................... 7-35
7.10.1.2 Memory-Mapped SRAM Initialization ................................................................. 7-35
7.10.2 Managing Errors........................................................................................................ 7-35
7.10.2.1 ECC Errors............................................................................................................. 7-35
7.10.2.2 Tag Parity Errors....................................................................................................7-36
Part III
Memory and I/O Interfaces
Chapter 8
e500 Coherency Module
8.1 Introduction...................................................................................................................... 8-1
8.1.1 Overview...................................................................................................................... 8-1
8.1.2 Features........................................................................................................................ 8-2
8.2 Memory Map/Register Definition ................................................................................... 8-3
8.2.1 Register Descriptions................................................................................................... 8-3
8.2.1.1 ECM CCB Address Configuration Register (EEBACR) ........................................ 8-3
8.2.1.2 ECM CCB Port Configuration Register (EEBPCR) ............................................... 8-4
8.2.1.3 ECM Error Detect Register (EEDR) ....................................................................... 8-5
8.2.1.4 ECM Error Enable Register (EEER).......................................................................8-6
8.2.1.5 ECM Error Attributes Capture Register (EEATR).................................................. 8-7
8.2.1.6 ECM Error Address Capture Register (EEADR).................................................... 8-8
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8.3 Functional Description..................................................................................................... 8-9
8.3.1 I/O Arbiter.................................................................................................................... 8-9
8.3.2 CCB Arbiter.................................................................................................................8-9
8.3.3 Transaction Queue....................................................................................................... 8-9
8.3.4 Global Data Multiplexor............................................................................................ 8-10
8.3.5 CCB Interface............................................................................................................ 8-10
8.4 Initialization/Application Information........................................................................... 8-10
Chapter 9
DDR Memory Controller
9.1 Introduction...................................................................................................................... 9-1
9.2 Features............................................................................................................................9-2
9.2.1 Modes of Operation..................................................................................................... 9-3
9.3 External Signal Descriptions ........................................................................................... 9-3
9.3.1 Signals Overview......................................................................................................... 9-3
9.3.2 Detailed Signal Descriptions ....................................................................................... 9-5
9.3.2.1 Memory Interface Signals........................................................................................ 9-5
9.3.2.2 Clock Interface Signals............................................................................................ 9-8
9.3.2.3 Debug Signals.......................................................................................................... 9-8
9.4 Memory Map/Register Definition ................................................................................... 9-9
9.4.1 Register Descriptions................................................................................................... 9-9
9.4.1.1 Chip Select Memory Bounds (CSn_BNDS).......................................................... 9-10
9.4.1.2 Chip Select Configuration (CSn_CONFIG).......................................................... 9-10
9.4.1.3 DDR SDRAM Timing Configuration 1 (TIMING_CFG_1)................................. 9-11
9.4.1.4 DDR SDRAM Timing Configuration 2 (TIMING_CFG_2)................................. 9-13
9.4.1.5 DDR SDRAM Control Configuration (DDR_SDRAM_CFG)............................. 9-14
9.4.1.6 DDR SDRAM Mode Configuration (DDR_SDRAM_MODE)............................ 9-16
9.4.1.7 DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) ................. 9-16
9.4.1.8 Memory Data Path Error Injection Mask High
(DATA_ERR_INJECT_HI)............................................................................... 9-17
9.4.1.9 Memory Data Path Error Injection Mask Low
(DATA_ERR_INJECT_LO).............................................................................. 9-18
9.4.1.10 Memory Data Path Error Injection Mask ECC
(ECC_ERR_INJECT)........................................................................................ 9-18
9.4.1.11 Memory Data Path Read Capture High (CAPTURE_DATA_HI)......................... 9-19
9.4.1.12 Memory Data Path Read Capture Low (CAPTURE_DATA_LO) ........................ 9-20
9.4.1.13 Memory Data Path Read Capture ECC (CAPTURE_ECC).................................. 9-20
9.4.1.14 Memory Error Detect (ERR_DETECT)................................................................ 9-21
9.4.1.15 Memory Error Disable (ERR_DISABLE)............................................................. 9-21
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9.4.1.16 Memory Error Interrupt Enable (ERR_INT_EN).................................................. 9-22
9.4.1.17 Memory Error Attributes Capture (CAPTURE_ATTRIBUTES)..........................9-23
9.4.1.18 Memory Error Address Capture (CAPTURE_ADDRESS) .................................. 9-24
9.4.1.19 Single-Bit ECC Memory Error Management (ERR_SBE)................................... 9-25
9.5 Functional Description................................................................................................... 9-25
9.5.1 DDR SDRAM Interface Operation............................................................................ 9-30
9.5.1.1 Supported DDR SDRAM Organizations............................................................... 9-31
9.5.2 DDR SDRAM Address Multiplexing........................................................................9-31
9.5.3 JEDEC Standard DDR SDRAM Interface Commands............................................. 9-32
9.5.4 SDRAM Interface Timing ......................................................................................... 9-34
9.5.4.1 Clock Distribution .................................................................................................9-37
9.5.5 DDR SDRAM Mode-Set Command Timing............................................................. 9-38
9.5.6 DDR SDRAM Registered DIMM Mode................................................................... 9-39
9.5.7 DDR SDRAM Write Timing Adjustments................................................................ 9-39
9.5.8 DDR SDRAM Refresh .............................................................................................. 9-40
9.5.8.1 DDR SDRAM Refresh Timing..............................................................................9-41
9.5.8.2 DDR SDRAM Refresh and Power-Saving Modes................................................ 9-42
9.5.8.2.1 Self-Refresh in Sleep Mode............................................................................... 9-43
9.5.9 DDR Data Beat Ordering........................................................................................... 9-44
9.5.10 Page Mode and Logical Bank Retention ...................................................................9-44
9.5.11 Error Checking and Correcting (ECC) ...................................................................... 9-45
9.5.12 Error Management..................................................................................................... 9-47
9.6 Initialization/Application Information........................................................................... 9-48
9.6.1 DDR SDRAM Initialization Sequence...................................................................... 9-49
Chapter 10
Programmable Interrupt Controller
10.1 Introduction.................................................................................................................... 10-1
10.1.1 Overview.................................................................................................................... 10-2
10.1.2 Features...................................................................................................................... 10-3
10.1.3 Interrupts to the Processor Core................................................................................. 10-4
10.1.4 Modes of Operation................................................................................................... 10-5
10.1.4.1 Mixed Mode (GCR[M] = 1)..................................................................................10-5
10.1.4.2 Pass-Through Mode (GCR[M] = 0) ...................................................................... 10-6
10.1.5 Interrupt Sources........................................................................................................ 10-6
10.1.5.1 Interrupt Routing—Mixed Mode........................................................................... 10-7
10.1.5.2 Internal Interrupt Sources ...................................................................................... 10-7
10.2 External Signal Descriptions ......................................................................................... 10-8
10.2.1 Signal Overview ........................................................................................................ 10-8
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10.2.2 Detailed Signal Descriptions ..................................................................................... 10-8
10.3 Memory Map/Register Definition ................................................................................. 10-9
10.3.1 Global Registers.......................................................................................................10-16
10.3.1.1 Feature Reporting Register (FRR)....................................................................... 10-16
10.3.1.2 Global Configuration Register (GCR)................................................................. 10-17
10.3.1.3 Vendor Identification Register (VIR) .................................................................. 10-17
10.3.1.4 Processor Initialization Register (PIR)................................................................10-18
10.3.1.5 IPI Vector/Priority Registers (IPIVPRn) .............................................................10-19
10.3.1.6 Spurious Vector Register (SVR)..........................................................................10-19
10.3.2 Global Timer Registers............................................................................................ 10-20
10.3.2.1 Timer Frequency Reporting Register (TFRR)..................................................... 10-20
10.3.2.2 Global Timer Current Count Registers (GTCCRn)............................................. 10-21
10.3.2.3 Global Timer Base Count Registers (GTBCRn) ................................................. 10-21
10.3.2.4 Global Timer Vector/Priority Registers (GTVPRn) ............................................ 10-22
10.3.2.5 Global Timer Destination Registers (GTDRn).................................................... 10-23
10.3.2.6 Timer Control Register (TCR)............................................................................. 10-23
10.3.3 IRQ_OUT
and Critical Interrupt Summary Registers............................................. 10-26
10.3.3.1 IRQ_OUT
Summary Register 0 (IRQSR0)......................................................... 10-26
10.3.3.2 IRQ_OUT
Summary Register 1 (IRQSR1)......................................................... 10-27
10.3.3.3 Critical Interrupt Summary Register 0 (CISR0).................................................. 10-27
10.3.3.4 Critical Interrupt Summary Register 1 (CISR1).................................................. 10-28
10.3.4 Performance Monitor Mask Registers (PMMRs).................................................... 10-28
10.3.4.1 Performance Monitor Mask Register (Lower) (PMnMR0)................................. 10-29
10.3.4.2 Performance Monitor Mask Registers (Upper) (PMnMR1)................................ 10-29
10.3.5 Message Registers.................................................................................................... 10-30
10.3.5.1 Message Registers (MSGR0–MSGR3)............................................................... 10-30
10.3.5.2 Message Enable Register (MER)......................................................................... 10-30
10.3.5.3 Message Status Register (MSR).......................................................................... 10-31
10.3.6 Interrupt Source Configuration Registers................................................................ 10-32
10.3.6.1 External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11) ..................... 10-32
10.3.6.2 External Interrupt Destination Registers (EIDR0–EIDR11)............................... 10-33
10.3.6.3 Internal Interrupt Vector/Priority Registers (IIVPR0–IIVPR31)......................... 10-34
10.3.6.4 Internal Interrupt Destination Registers (IIDR0–IIDR31) .................................. 10-35
10.3.6.5 Messaging Interrupt Vector/Priority Registers (MIVPR0–MIVPR3) ................. 10-36
10.3.6.6 Messaging Interrupt Destination Registers (MIDR0–MIDR3)........................... 10-37
10.3.7 Per-CPU Registers................................................................................................... 10-38
10.3.7.1 Interprocessor Interrupt Dispatch Register (IPIDR0–IPIDR3) ........................... 10-39
10.3.7.2 Processor Current Task Priority Register (CTPR)............................................... 10-40
10.3.7.3 Who Am I Register (WHOAMI)......................................................................... 10-41
10.3.7.4 Processor Interrupt Acknowledge Register (IACK)............................................ 10-41
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10.3.7.5 Processor End of Interrupt Register (EOI) .......................................................... 10-42
10.4 Functional Description................................................................................................. 10-43
10.4.1 Flow of Interrupt Control......................................................................................... 10-43
10.4.1.1 Interrupt Source Priority...................................................................................... 10-45
10.4.1.2 Processor Current Task Priority........................................................................... 10-45
10.4.1.3 Interrupt Acknowledge........................................................................................10-46
10.4.2 Nesting of Interrupts................................................................................................ 10-46
10.4.3 Processor Initialization ............................................................................................ 10-46
10.4.4 Spurious Vector Generation..................................................................................... 10-46
10.4.5 Messaging Interrupts................................................................................................ 10-47
10.4.6 Global Timers ..........................................................................................................10-47
10.4.7 Reset of the PIC....................................................................................................... 10-47
10.5 Initialization/Application Information......................................................................... 10-48
10.5.1 Programming Guidelines.........................................................................................10-48
10.5.1.1 PIC Registers....................................................................................................... 10-48
10.5.1.2 Changing Interrupt Source Configuration........................................................... 10-49
Chapter 11
I
2
C Interface
11.1 Introduction.................................................................................................................... 11-1
11.1.1 Overview.................................................................................................................... 11-2
11.1.2 Features...................................................................................................................... 11-2
11.1.3 Modes of Operation................................................................................................... 11-2
11.2 External Signal Descriptions ......................................................................................... 11-3
11.2.1 Signal Overview ........................................................................................................ 11-3
11.2.2 Detailed Signal Descriptions ..................................................................................... 11-3
11.3 Memory Map/Register Definition ................................................................................. 11-4
11.3.1 Register Descriptions................................................................................................. 11-4
11.3.1.1 I
2
C Address Register (I2CADR)........................................................................... 11-5
11.3.1.2 I
2
C Frequency Divider Register (I2CFDR)........................................................... 11-5
11.3.1.3 I
2
C Control Register (I2CCR)............................................................................... 11-6
11.3.1.4 I
2
C Status Register (I2CSR).................................................................................. 11-7
11.3.1.5 I
2
C Data Register (I2CDR).................................................................................... 11-9
11.3.1.6 Digital Filter Sampling Rate Register (I2CDFSRR)........................................... 11-10
11.4 Functional Description................................................................................................. 11-10
11.4.1 Transaction Protocol................................................................................................ 11-10
11.4.1.1 START Condition .................................................................................................11-11
11.4.1.2 Slave Address Transmission.................................................................................11-11
11.4.1.3 Repeated START Condition ................................................................................ 11-12
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11.4.1.4 STOP Condition................................................................................................... 11-12
11.4.1.5 Protocol Implementation Details......................................................................... 11-13
11.4.1.5.1 Transaction Monitoring—Implementation Details.......................................... 11-13
11.4.1.5.2 Control Transfer—Implementation Details..................................................... 11-13
11.4.1.6 Address Compare—Implementation Details....................................................... 11-14
11.4.2 Arbitration Procedure .............................................................................................. 11-14
11.4.2.1 Arbitration Control .............................................................................................. 11-15
11.4.3 Handshaking ............................................................................................................ 11-15
11.4.4 Clock Control........................................................................................................... 11-15
11.4.4.1 Clock Synchronization......................................................................................... 11-16
11.4.4.2 Input Synchronization and Digital Filter............................................................. 11-16
11.4.4.2.1 Input Signal Synchronization .......................................................................... 11-16
11.4.4.2.2 Filtering of SCL and SDA Lines..................................................................... 11-16
11.4.4.3 Clock Stretching .................................................................................................. 11-17
11.4.5 Boot Sequencer Mode.............................................................................................. 11-17
11.4.5.1 EEPROM Calling Address.................................................................................. 11-17
11.4.5.2 EEPROM Data Format........................................................................................ 11-18
11.5 Initialization/Application Information......................................................................... 11-20
11.5.1 Initialization Sequence............................................................................................. 11-20
11.5.2 Generation of START.............................................................................................. 11-21
11.5.3 Post-Transfer Software Response............................................................................ 11-21
11.5.4 Generation of STOP................................................................................................. 11-22
11.5.5 Generation of Repeated START .............................................................................. 11-22
11.5.6 Generation of SCL When SDA Low....................................................................... 11-22
11.5.7 Slave Mode Interrupt Service Routine..................................................................... 11-23
11.5.7.1 Slave Transmitter and Received Acknowledge................................................... 11-23
11.5.7.2 Loss of Arbitration and Forcing of Slave Mode.................................................. 11-23
11.5.8 Interrupt Service Routine Flowchart........................................................................ 11-23
Chapter 12
Local Bus Controller
12.1 Introduction.................................................................................................................... 12-1
12.1.1 Overview.................................................................................................................... 12-2
12.1.2 Features...................................................................................................................... 12-2
12.1.3 Modes of Operation................................................................................................... 12-3
12.1.3.1 LBC Bus Clock and Clock Ratios.........................................................................12-4
12.1.3.2 Source ID Debug Mode......................................................................................... 12-4
12.1.4 Power-Down Mode.................................................................................................... 12-4
12.1.5 References.................................................................................................................. 12-4
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NXP MPC8560ADS Reference guide

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