NXP MPC8560 User guide

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MPC8560 PowerQUICC III™

Torridon User’s Guide

MPC8560UG

Rev. 0.1

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Chandler, Arizona 85224

(800) 521-6274

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+49 89 92103 559 (German)

+33 1 69 35 48 48 (French)

Japan:

Freescale Semiconductor Japan Ltd.

Technical Information Center

3-20-1, Minami-Azabu, Minato-ku

Tokyo 106-0047 Japan

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+81-3-3440-3569

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Tai Po, N.T., Hong Kong

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MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1

Freescale Semiconductor -iii

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

Contents

Paragraph

Number Title

Page

Number

Chapter 1 References

1.1 Glossary ...............................................................................................................................1

1.2 References............................................................................................................................3

Chapter 2 Introduction

2.1 Background..........................................................................................................................1

2.2 Scope....................................................................................................................................1

2.3 System Overview.................................................................................................................1

Chapter 3 Motherboard

3.1 Motherboard Overview........................................................................................................1

3.2 Motherboard Features..........................................................................................................2

Chapter 4 Processor

4.1 Overview..............................................................................................................................1

4.2 MPC8560 Processor Configuration.....................................................................................2

4.3 COP Interface ......................................................................................................................4

Chapter 5 Flash

5.1 Overview..............................................................................................................................1

5.2 Flash.....................................................................................................................................1

Chapter 6 DDR

6.1 Overview..............................................................................................................................1

6.1.1 DDR Memory..................................................................................................................1

6.1.2 The MPC8560’s DDR Memory Controller .....................................................................1

6.1.2.1 Available Signals .........................................................................................................1

6.2 Design Considerations.........................................................................................................2

6.2.1 Signal Termination...........................................................................................................2

6.2.2 Signal Connections..........................................................................................................3

6.2.2.1 Address and Control Signals .......................................................................................3

6.2.2.2 Data..............................................................................................................................3

6.2.2.3 Clock............................................................................................................................4

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6.2.2.4 Serial Presence Detect .................................................................................................4

6.2.2.5 DDR SDRAM Power ..................................................................................................4

6.2.2.6 Voltage Generation ......................................................................................................5

6.3 Physical Implementation......................................................................................................5

6.3.1 Schematics.......................................................................................................................7

6.4 Layout................................................................................................................................12

6.4.1 Address and Control ......................................................................................................12

6.4.2 Data................................................................................................................................14

6.4.3 Clocks ............................................................................................................................17

6.4.4 DDR Power....................................................................................................................19

Chapter 7 RapidIO

7.1 Overview..............................................................................................................................1

7.1.1 RapidIO Interconnect.......................................................................................................1

7.1.2 The MPC8560’s RapidIO Controller...............................................................................1

7.1.3 Signals Descriptions ........................................................................................................1

7.2 Design Considerations.........................................................................................................2

7.2.1 Signal Termination...........................................................................................................2

7.2.2 Signal Connections..........................................................................................................3

7.3 Logic Analyser Connection .................................................................................................5

7.4 Physical Connections...........................................................................................................7

7.5 Layout Considerations.......................................................................................................11

Chapter 8 GBit Ethernet

8.1 Overview..............................................................................................................................1

8.2 GBit Ethernet Connection....................................................................................................1

8.3 GMII Interface.....................................................................................................................2

8.4 PHY Device.........................................................................................................................3

8.5 Magnetics & RJ45 ...............................................................................................................5

8.6 Layout Considerations.........................................................................................................6

Chapter 9 UART

9.1 Overview..............................................................................................................................1

Chapter 10 PCI

10.1 Overview..............................................................................................................................1

10.2 PCI Clocks...........................................................................................................................2

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10.3 Bus Connectivity..................................................................................................................2

10.4 PCI Configuration................................................................................................................2

10.5 Schematics ...........................................................................................................................2

Chapter 11 Peripheral Support

11.1 Overview..............................................................................................................................1

11.2 IDE Interface........................................................................................................................1

11.2.1 Compact Flash Support....................................................................................................4

11.2.1.1 Overview......................................................................................................................4

11.2.1.2 Implementation on Torridon........................................................................................4

11.3 USB......................................................................................................................................6

11.4 PS2.......................................................................................................................................7

Chapter 12 Communications

12.1 Overview..............................................................................................................................1

12.2 Test.......................................................................................................................................1

12.3 QUADS Compatible Headers..............................................................................................1

12.4 UTOPIA Interface..............................................................................................................13

Chapter 13 Reset

13.1 Overview..............................................................................................................................1

13.2 Reset Sources.......................................................................................................................1

13.3 Reset Scheme.......................................................................................................................2

Chapter 14 Clocking

14.1 Overview..............................................................................................................................1

14.2 System Clocks......................................................................................................................1

14.3 RapidIO Clocks....................................................................................................................4

14.3.1 Overview..........................................................................................................................4

14.3.2 Torridon’s RapidIO Sub-System......................................................................................5

14.3.3 Processor Clocks..............................................................................................................7

14.3.4 TSI500 Clocks .................................................................................................................7

14.3.5 Clock Distribution on Torridon........................................................................................9

14.4 Processor Real Time Clock................................................................................................14

14.5 GBit Ethernet Clocks.........................................................................................................16

14.6 Southbridge Real Time Clock............................................................................................16

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Contents

Paragraph

Number Title

Page

Number

Chapter 15 Voltage Regulation

15.1 Overview..............................................................................................................................1

15.2 Power Available...................................................................................................................1

15.3 Power Required....................................................................................................................2

15.4 Power Distribution...............................................................................................................2

15.5 Voltage Generation...............................................................................................................4

15.5.1 CPLD Power....................................................................................................................4

15.5.2 5V/3.3V Switching ..........................................................................................................6

15.5.3 MPC8560.........................................................................................................................8

15.5.3.1 MPC8560 Power Requirements ..................................................................................8

15.5.3.2 Core & PLL Voltage....................................................................................................8

15.5.3.3 DDR DRAM I/O Voltage ..........................................................................................14

15.5.3.4 I/O Voltage.................................................................................................................16

15.5.4 DDR SDRAM................................................................................................................16

15.5.5 GBit Ethernet.................................................................................................................18

15.5.6 TSI500 ...........................................................................................................................21

15.6 Power Sequencing..............................................................................................................25

Chapter 16 Processor Sockets

16.1 Overview..............................................................................................................................1

16.2 The Need For Sockets..........................................................................................................1

16.3 Socket Criteria .....................................................................................................................1

16.4 The Choice of a Socket........................................................................................................2

16.5 Socket Mechanics ................................................................................................................2

16.6 The Base Package Emulator (BPE) .....................................................................................4

16.7 The Flat Pin Array (FPA).....................................................................................................6

16.8 Alternative Parts ..................................................................................................................8

16.9 Sockets on Torridon.............................................................................................................8

Chapter 17 Heat Sinks

17.1 Overview..............................................................................................................................1

17.2 Processor Thermal Characteristics.......................................................................................1

17.3 Thermal Management Information......................................................................................2

17.4 Adhesives and Thermal Interface Materials........................................................................2

17.5 Heat Sink Selection..............................................................................................................3

17.6 Fans......................................................................................................................................5

17.7 Heat Sinks On Torridon .......................................................................................................6

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Contents

Paragraph

Number Title

Page

Number

Appendix A

Schematics

Appendix B

Revision History

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Tables

Table

Number Title

Page

Number

1-1 Glossary of Terms.......................................................................................................................1

4-1 MPC8560 Configuration.............................................................................................................3

4-2 COP/JTAG Connector.................................................................................................................5

6-1 DDR SDRAM Interface Signals.................................................................................................2

6-2 Data Byte Lanes........................................................................................................................14

7-1 RapidIO Interface Signals...........................................................................................................2

7-2 RapidIO Probe - P30...................................................................................................................7

7-3 RapidIO Probe - P31...................................................................................................................8

7-4 RapidIO Probe - P32...................................................................................................................9

7-5 RapidIO Probe - P33.................................................................................................................10

8-1 TSEC GMII Interface Signals.....................................................................................................2

8-2 PHY Configuration Pins .............................................................................................................4

8-3 Setting PHY Configuration Pins.................................................................................................4

8-4 PHY Configuration Pins on Torridon .........................................................................................5

8-5 Ethernet Connections..................................................................................................................6

9-1 Specific MPC8560 - UART Signals ...........................................................................................1

9-2 RS232 Connector........................................................................................................................2

11-1 CompactFlash Interconnect.........................................................................................................4

12-1 ADS Compatible Expansion Connector - P28 - Row A.............................................................5

12-2 ADS Compatible Expansion Connector - P28 - Row B .............................................................6

12-3 ADS Compatible Expansion Connector - P28 - Row C .............................................................7

12-4 ADS Compatible Expansion Connector - P28 - Row B .............................................................8

12-5 ADS Compatible Expansion Connector - P29 - Row A.............................................................9

12-6 ADS Compatible Expansion Connector - P29 - Row B ...........................................................10

12-7 ADS Compatible Expansion Connector - P29 - Row C ...........................................................11

12-8 ADS Compatible Expansion Connector - P29 - Row D...........................................................12

12-9 16 Bit UTOPIA Connector - P7 - Row A .................................................................................13

12-10 16 Bit UTOPIA Connector - P7 - Row B .................................................................................14

12-11 16 Bit UTOPIA Connector - P7 - Row C .................................................................................14

12-12 16 Bit UTOPIA Connector - P7- Row D ..................................................................................15

12-13 16 Bit UTOPIA Connector - P7 - Row E..................................................................................16

12-14 16 Bit UTOPIA Connector - P7 - Row F..................................................................................16

13-1 Reset Signals...............................................................................................................................3

15-1 Power Supplied from an ATX Power Supply .............................................................................1

15-2 Power Required...........................................................................................................................2

15-3 MPC8560 Power Requirements..................................................................................................8

16-1 Alternative Socket Vendors.........................................................................................................8

17-1 Package Thermal Characteristics................................................................................................1

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Table

Number Title

Page

Number

B-1 Revision History .........................................................................................................................1

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Figures

Figure

Number Title

Page

Number

2-1 Typical Torridon Platform Configuration ...................................................................................2

3-1 Torridon Motherboard.................................................................................................................1

3-2 Torridon Block Diagram .............................................................................................................3

4-1 MPC8560 POR Configuration....................................................................................................2

4-2 COP/JTAG Connections .............................................................................................................6

5-1 Flash ROM..................................................................................................................................2

5-2 Flash ROM Schematics - Local Bus Controller..........................................................................3

5-3 Flash ROM Schematics - Address/Data Demuxing....................................................................4

5-4 Flash ROM Schematics - Flash...................................................................................................5

6-1 DDR Termination........................................................................................................................3

6-2 DDR SDRAM Voltage Levels....................................................................................................4

6-3 DDR SDRAM Voltage Generation.............................................................................................5

6-4 64 Bit DDR SDRAM..................................................................................................................6

6-5 MPC8560 DDR Controller .........................................................................................................8

6-6 SODIMM Connection...............................................................................................................10

6-7 VTT Voltage Generation...........................................................................................................11

6-8 Address and Control..................................................................................................................12

6-9 Address and Control Layout .....................................................................................................13

6-10 Data...........................................................................................................................................15

6-11 Data Layout...............................................................................................................................16

6-12 DLL Configuration ...................................................................................................................17

6-13 DDR Clock Signals...................................................................................................................18

6-14 Clock Layout.............................................................................................................................19

6-15 LP2995 Layout..........................................................................................................................20

6-16 VREF Layout............................................................................................................................21

6-17 VTT Island................................................................................................................................22

6-18 VTT Voltage Monitoring...........................................................................................................22

7-1 RapidIO Termination ..................................................................................................................2

7-2 RapidIO Signal Connections.......................................................................................................4

7-3 Tektronix TLA700 System..........................................................................................................5

7-4 P6880 Probes...............................................................................................................................5

7-5 Mother Board Connection...........................................................................................................6

7-6 Probe Layout...............................................................................................................................6

7-7 RapidIO Receive Path Layout...................................................................................................11

7-8 RapidIO Receive Path Layout (With Logic Probes).................................................................12

8-1 GBit Ethernet Connection...........................................................................................................1

8-2 GMII Interface ............................................................................................................................3

8-3 RJ45 with Integrated Magnetics .................................................................................................6

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Figures

Figure

Number Title

Page

Number

8-4 MDI Bus Layout .........................................................................................................................7

9-1 RS232 Interface...........................................................................................................................1

9-2 MPC8560 CPM...........................................................................................................................3

9-3 RS232 Transceiver......................................................................................................................4

10-1 Boot Processor’s PCI Bus...........................................................................................................1

10-2 MPC8560’s PCI Interface - Schematics......................................................................................3

10-3 PCI Slot - Schematics .................................................................................................................5

11-1 Primary IDE Interface - Schematics ...........................................................................................2

11-2 Secondary IDE Interface - Schematics .......................................................................................3

11-3 CompactFlash Connection..........................................................................................................6

11-4 USB - Schematics .......................................................................................................................7

11-5 PS2 - Schematics.........................................................................................................................8

12-1 E1/T1 Card..................................................................................................................................2

12-2 QUADS Compatible Headers.....................................................................................................3

12-3 Connectivity to the QUADS Headers.........................................................................................4

13-1 Reset Scheme..............................................................................................................................2

13-2 Resets..........................................................................................................................................6

14-1 System Clocks.............................................................................................................................2

14-2 System Clocks - Schematics.......................................................................................................3

14-3 RapidIO Clocking.......................................................................................................................5

14-4 RapidIO Sub-System...................................................................................................................6

14-5 RapidIO Clock Options...............................................................................................................7

14-6 TSI500 RapidIO Clock Options..................................................................................................8

14-7 RapidIO Clock Distribution on Torridon..................................................................................10

14-8 High Speed Clock Generation...................................................................................................11

14-9 Slow Speed Clock Generation ..................................................................................................13

14-10 Processor Real Time Clocks .....................................................................................................14

14-11 Processor Real Time Clocks - Schematics................................................................................15

14-12 GBit Ethernet Clocks ................................................................................................................16

14-13 Real Time Clock Schematics ....................................................................................................18

15-1 Power Distribution......................................................................................................................3

15-2 CPLD Power - Schematics..........................................................................................................5

15-3 3.3V/5V Isolator - Schematics....................................................................................................7

15-4 NXI100 Power Module...............................................................................................................8

15-5 Vdd Power - Schematics...........................................................................................................10

15-6 Vdd Power - Feedback- Schematics .........................................................................................11

15-7 PLL Power - Schematics...........................................................................................................13

15-8 DDR12 Module.........................................................................................................................14

15-9 2.5V Voltage Generation...........................................................................................................15

15-10 1.25V Signal Generation...........................................................................................................17

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Page

Number

15-11 GBit Ethernet - 2.5V Generation ..............................................................................................19

15-12 GBit Ethernet - 1.5V Generation ..............................................................................................20

15-13 TSI500 - 2.5V Generation.........................................................................................................22

15-14 TSI500 - 1.3V Generation.........................................................................................................23

15-15 TSI500 - 1.2V Generation.........................................................................................................24

15-16 Power-Up Sequence..................................................................................................................26

16-1 Socket Mechanics .......................................................................................................................3

16-2 Processor - Socket Swapping......................................................................................................4

16-3 The BPE......................................................................................................................................5

16-4 The FPA ......................................................................................................................................7

16-5 BPE .............................................................................................................................................8

16-6 PowerQUICCIII in FPA..............................................................................................................9

16-7 PowerQUICCIII in FPA - Side View..........................................................................................9

16-8 PowerQUICCIII + FPA + BPE.................................................................................................10

16-9 Heat Sink Attached ...................................................................................................................10

17-1 Heat Sink Attachment.................................................................................................................2

17-2 Thermal Performance of Interface Material................................................................................3

17-3 Aavid Thermalloy 10-THMA-01 Thermal Characteristics ........................................................4

17-4 Aavid Thermalloy 10-THMA-01 Dimensions............................................................................5

17-5 Heat Sink on Torridon.................................................................................................................6

A-1 Top Level ....................................................................................................................................2

A-2 Boot Processor—Top Level........................................................................................................3

A-3 Boot Processor—Local Bus—Flash ...........................................................................................4

A-4 Boot Processor—DDR SDRAM.................................................................................................5

A-5 Boot Processor—PCI Interface...................................................................................................6

A-6 Boot Processor—RapidIO Interface ...........................................................................................7

A-7 Boot Processor—GigaByte Ethernet Interface—Top.................................................................8

A-8 Boot Processor—GigaByte Ethernet Interface ...........................................................................9

A-9 Boot Processor—GigaByte Ethernet Interface—PHY1 ...........................................................10

A-10 Boot Processor—GigaByte Ethernet Interface—PHY2 ...........................................................11

A-11 Boot Processor—Communications Processor Module.............................................................12

A-12 Boot Processor—Auxiliary Functions......................................................................................13

A-13 Boot Processor—Power On Configuration...............................................................................14

A-14 Boot Processor—PCI Expansion..............................................................................................15

A-15 Southbridge—Top Level...........................................................................................................16

A-16 Southbridge—PCI, PIDE, AC97 ..............................................................................................17

A-17 Southbridge—Side, ISA, Peripheral.........................................................................................18

A-18 Southbridge—IO.......................................................................................................................19

A-19 Boot Processor—PCI Slot.........................................................................................................20

A-20 Boot Processor—Power............................................................................................................21

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Figures

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Page

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A-21 Work Processor 1—Top Level..................................................................................................22

A-22 Work Processor 1—Local Bus..................................................................................................23

A-23 Work Processor 1—DDR SDRAM...........................................................................................24

A-24 Work Processor 1—RapidIO Interface .....................................................................................25

A-25 Work Processor 1—PCI Interface.............................................................................................26

A-26 Work Processor 1—GigaByte Ethernet Interface—Top...........................................................27

A-27 Work Processor 1—GigaByte Ethernet Interface.....................................................................28

A-28 Work Processor 1—GigaByte Ethernet Interface—PHY .........................................................29

A-29 Work Processor 1—Communications Processor Module.........................................................30

A-30 Work Processor 1—Auxiliary Functions..................................................................................31

A-31 Work Processor 1—Power On Configuration...........................................................................32

A-32 Work Processor 1—Power........................................................................................................33

A-33 Work Processor 2—Top Level..................................................................................................34

A-34 Work Processor 2—Local Bus..................................................................................................35

A-35 Work Processor 2—DDR SDRAM...........................................................................................36

A-36 Work Processor 2—RapidIO Interface .....................................................................................37

A-37 Work Processor 2—PCI Interface.............................................................................................38

A-38 Work Processor 2—GigaByte Ethernet Interface—Top...........................................................39

A-39 Work Processor 2—GigaByte Ethernet Interface.....................................................................40

A-40 GigaByte Ethernet Interface—PHY..........................................................................................41

A-41 Work Processor 2—Communications Processor Module.........................................................42

A-42 Work Processor 2—Auxiliary Functions..................................................................................43

A-43 Work Processor 2—Power On Configuration...........................................................................44

A-44 Work Processor 2—Power........................................................................................................45

A-45 Work Processor 3—Top Level..................................................................................................46

A-46 Work Processor 3—Local Bus..................................................................................................47

A-47 Work Processor 3—DDR SDRAM...........................................................................................48

A-48 Work Processor 3—RapidIO Interface .....................................................................................49

A-49 Work Processor 3—PCI Interface.............................................................................................50

A-50 Work Processor 3—GigaByte Ethernet Interface—Top...........................................................51

A-51 Work Processor 3—GigaByte Ethernet Interface.....................................................................52

A-52 Work Processor 3—GigaByte Ethernet Interface—PHY .........................................................53

A-53 Work Processor 3—Communications Processor Module.........................................................54

A-54 Work Processor 3—Auxiliary Functions..................................................................................55

A-55 Work Processor 3—Power On Configuration...........................................................................56

A-56 Work Processor 3—Power........................................................................................................57

A-57 RapidIO Switch—Top Level.....................................................................................................58

A-58 RapidIO Switch—Ports 0 and 1................................................................................................59

A-59 RapidIO Switch—Ports 2 and 3................................................................................................60

A-60 RapidIO Switch—Misc.............................................................................................................61

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A-61 RapidIO Switch—Power...........................................................................................................62

A-62 Clocking—Top Level................................................................................................................63

A-63 Clocking—Processor ................................................................................................................64

A-64 Clocking—RapidIO..................................................................................................................65

A-65 Reset Control.............................................................................................................................66

A-66 Power Supply—Top Level........................................................................................................67

A-67 Power Supply—Core Voltage...................................................................................................68

A-68 Power Supply—IO Voltages.....................................................................................................69

A-69 Power Supply—Supplied Power...............................................................................................70

A-70 WP—Debug Ports.....................................................................................................................71

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MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1

Freescale Semiconductor 1-1

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Chapter 1 References

This section contains references used throughout this design guide.

1.1 Glossary

Table 1-1 shows acronyms and terms used throughout this design guide.

Table 1-1. Glossary of Terms

Term Description

ATA AT Attachment

ATM Asynchronous Transfer Mode

Boot Processor MPC8560 Networking and Communications Processor

CD Carrier Detect

COP Common On-Board Processor

CPM Communication Processor Module

CTS Clear To Send

DDR SDRAM Double Data Rate SDRAM

DIMM Dual Inline Memory Module

DIP Dual Inline Package

DLL

Delay Locked Loop

DMA

Direct Memory Access

DSR

Data Send Ready

DTR

Data Terminal Ready

EEPROM

Electrically Erasable Programmable Read Only Memory

FCC Fast Communications Controller

FIFO First In First Out

FPGA Field Programmable Gate Array

GMII GBit Media Independent Interface

GPCM General Purpose Chip Select Machine

I2C Inter-Integrated Circuit Controller

IDE Integrated Device Electronics

I/O Input/Output

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1

1-2 Freescale Semiconductor

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

References

LP-LVDS Link Protocol - Low Voltage Differential Signalling

JTAG Joint Test Access Group

MAC Media Access Controller

MCC Multi-Channel Communications Controller

MII Media Independent Interface

PCB Printed Circuit Board

PCI Peripheral Component Interconnect

PCMCIA Personal Computer Memory Card International Association

PLL Phase Locked Loop

PHY Physical Interface

POR Power on Reset

PowerQUICC MPC8xx Networking and Communications Processor

PowerQUICCII MPC82xx Networking and Communications Processor

PowerQUICCIII MPC85xx Networking and Communications Processor

RI Ring Indicator

RIO RapidIO

ROM Read Only Memory

RTS Ready to Send

Rxd Received Data

SCC Serial Communications Controller

SDRAM Synchronous Dynamic Random Access Memory

SPD Serial Presence Detect

SSTL_2 Stub Series Terminated Logic for 2.5 Volts

TDM Time Division Multiplex

TSEC Triple Speed Ethernet Controller

Txd Transmitted Data

USB Universal Serial Bus

UTOPIA Universal Test Operational Physical Interface for ATM

Work Processor MPC8560 Networking and Communications Processor

Table 1-1. Glossary of Terms (continued)

Term Description

References

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1

Freescale Semiconductor 1-3

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

1.2 References

Please refer to the following for more information.

1. MPC8560 Integrated Processor Reference Manual

2. MPC8540 Integrated Processor Reference Manual

3. TSI500 RapidIO Multi-port Switch User Manual

4. M88E1011 Data Sheet

5. Via VT82C686B “Super South” South Bridge Data Sheet

6. Torridon System Specification - Ver 1.3

7. Torridon User Manual - Ver 2.0

MPC8560 PowerQUICC III Torridon User’s Guide, Rev. 0.1

1-4 Freescale Semiconductor

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

References

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NXP MPC8560 User guide

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