NXP MPC860 Reference guide

Type
Reference guide
MPC860 PowerQUICC™ Family
Users Manual
Supports
MPC860P
MPC860T
MPC860SR
MPC860DP
MPC860DE
MPC860EN
MPC860DT
MPC860UM
Rev. 3
07/2004
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© Freescale Semiconductor, Inc. 2004. All rights reserved.
MPC860UM
Rev. 3
07/2004
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Part I—Overview
I
Overview 1
Signal Descriptions 2
Part II—MPC8xx Microprocessor Module
II
The MPC8xx Core 3
MPC8xx Core Register Set 4
MPC8xx Instruction Set 5
Exceptions 6
Instruction and Data Caches 7
Memory Management Unit 8
Instruction Execution Timing 9
Part III—Configuration and Reset
III
System Interface Unit 10
Reset 11
Part IV—Hardware Interface
IV
External Signals 12
External Bus Interface 13
Clocks and Power Control 14
Memory Controller 15
PCMCIA Interface 16
Part V—Communications Processor Module
V
Communications Processor Module and CPM Timers 17
Communications Processor 18
SDMA Channels and IDMA Emulation 19
Serial Interface 20
Serial Communications Controllers 21
SCC UART Mode 22
SCC HDLC Mode 23
SCC AppleTalk Mode 24
SCC Asynchronous HDLC Mode and IrDA 25
SCC BISYNC Mode 26
SCC Ethernet Mode 27
SCC Transparent Mode 28
Serial Management Controllers (SMCs) 29
Serial Peripheral Interface (SPI) 30
I
2
C Controller 31
Parallel Interface Port (PIP) 32
Parallel I/O Ports 33
CPM Interrupt Controller 34
I Part I—Overview
1
Overview
2
Signal Descriptions
II Part II—MPC8xx Microprocessor Module
3
The MPC8xx Core
4
MPC8xx Core Register Set
5
MPC8xx Instruction Set
6
Exceptions
7
Instruction and Data Caches
8
Memory Management Unit
9
Instruction Execution Timing
III Part III—Configuration and Reset
10
System Interface Unit
11
Reset
IV Part IV—Hardware Interface
12
External Signals
13
External Bus Interface
14
Clocks and Power Control
15
Memory Controller
16
PCMCIA Interface
V Part V—Communications Processor Module
17
Communications Processor Module and CPM Timers
18
Communications Processor
19
SDMA Channels and IDMA Emulation
20
Serial Interface
21
Serial Communications Controllers
22
SCC UART Mode
23
SCC HDLC Mode
24
SCC AppleTalk Mode
25
SCC Asynchronous HDLC Mode and IrDA
26
SCC BISYNC Mode
27
SCC Ethernet Mode
28
SCC Transparent Mode
29
Serial Management Controllers (SMCs)
30
Serial Peripheral Interface (SPI)
31
I
2
C Controller
32
Parallel Interface Port (PIP)
33
Parallel I/O Ports
34
CPM Interrupt Controller
Part VI—Asynchronous Transfer Mode (ATM)
VI
ATM Overview 35
Buffer Descriptors and Connection Tables 36
ATM Parameter RAM 37
ATM Controller 38
ATM Pace Control 39
ATM Exceptions 40
Interface Configuration 41
UTOPIA Interface 42
Part VII—Fast Ethernet Controller (FEC)
VII
Fast Ethernet Controller (FEC) 43
Part VIII—System Debugging and Testing Support
VIII
System Development and Debugging 44
IEEE 1149.1 Test Access Port 45
Byte Ordering A
Serial Communications Performance B
Register Quick Reference Guide C
Instruction Set Listings D
Serial ATM Scrambling, Reception, and SI Programming E
MPC860DE F
MPC860DT G
MPC860DP H
MPC860EN I
MPC860SR J
MPC860T K
User’s Manual Revision History L
Glossary GLO
Index IND
VI Part VI—Asynchronous Transfer Mode (ATM)
35
ATM Overview
36
Buffer Descriptors and Connection Tables
37
ATM Parameter RAM
38
ATM Controller
39
ATM Pace Control
40
ATM Exceptions
41
Interface Configuration
42
UTOPIA Interface
VII Part VII—Fast Ethernet Controller (FEC)
43
Fast Ethernet Controller (FEC)
VIII Part VIII—System Debugging and Testing Support
44
System Development and Debugging
45
IEEE 1149.1 Test Access Port
A
Byte Ordering
B
Serial Communications Performance
C
Register Quick Reference Guide
D
Instruction Set Listings
E
Serial ATM Scrambling, Reception, and SI Programming
F
MPC860DE
G
MPC860DT
H
MPC860DP
I
MPC860EN
J
MPC860SR
K
MPC860T
L
User’s Manual Revision History
GLO
Glossary
IND
Index
MPC860 PowerQUICC Family User’s Manual, Rev. 3
Freescale Semiconductor vii
Contents
Paragraph
Number Title
Page
Number
About This Book
Part I
Overview
Chapter 1
MPC860 Overview
1.1 Features............................................................................................................................ 1-2
1.2 Embedded MPC8xx Core................................................................................................ 1-8
1.3 System Interface Unit (SIU) ............................................................................................ 1-9
1.4 PCMCIA Controller....................................................................................................... 1-10
1.5 Power Management ....................................................................................................... 1-10
1.6 Communications Processor Module (CPM)..................................................................1-10
1.7 ATM Capabilities........................................................................................................... 1-11
Chapter 2
Memory Map
Part II
MPC8xx Microprocessor Module
Chapter 3
The MPC8xx Core
3.1 The MPC8xx Core as a PowerPC Implementation ......................................................... 3-1
3.2 PowerPC Architecture Overview..................................................................................... 3-1
3.2.1 Levels of the PowerPC Architecture ........................................................................... 3-3
3.3 Features............................................................................................................................ 3-4
3.4 Basic Structure of the Core.............................................................................................. 3-6
3.4.1 Instruction Flow...........................................................................................................3-7
3.4.2 Basic Instruction Pipeline............................................................................................ 3-8
3.4.3 Instruction Unit............................................................................................................ 3-8
3.4.3.1 Branch Operations ................................................................................................... 3-8
3.4.3.2 Dispatching Instructions........................................................................................ 3-10
3.5 Register Set.................................................................................................................... 3-10
3.6 Execution Units..............................................................................................................3-10
3.6.1 Branch Processing Unit ............................................................................................. 3-11
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3.6.2 Integer Unit................................................................................................................ 3-11
3.6.3 Load/Store Unit.......................................................................................................... 3-11
3.6.3.1 Executing Load/Store Instructions......................................................................... 3-13
3.6.3.2 Serializing Load/Store Instructions ....................................................................... 3-13
3.6.3.3 Store Accesses ....................................................................................................... 3-13
3.6.3.4 Nonspeculative Load Instructions ......................................................................... 3-14
3.6.3.5 Unaligned Accesses............................................................................................... 3-14
3.6.3.6 Atomic Update Primitives ..................................................................................... 3-15
3.7 The MPC860 and Implementation of the PowerPC Architecture ................................. 3-15
Chapter 4
MPC8xx Core Register Set
4.1 MPC860 Register Implementation .................................................................................. 4-1
4.1.1 PowerPC Registers—User Registers........................................................................... 4-1
4.1.1.1 PowerPC User-Level Register Bit Assignments .....................................................4-2
4.1.1.1.1 Condition Register (CR)...................................................................................... 4-2
4.1.1.1.2 Condition Register CR0 Field Definition............................................................ 4-3
4.1.1.1.3 XER .....................................................................................................................4-3
4.1.1.1.4 Time Base Registers ............................................................................................ 4-4
4.1.2 PowerPC Registers—Supervisor Registers ................................................................. 4-5
4.1.2.1 DAR, DSISR, and BAR Operation.......................................................................... 4-5
4.1.2.2 Unsupported Registers............................................................................................. 4-6
4.1.2.3 PowerPC Supervisor-Level Register Bit Assignments............................................ 4-6
4.1.2.3.1 Machine State Register (MSR)............................................................................ 4-7
4.1.2.3.2 Processor Version Register.................................................................................. 4-9
4.1.3 MPC860-Specific SPRs............................................................................................... 4-9
4.1.3.1 Accessing SPRs ..................................................................................................... 4-11
4.2 Register Initialization at Reset....................................................................................... 4-12
Chapter 5
MPC860 Instruction Set
5.1 Operand Conventions ...................................................................................................... 5-1
5.1.1 Data Organization in Memory and Data Transfers......................................................5-1
5.1.2 Aligned and Misaligned Accesses............................................................................... 5-1
5.2 Instruction Set Summary ................................................................................................. 5-2
5.2.1 Classes of Instructions ................................................................................................. 5-3
5.2.1.1 Definition of Boundedly Undefined........................................................................ 5-4
5.2.1.2 Defined Instruction Class ........................................................................................ 5-4
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5.2.1.3 Illegal Instruction Class........................................................................................... 5-4
5.2.1.4 Reserved Instruction Class ...................................................................................... 5-5
5.2.2 Addressing Modes ....................................................................................................... 5-5
5.2.2.1 Memory Addressing ................................................................................................ 5-6
5.2.2.2 Effective Address Calculation ................................................................................. 5-6
5.2.2.3 Synchronization....................................................................................................... 5-6
5.2.2.3.1 Context Synchronization ..................................................................................... 5-6
5.2.2.3.2 Execution Synchronization.................................................................................. 5-7
5.2.2.3.3 Instruction-Related Exceptions............................................................................ 5-7
5.2.3 Instruction Set Overview ............................................................................................. 5-8
5.2.4 PowerPC UISA Instructions........................................................................................ 5-8
5.2.4.1 Integer Instructions.................................................................................................. 5-8
5.2.4.1.1 Integer Arithmetic Instructions............................................................................ 5-8
5.2.4.1.2 Integer Compare Instructions .............................................................................. 5-9
5.2.4.1.3 Integer Logical Instructions............................................................................... 5-10
5.2.4.1.4 Integer Rotate and Shift Instructions................................................................. 5-11
5.2.4.2 Load and Store Instructions................................................................................... 5-12
5.2.4.2.1 Integer Load and Store Address Generation......................................................5-12
5.2.4.2.2 Register Indirect Integer Load Instructions.......................................................5-12
5.2.4.2.3 Integer Store Instructions................................................................................... 5-13
5.2.4.2.4 Integer Load and Store with Byte-Reverse Instructions.................................... 5-13
5.2.4.2.5 Integer Load and Store Multiple Instructions....................................................5-14
5.2.4.2.6 Integer Load and Store String Instructions........................................................ 5-14
5.2.4.3 Branch and Flow Control Instructions................................................................... 5-15
5.2.4.3.1 Branch Instruction Address Calculation............................................................5-16
5.2.4.3.2 Branch Instructions............................................................................................ 5-16
5.2.4.3.3 Condition Register Logical Instructions............................................................ 5-17
5.2.4.4 Trap Instructions.................................................................................................... 5-17
5.2.4.5 Processor Control Instructions............................................................................... 5-17
5.2.4.5.1 Move to/from Condition Register Instructions.................................................. 5-17
5.2.4.6 Memory Synchronization Instructions—UISA..................................................... 5-18
5.2.5 PowerPC VEA Instructions ....................................................................................... 5-20
5.2.5.1 Processor Control Instructions............................................................................... 5-20
5.2.5.2 Memory Synchronization Instructions—VEA ...................................................... 5-20
5.2.5.2.1 eieio Behavior.................................................................................................... 5-21
5.2.5.2.2 isync Behavior................................................................................................... 5-21
5.2.5.3 Memory Control Instructions—VEA .................................................................... 5-21
5.2.6 PowerPC OEA Instructions ....................................................................................... 5-22
5.2.6.1 System Linkage Instructions.................................................................................. 5-22
5.2.6.2 Processor Control Instructions—OEA .................................................................. 5-23
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5.2.6.2.1 Move to/from Machine State Register Instructions...........................................5-23
5.2.6.2.2 Move to/from Special-Purpose Register Instructions........................................ 5-23
5.2.6.3 Memory Control Instructions—OEA .................................................................... 5-24
Chapter 6
Exceptions
6.1 Exceptions........................................................................................................................ 6-1
6.1.1 Exception Ordering...................................................................................................... 6-3
6.1.2 PowerPC-Defined Exceptions ..................................................................................... 6-4
6.1.2.1 System Reset Interrupt (0x00100)...........................................................................6-5
6.1.2.2 Machine Check Interrupt (0x00200) ....................................................................... 6-5
6.1.2.3 DSI Exception (0x00300)........................................................................................ 6-6
6.1.2.4 ISI Exception (0x00400).......................................................................................... 6-6
6.1.2.5 External Interrupt Exception (0x00500).................................................................. 6-6
6.1.2.6 Alignment Exception (0x00600) .............................................................................6-7
6.1.2.6.1 Integer Alignment Exceptions............................................................................. 6-8
6.1.2.7 Program Exception (0x00700)................................................................................. 6-9
6.1.2.8 Decrementer Exception (0x00900)........................................................................6-10
6.1.2.9 System Call Exception (0x00C00) ........................................................................ 6-11
6.1.2.10 Trace Exception (0x00D00)................................................................................... 6-11
6.1.2.11 Floating-Point Assist Exception ............................................................................ 6-12
6.1.3 Implementation-Specific Exceptions......................................................................... 6-12
6.1.3.1 Software Emulation Exception (0x01000) ............................................................ 6-12
6.1.3.2 Instruction TLB Miss Exception (0x01100).......................................................... 6-13
6.1.3.3 Data TLB Miss Exception (0x01200).................................................................... 6-13
6.1.3.4 Instruction TLB Error Exception (0x01300).........................................................6-14
6.1.3.5 Data TLB Error Exception (0x01400)................................................................... 6-14
6.1.3.6 Debug Exceptions (0x01C00–0x01F00) ...............................................................6-15
6.1.4 Implementing the Precise Exception Model.............................................................. 6-16
6.1.5 Recoverability After an Exception ............................................................................ 6-17
6.1.6 Exception Latency ..................................................................................................... 6-19
6.1.7 Partially Completed Instructions ............................................................................... 6-20
Chapter 7
Instruction and Data Caches
7.1 Instruction Cache Organization ....................................................................................... 7-2
7.2 Data Cache Organization ................................................................................................. 7-5
7.3 Cache Control Registers .................................................................................................. 7-8
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7.3.1 Instruction Cache Control Registers............................................................................ 7-8
7.3.1.1 Reading Data and Tags in the Instruction Cache................................................... 7-11
7.3.1.2 IC_CST Commands............................................................................................... 7-12
7.3.1.2.1 Instruction Cache Enable/Disable Commands .................................................. 7-12
7.3.1.2.2 Instruction Cache Load and Lock Cache Block Command .............................. 7-12
7.3.1.2.3 Instruction Cache Unlock Cache Block Command...........................................7-13
7.3.1.2.4 Instruction Cache Unlock All Command .......................................................... 7-13
7.3.1.2.5 Instruction Cache Invalidate All Command ...................................................... 7-14
7.3.2 Data Cache Control Registers.................................................................................... 7-14
7.3.2.1 Reading Data Cache Tags and Copyback Buffer...................................................7-17
7.3.2.2 DC_CST Commands ............................................................................................. 7-18
7.3.2.2.1 Data Cache Enable/Disable Commands............................................................ 7-18
7.3.2.2.2 Data Cache Load and Lock Cache Block Command........................................7-19
7.3.2.2.3 Data Cache Unlock Cache Block Command.....................................................7-19
7.3.2.2.4 Data Cache Unlock All Command.................................................................... 7-20
7.3.2.2.5 Data Cache Invalidate All Command................................................................ 7-20
7.3.2.2.6 Data Cache Flush Cache Block Command........................................................ 7-20
7.4 Cache Control Instructions ............................................................................................ 7-21
7.4.1 Instruction Cache Block Invalidate (icbi).................................................................. 7-21
7.4.2 Data Cache Block Touch (dcbt) and Data Cache Block Touch for Store (dcbtst)... 7-21
7.4.3 Data Cache Block Zero (dcbz).................................................................................. 7-22
7.4.4 Data Cache Block Store (dcbst)................................................................................ 7-22
7.4.5 Data Cache Block Flush (dcbf)................................................................................. 7-22
7.4.6 Data Cache Block Invalidate (dcbi).......................................................................... 7-23
7.5 Instruction Cache Operations......................................................................................... 7-23
7.5.1 Instruction Cache Hit................................................................................................. 7-25
7.5.2 Instruction Cache Miss .............................................................................................. 7-25
7.5.3 Instruction Fetching on a Predicted Path................................................................... 7-26
7.5.4 Fetching Instructions from Caching-Inhibited Regions.............................................7-26
7.5.5 Updating Code and Memory Region Attributes........................................................ 7-26
7.6 Data Cache Operation.................................................................................................... 7-27
7.6.1 Data Cache Load Hit.................................................................................................. 7-28
7.6.2 Data Cache Read Miss............................................................................................... 7-28
7.6.3 Write-Through Mode................................................................................................. 7-29
7.6.3.1 Data Cache Store Hit in Write-Through Mode...................................................... 7-29
7.6.3.2 Data Cache Store Miss in Write-Through Mode...................................................7-29
7.6.4 Write-Back Mode....................................................................................................... 7-29
7.6.4.1 Data Cache Store Hit in Write-Back Mode ...........................................................7-30
7.6.4.2 Data Cache Store Miss in Write-Back Mode.........................................................7-30
7.6.5 Data Accesses to Caching-Inhibited Memory Regions.............................................7-31
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7.6.6 Atomic Memory References...................................................................................... 7-31
7.7 Cache Initialization after Reset...................................................................................... 7-32
7.8 Debug Support...............................................................................................................7-33
7.8.1 Instruction and Data Cache Operation in Debug Mode.............................................7-33
7.8.2 Instruction and Data Cache Operation with a Software Monitor Debugger.............. 7-33
Chapter 8
Memory Management Unit
8.1 Features............................................................................................................................ 8-1
8.2 PowerPC Architecture Compliance................................................................................. 8-2
8.3 Address Translation ......................................................................................................... 8-3
8.3.1 Translation Disabled.................................................................................................... 8-3
8.3.2 Translation Enabled ..................................................................................................... 8-3
8.3.3 TLB Operation............................................................................................................. 8-5
8.4 Using Access Protection Groups ..................................................................................... 8-6
8.5 Protection Resolution Modes........................................................................................... 8-7
8.6 Memory Attributes........................................................................................................... 8-8
8.7 Translation Table Structure.............................................................................................. 8-9
8.7.1 Level-One Descriptor ................................................................................................ 8-12
8.7.2 Level-Two Descriptor................................................................................................ 8-13
8.7.3 Page Size....................................................................................................................8-14
8.8 Programming Model...................................................................................................... 8-14
8.8.1 IMMU Control Register (MI_CTR) .......................................................................... 8-15
8.8.2 DMMU Control Register (MD_CTR)....................................................................... 8-16
8.8.3 IMMU/DMMU Effective Page Number Register (Mx_EPN) ..................................8-18
8.8.4 IMMU Tablewalk Control Register (MI_TWC) .......................................................8-18
8.8.5 DMMU Tablewalk Control Register (MD_TWC) .................................................... 8-19
8.8.6 IMMU Real Page Number Register (MI_RPN) ........................................................ 8-21
8.8.7 DMMU Real Page Number Register (MD_RPN).....................................................8-22
8.8.8 MMU Tablewalk Base Register (M_TWB)............................................................... 8-24
8.8.9 MMU Current Address Space ID Register (M_CASID)........................................... 8-25
8.8.10 MMU Access Protection Registers (MI_AP/MD_AP) ............................................. 8-25
8.8.11 MMU Tablewalk Special Register (M_TW) ............................................................. 8-26
8.8.12 MMU Debug Registers.............................................................................................. 8-26
8.8.12.1 IMMU CAM Entry Read Register (MI_CAM).....................................................8-26
8.8.12.2 IMMU RAM Entry Read Register 0 (MI_RAM0)................................................8-28
8.8.12.3 IMMU RAM Entry Read Register 1 (MI_RAM1)................................................8-29
8.8.12.4 DMMU CAM Entry Read Register (MD_CAM).................................................. 8-30
8.8.12.5 DMMU RAM Entry Read Register 0 (MD_RAM0)............................................. 8-31
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8.8.13 DMMU RAM Entry Read Register 1 (MD_RAM1)................................................. 8-32
8.9 Memory Management Unit Exceptions......................................................................... 8-33
8.10 TLB Manipulation ......................................................................................................... 8-34
8.10.1 TLB Reload................................................................................................................8-34
8.10.1.1 Translation Reload Examples................................................................................ 8-34
8.10.2 Locking TLB Entries ................................................................................................. 8-36
8.10.3 Loading Locked TLB Entries .................................................................................... 8-36
8.10.4 TLB Invalidation........................................................................................................ 8-37
Chapter 9
Instruction Execution Timing
9.1 Instruction Execution Timing Examples.......................................................................... 9-1
9.1.1 Data Cache Load with a Data Dependency ................................................................. 9-1
9.1.2 Writeback Arbitration.................................................................................................. 9-2
9.1.3 Private Writeback Bus Load........................................................................................ 9-3
9.1.4 Fastest External Load (Data Cache Miss).................................................................... 9-3
9.1.5 A Full Completion Queue............................................................................................ 9-4
9.1.6 Branch Instruction Handling........................................................................................ 9-5
9.1.7 Branch Prediction ........................................................................................................ 9-5
9.2 Instruction Timing List .................................................................................................... 9-6
9.2.1 Load/Store Instruction Timing..................................................................................... 9-8
9.2.2 String Instruction Latency ........................................................................................... 9-8
9.2.3 Accessing Off-Core SPRs............................................................................................ 9-8
Part III
Configuration and Reset
Chapter 10
System Interface Unit
10.1 Features..........................................................................................................................10-1
10.2 System Configuration and Protection............................................................................ 10-2
10.3 Multiplexing SIU Pins................................................................................................... 10-3
10.4 Programming the SIU .................................................................................................... 10-4
10.4.1 Internal Memory Map Register (IMMR)................................................................... 10-5
10.4.2 SIU Module Configuration Register (SIUMCR).......................................................10-6
10.4.3 System Protection Control Register (SYPCR) ..........................................................10-8
10.4.4 Transfer Error Status Register (TESR)...................................................................... 10-9
10.4.5 Register Lock Mechanism ....................................................................................... 10-10
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10.5 System Configuration .................................................................................................. 10-12
10.5.1 Interrupt Structure.................................................................................................... 10-12
10.5.2 Priority of Interrupt Sources .................................................................................... 10-14
10.5.3 SIU Interrupt Processing.......................................................................................... 10-14
10.5.3.1 Nonmaskable Interrupts—IRQ0 and SWT..........................................................10-15
10.5.4 Programming the SIU Interrupt Controller.............................................................. 10-16
10.5.4.1 SIU Interrupt Pending Register (SIPEND).......................................................... 10-16
10.5.4.2 SIU Interrupt Mask Register (SIMASK)............................................................. 10-17
10.5.4.3 SIU Interrupt Edge/Level Register (SIEL).......................................................... 10-18
10.5.4.4 SIU Interrupt Vector Register (SIVEC)............................................................... 10-19
10.6 The Bus Monitor.......................................................................................................... 10-21
10.7 Software Watchdog Timer ........................................................................................... 10-22
10.7.1 Software Service Register (SWSR)......................................................................... 10-23
10.8 The Decrementer.......................................................................................................... 10-24
10.8.1 Decrementer Register (DEC)................................................................................... 10-25
10.9 The Timebase............................................................................................................... 10-25
10.9.1 Timebase Register (TBU and TBL)......................................................................... 10-25
10.9.2 Timebase Reference Registers (TBREFA and TBREFB) ....................................... 10-26
10.9.3 Timebase Status and Control Register (TBSCR).....................................................10-27
10.10 The Real-Time Clock................................................................................................... 10-28
10.10.1 Real-Time Clock Status and Control Register (RTCSC)......................................... 10-29
10.10.2 Real-Time Clock Register (RTC) ............................................................................ 10-30
10.10.3 Real-Time Clock Alarm Register (RTCAL)............................................................ 10-30
10.10.4 Real-Time Clock Alarm Seconds Register (RTSEC).............................................. 10-31
10.11 Periodic Interrupt Timer (PIT)..................................................................................... 10-32
10.11.1 Periodic Interrupt Status and Control Register (PISCR) .........................................10-33
10.11.2 PIT Count Register (PITC)......................................................................................10-34
10.11.3 PIT Register (PITR)................................................................................................. 10-34
10.12 General SIU Timers Operation .................................................................................... 10-35
10.12.1 Freeze Operation...................................................................................................... 10-35
10.12.2 Low-Power Stop Operation ..................................................................................... 10-35
Chapter 11
Reset
11.1 Types of Reset................................................................................................................ 11-1
11.1.1 Power-On Reset ......................................................................................................... 11-2
11.1.2 External Hard Reset................................................................................................... 11-2
11.1.3 Internal Hard Reset.................................................................................................... 11-2
11.1.3.1 Software Watchdog Reset...................................................................................... 11-3
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11.1.3.2 Checkstop Reset..................................................................................................... 11-3
11.1.4 Debug Port Hard or Soft Reset.................................................................................. 11-3
11.1.5 JTAG Reset................................................................................................................ 11-3
11.1.6 Power-On and Hard Reset Sequence......................................................................... 11-3
11.1.7 External Soft Reset .................................................................................................... 11-4
11.1.8 Internal Soft Reset ..................................................................................................... 11-4
11.1.9 Soft Reset Sequence................................................................................................... 11-4
11.2 Reset Status Register (RSR) .......................................................................................... 11-5
11.3 MPC860 Reset Configuration........................................................................................ 11-6
11.3.1 Hard Reset.................................................................................................................. 11-7
11.3.1.1 Hard Reset Configuration Word ............................................................................ 11-9
11.3.2 Soft Reset..................................................................................................................11-11
11.4 TRST and Power Mode Considerations .......................................................................11-11
Part IV
Hardware Interface
Chapter 12
External Signals
12.1 System Bus Signals........................................................................................................ 12-5
12.2 Active Pull-Up Buffers ................................................................................................ 12-23
12.3 Internal Pull-Up and Pull-Down Resistors ................................................................. 12-25
12.4 Recommended Basic Pin Connections ........................................................................ 12-25
12.4.1 Reset Configuration................................................................................................. 12-26
12.4.1.1 Bus Control Signals and Interrupts...................................................................... 12-26
12.4.2 JTAG and Debug Ports ............................................................................................12-26
12.4.3 Unused Inputs ..........................................................................................................12-27
12.4.4 Unused Outputs........................................................................................................ 12-27
12.5 Signal States During Reset........................................................................................... 12-27
Chapter 13
External Bus Interface
13.1 Features..........................................................................................................................13-1
13.2 Bus Transfer Overview.................................................................................................. 13-1
13.3 Bus Interface Signal Descriptions.................................................................................. 13-2
13.4 Bus Operations............................................................................................................... 13-6
13.4.1 Basic Transfer Protocol.............................................................................................. 13-6
13.4.2 Single-Beat Transfer.................................................................................................. 13-7
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13.4.2.1 Single-Beat Read Flow.......................................................................................... 13-7
13.4.2.2 Single-Beat Write Flow ....................................................................................... 13-10
13.4.3 Burst Transfers......................................................................................................... 13-14
13.4.4 Burst Operations ...................................................................................................... 13-15
13.4.5 Alignment and Data Packing on Transfers.............................................................. 13-24
13.4.6 Arbitration Phase ..................................................................................................... 13-27
13.4.6.1 Bus Request (BR) ................................................................................................ 13-28
13.4.6.2 Bus Grant (BG).................................................................................................... 13-28
13.4.6.3 Bus Busy (BB)..................................................................................................... 13-28
13.4.6.4 External Bus Parking........................................................................................... 13-31
13.4.7 Address Transfer Phase-Related Signals ................................................................. 13-31
13.4.7.1 Transfer Start (TS)............................................................................................... 13-31
13.4.7.2 Address Bus......................................................................................................... 13-32
13.4.7.3 Transfer Attributes............................................................................................... 13-32
13.4.7.3.1 Read/Write (RD/WR) ...................................................................................... 13-32
13.4.7.3.2 Burst Indicator (BURST)................................................................................. 13-32
13.4.7.3.3 Transfer Size (TSIZ)........................................................................................ 13-32
13.4.7.3.4 Address Types (AT)......................................................................................... 13-33
13.4.7.3.5 Burst Data in Progress (BDIP) ........................................................................ 13-35
13.4.8 Termination Signals................................................................................................. 13-35
13.4.8.1 Transfer Acknowledge (TA)................................................................................ 13-35
13.4.8.2 Burst Inhibit (BI) ................................................................................................. 13-35
13.4.8.3 Transfer Error Acknowledge (TEA).................................................................... 13-35
13.4.8.4 Termination Signals Protocol .............................................................................. 13-35
13.4.9 Memory Reservation................................................................................................ 13-37
13.4.9.1 Cancel Reservation (CR)..................................................................................... 13-37
13.4.9.2 Kill Reservation (KR
).......................................................................................... 13-38
13.4.10 Bus Exception Control Cycles................................................................................. 13-39
13.4.10.1 RETRY ................................................................................................................ 13-40
Chapter 14
Clocks and Power Control
14.1 Features..........................................................................................................................14-1
14.2 The Clock Module......................................................................................................... 14-2
14.2.1 External Reference Clocks......................................................................................... 14-3
14.2.1.1 Off-Chip Oscillator Input (EXTCLK)................................................................... 14-4
14.2.1.2 Crystal Oscillator Support (EXTAL and XTAL)...................................................14-4
14.2.2 System PLL................................................................................................................14-5
14.2.2.1 SPLL Reset Configuration..................................................................................... 14-6
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14.2.2.2 SPLL Output Characteristics and Stability............................................................ 14-7
14.2.2.3 System Phase-Locked Loop Pins (VDDSYN, VSSSYN, VSSSYN1, XFC)........ 14-8
14.2.2.4 Disabling the SPLL................................................................................................ 14-9
14.3 Clock Signals ................................................................................................................. 14-9
14.3.1 Clocks Derived from the SPLL Output ................................................................... 14-10
14.3.1.1 The Internal General System Clocks (GCLK1C, GCLK2C, GCLK1,
GCLK2)........................................................................................................... 14-11
14.3.1.2 Memory Controller and External Bus Clocks (GCLK1_50, GCLK2_50,
CLKOUT)........................................................................................................ 14-12
14.3.1.3 CLKOUT Special Considerations: 1:2:1 Mode...................................................14-14
14.3.1.4 The Baud Rate Generator Clock (BRGCLK)...................................................... 14-15
14.3.1.5 The Synchronization Clock (SYNCCLK, SYNCCLKS)....................................14-15
14.3.2 The PIT and RTC Clock (PITRTCLK).................................................................... 14-16
14.3.3 The Time Base and Decrementer Clock (TMBCLK).............................................. 14-17
14.4 Power Distribution....................................................................................................... 14-17
14.4.1 I/O Buffer Power (VDDH) ...................................................................................... 14-18
14.4.2 Internal Logic Power (VDDL)................................................................................. 14-19
14.4.3 Clock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1).................................. 14-19
14.4.4 Keep-Alive Power (KAPWR) ................................................................................. 14-19
14.5 Power Control (Low-Power Modes)............................................................................ 14-19
14.5.1 Normal High Mode.................................................................................................. 14-23
14.5.2 Normal Low Mode................................................................................................... 14-23
14.5.3 Doze High Mode...................................................................................................... 14-23
14.5.4 Doze Low Mode ...................................................................................................... 14-24
14.5.5 Sleep Mode .............................................................................................................. 14-25
14.5.6 Deep-Sleep Mode .................................................................................................... 14-25
14.5.7 Power-Down Mode.................................................................................................. 14-26
14.5.7.1 Software Initiation of Power-Down Mode, with Automatic Wake-Up...............14-26
14.5.7.2 Maintaining the Real-Time Clock (RTC) During Shutdown or Power Failure...14-28
14.5.7.3 Register Lock Mechanism: Protecting SIU Registers in Power-Down Mode..... 14-28
14.5.8 TMIST: Facilitating Nesting of SIU Timer Interrupts............................................. 14-29
14.6 Clock and Power Control Registers............................................................................. 14-29
14.6.1 System Clock and Reset Control Register (SCCR).................................................14-29
14.6.2 PLL, Low-Power, and Reset Control Register (PLPRCR)......................................14-32
Chapter 15
Memory Controller
15.1 Features..........................................................................................................................15-1
15.2 Basic Architecture.......................................................................................................... 15-3
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15.3 Chip-Select Programming Common to the GPCM and UPM.......................................15-6
15.3.1 Address Space Programming.....................................................................................15-7
15.3.2 Register Programming Order..................................................................................... 15-7
15.3.3 Memory Bank Write Protection................................................................................. 15-7
15.3.4 Address Type Protection............................................................................................ 15-7
15.3.5 8-, 16-, and 32-Bit Port Size Configuration............................................................... 15-7
15.3.6 Parity Configuration .................................................................................................. 15-8
15.3.7 Memory Bank Protection Status................................................................................ 15-8
15.3.8 UPM-Specific Registers ............................................................................................ 15-8
15.3.9 GPCM-Specific Registers.......................................................................................... 15-8
15.4 Register Descriptions..................................................................................................... 15-9
15.4.1 Base Registers (BRx)................................................................................................. 15-9
15.4.2 Option Registers (ORx) ........................................................................................... 15-10
15.4.3 Memory Status Register (MSTAT).......................................................................... 15-13
15.4.4 Machine A Mode Register/Machine B Mode Registers (MxMR) .......................... 15-13
15.4.5 Memory Command Register (MCR)....................................................................... 15-15
15.4.6 Memory Data Register (MDR)................................................................................ 15-17
15.4.7 Memory Address Register (MAR) .......................................................................... 15-17
15.4.8 Memory Periodic Timer Prescaler Register (MPTPR)............................................ 15-18
15.5 General-Purpose Chip-Select Machine (GPCM).........................................................15-18
15.5.1 Timing Configuration .............................................................................................. 15-19
15.5.1.1 Chip-Select Assertion Timing .............................................................................15-20
15.5.1.2 Chip-Select and Write Enable Deassertion Timing.............................................15-21
15.5.1.3 Relaxed Timing.................................................................................................... 15-23
15.5.1.4 Output Enable (OE) Timing ................................................................................ 15-26
15.5.1.5 Programmable Wait State Configuration............................................................. 15-26
15.5.1.6 Extended Hold Time on Read Accesses.............................................................. 15-26
15.5.2 Boot Chip-Select Operation..................................................................................... 15-29
15.5.3 External Asynchronous Master Support.................................................................. 15-30
15.5.4 Special Case: Bursting with External Transfer Acknowledge:................................ 15-31
15.6 User-Programmable Machines (UPMs)....................................................................... 15-32
15.6.1 Requests................................................................................................................... 15-33
15.6.1.1 Internal/External Memory Access Requests........................................................ 15-34
15.6.1.2 UPM Periodic Timer Requests ............................................................................ 15-34
15.6.1.3 Software Requests—MCR RUN Command.........................................................15-35
15.6.1.4 Exception Requests.............................................................................................. 15-35
15.6.2 Programming the UPM............................................................................................ 15-35
15.6.3 Control Signal Generation Timing........................................................................... 15-36
15.6.4 The RAM Array....................................................................................................... 15-38
15.6.4.1 RAM Words......................................................................................................... 15-39
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15.6.4.2 Chip-Select Signals (CSTx)................................................................................. 15-42
15.6.4.3 Byte-Select Signals (BSTx)................................................................................. 15-43
15.6.4.4 General-Purpose Signals (GxTx, G0x)................................................................ 15-44
15.6.4.5 Loop Control (LOOP)..........................................................................................15-46
15.6.4.6 Exception Pattern Entry (EXEN)......................................................................... 15-47
15.6.4.7 Address Multiplexing (AMX) ............................................................................. 15-47
15.6.4.8 Transfer Acknowledge and Data Sample Control (UTA, DLT3)........................ 15-51
15.6.4.9 Disable Timer Mechanism (TODT)..................................................................... 15-52
15.6.4.10 The Last Word (LAST)........................................................................................ 15-52
15.6.4.11 Wait Mechanism (WAEN)................................................................................... 15-52
15.6.4.11.1 Internal and External Synchronous Masters.................................................... 15-53
15.6.4.11.2 External Asynchronous Masters...................................................................... 15-53
15.7 Handling Devices with Slow or Variable Access Times.............................................. 15-54
15.7.1 Hierarchical Bus Interface Example........................................................................ 15-55
15.7.2 Slow Devices Example............................................................................................ 15-55
15.8 External Master Support.............................................................................................. 15-55
15.8.1 Synchronous External Masters ................................................................................ 15-56
15.8.2 Asynchronous External Masters.............................................................................. 15-56
15.8.3 Special Case: Address Type Signals for External Masters......................................15-56
15.8.4 UPM Features Supporting External Masters........................................................... 15-56
15.8.4.1 Address Incrementing for External Synchronous Bursting Masters ................... 15-57
15.8.4.2 Handshake Mechanism for Asynchronous External Masters.............................. 15-57
15.8.4.3 Special Signal for External Address Multiplexer Control...................................15-57
15.8.5 External Master Examples....................................................................................... 15-57
15.8.5.1 External Masters and the GPCM......................................................................... 15-57
15.8.5.2 External Masters and the UPM............................................................................ 15-59
15.9 Memory System Interface Examples........................................................................... 15-64
15.9.1 Page-Mode DRAM Interface Example.................................................................... 15-64
15.9.2 Page Mode Extended Data-Out Interface Example................................................. 15-75
Chapter 16
PCMCIA Interface
16.1 System Configuration .................................................................................................... 16-1
16.2 PCMCIA Module Signal Definitions ............................................................................ 16-1
16.2.1 PCMCIA Cycle Control Signals................................................................................ 16-2
16.2.2 PCMCIA Input Port Signals ...................................................................................... 16-4
16.2.3 PCMCIA Output Port Signals (OP[0–4]).................................................................. 16-5
16.2.4 Other PCMCIA Signals ............................................................................................. 16-5
16.3 Operation Description.................................................................................................... 16-5
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16.3.1 Memory-Only Cards.................................................................................................. 16-5
16.3.2 I/O Cards.................................................................................................................... 16-6
16.3.3 Interrupts....................................................................................................................16-6
16.3.4 Power Control............................................................................................................ 16-7
16.3.5 Reset and Three-State Control................................................................................... 16-7
16.3.6 DMA.......................................................................................................................... 16-7
16.4 Programming Model...................................................................................................... 16-8
16.4.1 PCMCIA Interface Input Pins Register (PIPR).........................................................16-8
16.4.2 PCMCIA Interface Status Changed Register (PSCR) ...............................................16-9
16.4.3 PCMCIA Interface Enable Register (PER) ............................................................. 16-11
16.4.4 PCMCIA Interface General Control Register (PGCRx).......................................... 16-12
16.4.5 PCMCIA Base Registers 0–7 (PBR0–PBR7).......................................................... 16-13
16.4.6 PCMCIA Option Register 0–7 (POR0–POR7) .......................................................16-14
16.5 PCMCIA Controller Timing Examples ....................................................................... 16-17
Part V
Communications Processor Module
Chapter 17
Communications Processor Module and CPM Timers
17.1 Features..........................................................................................................................17-2
17.2 CPM General-Purpose Timers....................................................................................... 17-4
17.2.1 Features......................................................................................................................17-5
17.2.2 CPM Timer Operation ............................................................................................... 17-6
17.2.2.1 Timer Clock Source............................................................................................... 17-6
17.2.2.2 Timer Reference Count.......................................................................................... 17-6
17.2.2.3 Timer Capture........................................................................................................ 17-6
17.2.2.4 Timer Gating.......................................................................................................... 17-7
17.2.2.5 Cascaded Mode...................................................................................................... 17-7
17.2.2.6 Timer 1 and SPKROUT......................................................................................... 17-8
17.2.3 CPM Timer Register Set............................................................................................ 17-8
17.2.3.1 Timer Global Configuration Register (TGCR)...................................................... 17-8
17.2.4 Timer Mode Registers (TMR1–TMR4)..................................................................... 17-9
17.2.4.1 Timer Reference Registers (TRR1–TRR4) ......................................................... 17-10
17.2.4.2 Timer Capture Registers (TCR1–TCR4)............................................................. 17-11
17.2.4.3 Timer Counter Registers (TCN1–TCN4) ............................................................ 17-11
17.2.4.4 Timer Event Registers (TER1–TER4)................................................................. 17-12
17.2.5 Timer Initialization Examples..................................................................................17-12
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NXP MPC860 Reference guide

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Reference guide

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