Motorola MPC823E Reference guide

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Reference Manual

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Acknowledgments

The MPC823e Support Team would like to thank the following people for their

contribution to the success of the MPC823e:

Art Miller, CW Clark, Ken Edwards, Kevin Owen, Ray Burgess, Tom Gunter, John Round, Mike Shoemake,

James Wilson, Chris Lines, Ricardo Berger, Yehuda Rudin, Yair Liebman, Udi Barel, the rest of the Israel

design team, Stu Werbner, Tiffany Huling-Broadous, John Dailey, Lan Nguyen, Richard Hendricks,

Darcy Volden, Trish Sierer, Arnaldo Cruz, Danny Nguyen, Myle Buchanan, Joseph Mayfield, Rodolfo Guillen,

the rest of the product/test engineering team, Brian McCalley, Alan Weiss, Steve Rosebaugh, Jasmine Hsiao,

Mike Collier, John Southard, Joseph Lee, Pat Carr, Mark VandenBrink, the rest of the Systems Software team,

Yoichi Kimura, Yuzo Kuramochi, Tanamachi Goro, Fumihiko Kondo, Keiji Momozaki, Jean-Paul Davi,

Per-Eric Josefsson, Rodney Watt, Axel Streicher, Pierre Juste, Gary Segal, Mark DiPerri, Kurt Miller,

Steve Shoap, Rob Wackerman, Rick Heider, Gary Wilson, Thomas Yeh, Bill Durrenberger, Dave Hyder,

the rest of the Field Applications Engineering/Sales support team, Pamela Mitchell, Nina Friedman,

the rest of the Technical Information Center support team, Dan Malek, Jim Belesiu, Clark Liang, Ronny

Svensson, Mark Wagner, Bulent Egilmez, Kurt Fuqua, Robert Applebaum, Nick Vaccaro, Weifu Shi,

Roozbeh Ghorishi, Robert Ritchey, Brad Scott, Dan Malek, the rest of our customers,

the gang at comp.sys.powerpc.tech and linuxppc-embedded, and to many others.

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TABLE OF CONTENTS

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Section 1

Introduction

1.1 Features ................................................................................................1-1

1.2 Architecture ...........................................................................................1-6

1.2.1 The Embedded PowerPC Core ..................................................1-8

1.2.2 The System Interface Unit ..........................................................1-8

1.2.3 The Communication Processor Module .....................................1-9

1.2.4 The Video/LCD Controller ........................................................1-10

1.2.4.1 The Video Controller .....................................................1-10

1.2.4.2 The LCD Controller .......................................................1-10

1.3 The PCMCIA-ATA Controller ..............................................................1-10

1.4 Power Management ............................................................................1-11

1.5 System Debug Support .......................................................................1-11

1.6 Applications .........................................................................................1-11

1.7 Differences Between MPC823 (Rev B) and MPC823e .......................1-12

1.8 MPC823e Glueless System Design ....................................................1-12

Section 2

External Signals

2.1 The System Bus Signals .......................................................................2-2

Section 3

Memory Map

Section 4

Reset

4.1 Types of Reset ......................................................................................4-2

4.1.1 Power-On Reset .........................................................................4-2

4.1.2 External Hard Reset ...................................................................4-3

4.1.3 Internal Hard Reset ....................................................................4-3

4.1.3.1 Loss of Lock ....................................................................4-3

4.1.3.2 Software Watchdog Reset ..............................................4-3

4.1.3.3 Checkstop Reset ............................................................4-3

4.1.3.4 Debug Port Hard Reset ..................................................4-4

4.1.3.5 JTAG Reset ....................................................................4-4

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4.1.4 External Soft Reset ....................................................................4-4

4.1.5 Internal Soft Reset .....................................................................4-4

4.1.5.1 Debug Port Soft Reset ....................................................4-4

4.2 Reset Status Register ...........................................................................4-5

4.3 How to Configure Reset ........................................................................4-7

4.3.1 Hard Reset .................................................................................4-7

4.3.1.1 Hard Reset Configuration Word ...................................4-10

4.3.2 Soft Reset ................................................................................4-12

Section 5

Clocks and Power Control

5.1 Features ................................................................................................5-1

5.2 Register Model ......................................................................................5-3

5.2.1 System Clock and Reset Control Register .................................5-3

5.2.2 PLL, Low-Power, and Reset Control Register ...........................5-7

5.3 The Clock Module ...............................................................................5-10

5.3.1 On-Chip Oscillators and External Clock Input ..........................5-12

5.3.2 System PLL ..............................................................................5-12

5.3.2.1 SPLL Stability ...............................................................5-13

5.3.3 The Low-Power Clock Divider ..................................................5-14

5.3.4 Internal Clock Signals ..............................................................5-16

5.3.4.1 The General System Clocks .........................................5-16

5.3.4.2 The Baud Rate Generator Clock ..................................5-19

5.3.4.3 The Synchronization Clocks .........................................5-20

5.3.4.4 The LCD Clocks ...........................................................5-21

5.3.5 Clock Configuration ..................................................................5-22

5.3.5.1 Mode Clock Pins ...........................................................5-22

5.3.5.2 The System Phase-Locked Loop Pins .........................5-23

5.4 Power Control .....................................................................................5-24

5.4.1 Power Rails ..............................................................................5-24

5.4.2 Keep-Alive Power .....................................................................5-25

5.4.2.1 Power Switching Example ............................................5-26

5.4.2.2 Register Lock ................................................................5-27

5.5 Low-Power Operation .........................................................................5-28

Section 6

The PowerPC Core

6.1 Features ................................................................................................6-1

6.2 Basic Structure of the Core ...................................................................6-2

6.2.1 Instruction Flow Within the Core ................................................6-2

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6.2.2 Basic Instruction Pipeline ...........................................................6-4

6.3 Sequencer Unit .....................................................................................6-4

6.3.1 Flow Control ...............................................................................6-5

6.3.2 Issuing Instructions .....................................................................6-6

6.3.3 Interrupts ....................................................................................6-7

6.3.4 Implementing the Precise Exception Model ...............................6-8

6.3.4.1 Restartability After An Interrupt .....................................6-10

6.3.5 Processing an Interrupt ............................................................6-11

6.3.6 Serialization ..............................................................................6-12

6.3.6.1 Latency .........................................................................6-12

6.3.7 The External Interrupt ...............................................................6-13

6.3.7.1 Latency .........................................................................6-13

6.3.8 Interrupt Ordering .....................................................................6-14

6.4 The Register Unit ................................................................................6-15

6.4.1 Control Registers ......................................................................6-16

6.4.1.1 Physical Location of Special Registers .........................6-19

6.4.1.2 PowerPC Standard Control Register Bit Assignment....6-20

6.4.1.2.1 Machine State Register ....................................6-20

6.4.1.2.2 The Condition Register ....................................6-22

6.4.1.2.3 Fixed-Point Exception Cause Register ............6-23

6.4.1.3 Initializing the Control Registers ...................................6-24

6.4.1.3.1 System Reset Interrupt ....................................6-24

6.4.1.3.2 Hard/Soft Reset ................................................6-24

6.5 The Fixed-Point Unit ...........................................................................6-24

6.5.1 XER Update In Divide Instructions ...........................................6-24

6.6 The Load/Store Unit ............................................................................6-25

6.6.1 Issuing Load/Store Instructions ................................................6-26

6.6.2 Serializing Load/Store Instructions ...........................................6-27

6.6.3 Instructions Issued to the Data Cache .....................................6-27

6.6.4 Issuing Store Instruction Cycles ...............................................6-27

6.6.5 Issuing Nonspeculative Load Instructions ................................6-27

6.6.6 Executing Unaligned Instructions .............................................6-28

6.6.7 Little-Endian Mode Support ......................................................6-29

6.6.8 Atomic Update Primitives .........................................................6-29

6.6.9 Instruction Timing .....................................................................6-30

6.6.10 Stalling Storage Control Instructions ........................................6-30

6.6.11 Accessing Off-Core Special Registers .....................................6-30

6.6.12 Storage Control Instructions .....................................................6-31

6.6.13 Exceptions ................................................................................6-31

6.6.13.1 DAR, DSISR, and BAR Operation ................................6-31

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PowerPC Architecture Compliance

7.1 PowerPC User Instruction Set Architecture (Book I) ............................7-1

7.1.1 Computation Modes ...................................................................7-1

7.1.2 Reserved Fields .........................................................................7-1

7.1.3 Classes of Instructions ...............................................................7-1

7.1.4 Exceptions ..................................................................................7-2

7.1.5 The Branch Processor ...............................................................7-2

7.1.6 Fetching Instructions ..................................................................7-2

7.1.7 Branch Instructions ....................................................................7-2

7.1.7.1 Invalid Branch Instruction Forms ....................................7-2

7.1.7.2 Branch Prediction ...........................................................7-2

7.1.8 The Fixed-Point Processor .........................................................7-2

7.1.8.1 Move To/From System Register Instructions .................7-3

7.1.8.2 Fixed-Point Arithmetic Instructions .................................7-3

7.1.9 The Load/Store Processor .........................................................7-3

7.1.9.1 Fixed-Point Load With Update and Store

With Update Instructions ................................................7-3

7.1.9.2 Fixed-Point Load and Store Multiple Instructions ...........7-3

7.1.9.3 Fixed-Point Load String Instructions ...............................7-3

7.1.9.4 Storage Synchronization Instructions .............................7-4

7.1.9.5 Optional Instructions .......................................................7-4

7.1.9.6 Little-Endian Byte Ordering ............................................7-4

7.2 PowerPC Virtual Environment Architecture (Book II) ............................7-4

7.2.1 Storage Model ............................................................................7-4

7.2.1.1 Memory Coherence ........................................................7-4

7.2.1.2 Atomic Update Primitives ...............................................7-4

7.2.2 The Effect Of Operand Placement on Performance ..................7-5

7.2.3 The Storage Control Instructions ...............................................7-5

7.2.4 Timebase ...................................................................................7-6

7.3 PowerPC Operating Environment Architecture (Book III) .....................7-6

7.3.1 The Branch Processor ...............................................................7-6

7.3.1.1 Machine State Register ..................................................7-6

7.3.1.2 Processor Version Register ............................................7-6

7.3.1.3 Branch Processors Instructions ......................................7-6

7.3.2 The Fixed-Point Processor .........................................................7-6

7.3.2.1 Unsupported Registers ...................................................7-6

7.3.2.2 Added Registers .............................................................7-6

7.3.3 Storage Model ............................................................................7-6

7.3.3.1 Address Translation ........................................................7-6

7.3.4 Reference and Change Bits .......................................................7-7

7.3.5 Storage Protection .....................................................................7-7

7.3.6 Storage Control Instructions .......................................................7-7

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7.3.6.1 Data Cache Block Invalidate (dcbi) .................................7-7

7.3.6.2 TLB Invalidate Entry (tlbie) .............................................7-7

7.3.6.3 TLB Invalidate All (tlbia) ..................................................7-7

7.3.6.4 TLB Synchronize (tlbsync) ..............................................7-7

7.3.7 Interrupts ....................................................................................7-7

7.3.7.1 Classes ...........................................................................7-7

7.3.7.2 Processing ......................................................................7-8

7.3.7.3 Definitions .......................................................................7-8

7.3.7.3.1 System Reset Interrupt ......................................7-9

7.3.7.3.2 Machine Check Interrupt ....................................7-9

7.3.7.3.3 Data Storage Interrupt ......................................7-10

7.3.7.3.4 Instruction Storage Interrupt .............................7-10

7.3.7.3.5 Alignment Interrupt ...........................................7-10

7.3.7.3.6 Program Interrupt .............................................7-11

7.3.7.3.7 Floating-Point Unavailable Interrupt .................7-11

7.3.7.3.8 Trace Interrupt ..................................................7-11

7.3.7.3.9 Floating-Point Assist Interrupt ..........................7-11

7.3.7.3.10 Implementation-Dependent Software

Emulation Interrupt ............................................7-12

7.3.7.3.11 Implementation-Specific Instruction TLB

Miss Interrupt ....................................................7-12

7.3.7.3.12 Implementation-Specific Instruction TLB

Error Interrupt ....................................................7-13

7.3.7.3.13 Implementation-Specific Data TLB Miss

Interrupt .............................................................7-14

7.3.7.3.14 Implementation-Specific Data TLB Error

Interrupt .............................................................7-14

7.3.7.3.15 Implementation-Specific Debug Register .........7-15

7.3.7.4 Partially Executed Instructions ......................................7-17

7.3.8 Timer Facilities .........................................................................7-17

7.3.9 Optional Facilities and Instructions ...........................................7-17

Section 8

Instruction Execution Timing

8.1 Instruction Timing List ...........................................................................8-1

8.2 Instruction Execution Timing Examples ................................................8-4

8.2.1 Data Cache Load .......................................................................8-4

8.2.2 Writeback ...................................................................................8-5

8.2.2.1 Writeback Arbitration ......................................................8-5

8.2.2.2 Private Writeback Bus Load ...........................................8-6

8.2.3 Fastest External Load (Data Cache Miss) ..................................8-7

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8.2.4 A Full History Buffer ...................................................................8-8

8.2.5 Branch Folding ...........................................................................8-9

8.2.6 Branch Prediction .....................................................................8-10

Section 9

Instruction Cache

9.1 Features ................................................................................................9-1

9.2 Programming the Instruction Cache .....................................................9-4

9.2.1 Instruction Cache Control and Status Register ..........................9-5

9.2.2 Instruction Cache Address Register ...........................................9-6

9.2.3 Instruction Cache Data Port Register .........................................9-7

9.3 Instruction Cache Operation .................................................................9-7

9.3.1 Instruction Cache Hit ..................................................................9-7

9.3.2 Instruction Cache Miss ...............................................................9-8

9.3.3 Instruction Fetch On A Predicted Path .......................................9-8

9.4 instruction Cache Commands ...............................................................9-8

9.4.1 Invalidating the Instruction Cache ..............................................9-9

9.4.2 Loading and Locking the Instruction Cache .............................9-10

9.4.3 Unlocking A Line ......................................................................9-10

9.4.4 Unlocking the Entire Instruction Cache ....................................9-11

9.4.5 Inhibiting the Instruction Cache ................................................9-11

9.4.6 Instruction Cache Read ............................................................9-12

9.4.7 Instruction Cache Write ............................................................9-14

9.5 Restrictions .........................................................................................9-14

9.6 Instruction Cache Coherency ..............................................................9-14

9.7 Updating Code And Memory Region Attributes ..................................9-14

9.8 Reset Sequence .................................................................................9-14

9.9 Debug Support ....................................................................................9-15

9.9.1 Fetching Instructions From The Development Port ..................9-15

Section 10

Data Cache

10.1 Features ..............................................................................................10-1

10.2 Organization of the Data Cache ..........................................................10-2

10.3 Programming the Data Cache ............................................................10-3

10.3.1 PowerPC Architecture Instructions ..........................................10-3

10.3.1.1 PowerPC User Instruction Set Architecture (Book I).....10-3

10.3.1.2 PowerPC Virtual Environment Architecture (Book II)....10-4

10.3.1.3 PowerPC Operating Environment Architecture

(Book III) .......................................................................10-4

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10.3.2 Implementation-Specific Operations ........................................10-4

10.3.3 Special Registers of the Data Cache .......................................10-4

10.3.3.1 Data Cache Control and Status Register ......................10-5

10.3.3.2 Data Cache Address Register ......................................10-7

10.3.3.3 Reading the Cache Structures ......................................10-7

10.4 Operating the Data Cache ................................................................10-10

10.4.1 Data Cache Read ...................................................................10-10

10.4.2 Data Cache Write ...................................................................10-10

10.4.2.1 Copyback Mode ..........................................................10-11

10.4.2.2 Writethrough Mode .....................................................10-12

10.4.3 Data Cache Inhibited Accesses .............................................10-12

10.4.4 Data Cache Freeze ................................................................10-12

10.4.5 Data Cache Coherency ..........................................................10-13

10.5 Data Cache Commands ....................................................................10-13

10.5.1 Flushing and Invalidating the Cache ......................................10-13

10.5.2 Enabling and Disabling the Cache .........................................10-13

10.5.3 Locking and Unlocking the Cache ..........................................10-13

10.5.4 Data Cache Instructions .........................................................10-14

10.5.4.1 dcbi, dcbst, dcbf And dcbz Instructions ......................10-14

10.5.4.2 Touch ..........................................................................10-14

10.5.4.3 Storage Synchronization/Reservation ........................10-14

10.5.5 Data Cache Read ...................................................................10-14

Section 11

Memory Management Unit

11.1 Features ..............................................................................................11-1

11.2 Address Translation ............................................................................11-2

11.2.1 Translation Lookaside Buffer Operation ...................................11-2

11.3 Protection ............................................................................................11-3

11.4 Storage Control ...................................................................................11-4

11.5 Translation Table Structure .................................................................11-5

11.5.1 Level One Descriptor ................................................................11-9

11.5.2 Level Two Descriptor ..............................................................11-10

11.6 Programming the Memory Management Unit ...................................11-15

11.6.1 Control Registers ....................................................................11-16

11.6.1.1 MMU Instruction Control Register ...............................11-16

11.6.1.2 MMU Data Control Register ........................................11-17

11.6.1.3 MMU Current Address Space ID Register ..................11-18

11.6.1.4 MMU Instruction Effective Page Number Register .....11-19

11.6.1.5 MMU Data Effective Page Number Register ..............11-20

11.6.1.6 MMU Instruction Real Page Number Register ............11-21

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11.6.1.7 MMU Data Real Page Number Register ....................11-26

11.6.1.8 MMU Instruction Access Protection Register .............11-31

11.6.1.9 MMU Data Access Protection Register ......................11-32

11.6.1.10 MMU Instruction Tablewalk Control Register .............11-33

11.6.1.11 MMU Data Tablewalk Control Register ......................11-34

11.6.1.12 MMU Tablewalk Base Register ..................................11-36

11.6.1.13 MMU Tablewalk Special Register ...............................11-37

11.6.2 MMU Data Content-Addressable Registers ...........................11-37

11.6.2.1 MMU Data CAM Entry Read Register ........................11-38

11.6.2.2 MMU Data RAM Entry Read Register 0 .....................11-39

11.6.2.3 MMU Data RAM Entry Read Register 1 .....................11-41

11.6.3 MMU Instruction Content-Addressable Registers ..................11-43

11.6.3.1 MMU Instruction CAM Entry Read Register ...............11-43

11.6.3.2 MMU Instruction RAM Entry Read Register 0 ............11-45

11.6.3.3 MMU Instruction RAM Entry Read Register 1 ............11-46

11.7 Interrupts ...........................................................................................11-47

11.7.1 Implementation-Specific Instruction TLB Miss .......................11-47

11.7.2 Implementation-Specific Data TLB Miss ................................11-47

11.7.3 Implementation-Specific Instruction TLB Error .......................11-48

11.7.4 Implementation-Specific Data TLB Error ................................11-48

11.8 Manipulating the Translation Lookaside Buffer .................................11-49

11.8.1 Reloading the Translation Lookaside Buffer ..........................11-49

11.8.1.1 Translation Reload Examples .....................................11-50

11.8.2 Controlling the TLB Replacement Counter ............................11-51

11.8.3 Invalidating the Translation Lookaside Buffer ........................11-51

11.8.4 Loading the Reserved TLB Entries ........................................11-51

11.9 Requirements For Accessing The Memory Management Unit

Control Registers ..............................................................................11-52

Section 12

System Interface Unit

12.1 Features ..............................................................................................12-2

12.2 System Configuration and Protection .................................................12-2

12.3 Interrupt Configuration ........................................................................12-5

12.3.1 The Interrupt Structure .............................................................12-5

12.3.2 Priority of the Interrupt Sources ...............................................12-6

12.3.3 Programming the Interrupt Controller .......................................12-7

12.3.3.1 SIU Interrupt Pending Register .....................................12-7

12.3.3.2 SIU Interrupt Mask Register .........................................12-8

12.3.3.3 SIU Interrupt Edge/Level Register ................................12-9

12.3.3.4 SIU Interrupt Vector Register .....................................12-10

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12.4 The Bus Monitor ................................................................................12-11

12.5 The PowerPC Decrementer ..............................................................12-12

12.5.1 Decrementer Register ............................................................12-13

12.6 The PowerPC Timebase ...................................................................12-14

12.6.1 Timebase Register .................................................................12-14

12.6.2 Timebase Reference Registers ..............................................12-15

12.6.3 Timebase Status and Control Register ..................................12-16

12.7 The Real-Time Clock ........................................................................12-17

12.7.1 Real-Time Clock Status and Control Register ........................12-18

12.7.2 Real-Time Clock Register ......................................................12-19

12.7.3 Real-Time Clock Alarm Seconds Register .............................12-20

12.7.4 Real-Time Clock Alarm Register ............................................12-21

12.8 The Periodic Interrupt Timer .............................................................12-22

12.8.1 Periodic Interrupt Status and Control Register .......................12-23

12.8.2 Periodic Interrupt Timer Count Register .................................12-24

12.8.3 Periodic Interrupt Timer Register ...........................................12-25

12.9 The Software Watchdog Timer .........................................................12-26

12.9.1 Software Service Register ......................................................12-27

12.10 Freeze Operation ..............................................................................12-28

12.10.1 Low-Power Stop Operation ....................................................12-28

12.11 Multiplexing the System Interface Unit Pins ......................................12-29

12.12 Programming the System Interface Unit ...........................................12-30

12.12.1 System Configuration and Protection Registers .....................12-30

12.12.1.1 SIU Module Configuration Register ............................12-30

12.12.1.2 Internal Memory Map Register ...................................12-34

12.12.1.3 System Protection Control Register ............................12-35

12.12.1.4 Transfer Error Status Register ....................................12-36

Section 13

External Bus Interface

13.1 Features ..............................................................................................13-1

13.2 Transfer Signals ..................................................................................13-1

13.2.1 Control Signals .........................................................................13-3

13.3 Bus Signal Descriptions ......................................................................13-4

13.4 Bus Interface Operation ......................................................................13-7

13.4.1 Basic Transfers ........................................................................13-8

13.4.2 Single Beat Transfers ...............................................................13-8

13.4.2.1 Single Beat Read Flow .................................................13-9

13.4.2.2 Single Beat Write Flow ...............................................13-12

13.4.3 Burst Transfers .......................................................................13-16

13.4.4 The Burst Mechanism ............................................................13-16

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13.4.5 Transfer Alignment and Packaging ........................................13-25

13.4.6 Arbitration Phase-Related Signals .........................................13-27

13.4.6.1 Bus Request Signal ....................................................13-28

13.4.6.2 Bus Grant Signal ........................................................13-29

13.4.6.3 Bus Busy Signal .........................................................13-29

13.4.7 Address Transfer Phase-Related Signals ..............................13-31

13.4.7.1 Transfer Start Signal ...................................................13-31

13.4.7.2 Address Bus ...............................................................13-32

13.4.7.3 Transfer Attributes ......................................................13-32

13.4.7.3.1 Read/Write Signal ..........................................13-32

13.4.7.3.2 Burst Signal ....................................................13-32

13.4.7.3.3 Transfer Size Signal .......................................13-33

13.4.7.3.4 Address Space Attributes ..............................13-33

13.4.7.3.5 Special Transfer Start Signal .........................13-33

13.4.7.3.6 Burst Data in Progress Signal ........................13-36

13.4.8 Data Transfer Phase-Related Signals ....................................13-36

13.4.8.1 Data Signal .................................................................13-36

13.4.9 Termination Phase-Related Signals .......................................13-36

13.4.9.1 Transfer Acknowledge Signal .....................................13-36

13.4.9.2 Burst Inhibit Signal ......................................................13-36

13.4.9.3 Transfer Error Acknowledge Signal ............................13-36

13.4.9.4 Protocol for Termination Signals ................................13-37

13.4.10 Storage Reservation Protocol ................................................13-38

13.4.11 Exception Control Cycles .......................................................13-41

13.4.11.1 RETRY Signal ............................................................13-42

Section 14

Endian Modes

14.1 Little-Endian Features .........................................................................14-3

14.2 Big-Endian System Features ..............................................................14-5

14.3 PowerPC Little-Endian System Features ............................................14-5

14.4 Setting the Endian Mode Of Operation .............................................. 14-5

Section 15

Memory Controller

15.1 Features ..............................................................................................15-1

15.2 Architecture .........................................................................................15-4

15.3 Register Model ....................................................................................15-7

15.3.1 Register Descriptions ...............................................................15-9

15.3.1.1 Base Registers .............................................................15-9

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15.3.1.2 Option Registers .........................................................15-11

15.3.1.3 Memory Status Register .............................................15-15

15.3.1.4 Memory Command Register .......................................15-17

15.3.1.5 Machine A Mode Register ..........................................15-19

15.3.1.6 Machine B Mode Register ..........................................15-22

15.3.1.7 Memory Data Register ................................................15-26

15.3.1.8 Memory Address Register ..........................................15-26

15.3.1.9 Memory Periodic Timer Prescaler Register ................15-27

15.4 The General-Purpose Chip-Select Machine .....................................15-27

15.4.1 Configuration ..........................................................................15-27

15.4.1.1 Programmable Wait State Configuration ....................15-34

15.4.1.2 Extended Hold Time on Read Accesses ....................15-34

15.4.1.3 Boot Chip-Select Operation ........................................15-37

15.4.1.4 SRAM Interface ..........................................................15-38

15.4.1.5 External Asynchronous Master support ......................15-38

15.5 User-Programmable Machines .........................................................15-41

15.5.1 Requests ................................................................................15-42

15.5.1.1 Internal/External Memory Access Requests ...............15-43

15.5.1.2 Memory Periodic Timer Requests ..............................15-43

15.5.1.3 Software Requests .....................................................15-44

15.5.1.4 Exception Requests ....................................................15-44

15.5.2 Programming the User-Programmable Machine ....................15-44

15.5.3 Clock Timing ...........................................................................15-45

15.5.4 The RAM Array .......................................................................15-49

15.5.4.1 The RAM Word ...........................................................15-50

15.5.4.1.1 RAM Word Format .........................................15-50

15.5.4.2 RAM Word Operation .................................................15-55

15.5.4.2.1 Start Addresses ..............................................15-55

15.5.4.2.2 Chip-Select Signals ........................................15-56

15.5.4.2.3 Byte-Select Signals ........................................15-57

15.5.4.2.4 General-Purpose Signals ...............................15-59

15.5.4.2.5 Loop Control ...................................................15-60

15.5.4.2.6 Exception Handling ........................................15-60

15.5.4.2.7 Address Multiplexing ......................................15-61

15.5.4.2.8 Transfer Acknowledge and Data Sample

Control ............................................................15-65

15.5.4.2.9 Disable Timer Mechanism ..............................15-65

15.5.4.2.10 Last Word .......................................................15-65

15.5.5 The Wait Mechanism ..............................................................15-66

15.5.5.1 Internal and External Synchronous Master .................15-66

15.5.5.2 External Asynchronous Master ...................................15-67

15.5.5.3 Handling Variable Access Time and Slow Devices ....15-68

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15.5.5.3.1 Hierarchical Bus Interface Example ...............15-68

15.5.5.3.2 Slow Device Interface Example .....................15-68

15.6 External Master Support ...................................................................15-69

15.6.1 External Master Examples .....................................................15-73

15.6.1.1 Memory System Interface Examples ..........................15-77

15.6.2 Page Mode DRAM Interface Example ...................................15-77

15.6.3 Page Mode Extended Data-Out DRAM Interface Example ....15-89

Section 16

Communication Processor Module

16.1 Features ..............................................................................................16-1

16.2 The RISC Microcontroller ....................................................................16-4

16.2.1 RISC Microcontroller Features .................................................16-5

16.2.2 Communication Between the Microcontroller and Core ...........16-6

16.2.3 Communication Between the Microcontroller

and Peripherals .........................................................................16-6

16.2.4 Executing Microcode From RAM or ROM ................................16-7

16.2.5 RISC Configuration and Control Registers ..............................16-7

16.2.6 RISC Microcontroller Commands .............................................16-9

16.2.6.1 CPM Command Register ..............................................16-9

16.2.6.2 Command Definitions .................................................16-11

16.2.6.2.1 CPM Command Register Example ................16-13

16.2.6.3 Dual-Port RAM ...........................................................16-13

16.2.6.3.1 Buffer Descriptors ..........................................16-15

16.2.6.3.2 Parameter RAM .............................................16-15

16.2.6.4 The RISC Timer Tables ..............................................16-17

16.2.6.4.1 RISC Timer Table Parameter RAM

Memory Map ...................................................16-18

16.2.6.4.2 RISC Timer Table Entries ..............................16-22

16.2.6.4.3 The SET TIMER Command ...........................16-22

16.2.6.4.4 PWM Mode ....................................................16-22

16.2.6.5 RISC Timer Event Register ........................................16-23

16.2.6.6 RISC Timer Mask Register .........................................16-23

16.2.6.7 RISC Timer Initialization Sequence Example .............16-24

16.2.6.8 RISC Timer Interrupt Handling Example ....................16-25

16.2.6.9 RISC Timer Table Algorithm .......................................16-25

16.2.6.10 Using the Timers to Track Microcontroller Loading.....16-25

16.3 Digital Signal Processing ..................................................................16-26

16.3.1 Features .................................................................................16-26

16.3.2 DSP Operation .......................................................................16-26

16.3.2.1 Hardware ....................................................................16-27

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16.3.2.2 Software ......................................................................16-27

16.3.2.3 Firmware .....................................................................16-27

16.3.3 Programming the DSP Functions ...........................................16-27

16.3.3.1 Data Representation ...................................................16-28

16.3.3.2 Modulo Addressing .....................................................16-29

16.3.3.2.1 DSP Function Descriptors ..............................16-29

16.3.3.2.2 DSP Parameter RAM Memory Map ...............16-30

16.3.3.2.3 DSP Commands ............................................16-32

16.3.3.3 DSP Event Register ....................................................16-33

16.3.3.4 DSP Mask Register ....................................................16-34

16.3.3.5 DSP Implementation ...................................................16-35

16.3.3.5.1 DSP Programming Example (Core Only) .......16-36

16.3.3.5.2 DSP Programming Example

(Core and CPM) ..............................................16-37

16.3.4 DSP On-Chip Library Functions .............................................16-38

16.3.4.1 FIR1–Real C, Real X, and Real Y ..............................16-39

16.3.4.1.1 Coefficients and Sample Data Buffers ...........16-39

16.3.4.1.2 FIR1 Function Descriptor ...............................16-40

16.3.4.1.3 FIR1 Parameter Packet ..................................16-41

16.3.4.1.4 Application Example .......................................16-41

16.3.4.2 FIR2–Real C, Complex X, and Complex Y .................16-42

16.3.4.2.1 Coefficients and Sample Data Buffers ...........16-42

16.3.4.2.2 FIR2 Function Descriptor ...............................16-43

16.3.4.2.3 FIR2 Parameter Packet ..................................16-45

16.3.4.2.4 Application Example .......................................16-45

16.3.4.3 FIR3–Complex C, Complex X, and

Real/Complex Y .........................................................16-46

16.3.4.3.1 Coefficients and Sample Data Buffers ...........16-47

16.3.4.3.2 FIR3 Function Descriptor ...............................16-47

16.3.4.3.3 FIR3 Parameter Packet ..................................16-49

16.3.4.3.4 Application Example .......................................16-49

16.3.4.4 FIR5–Complex C, Complex X, and Complex Y ..........16-50

16.3.4.4.1 Coefficients and Sample Data Buffers ...........16-50

16.3.4.4.2 FIR5 Function Descriptor ...............................16-51

16.3.4.4.3 FIR5 Parameter Packet ..................................16-53

16.3.4.4.4 Application Example .......................................16-53

16.3.4.5 FIR6–Complex C, Real X, and Complex Y .................16-54

16.3.4.5.1 Coefficients and Sample Data Buffers ...........16-54

16.3.4.5.2 FIR6 Function Descriptor ...............................16-55

16.3.4.5.3 FIR6 Parameter Packet ..................................16-57

16.3.4.6 IIR–Real C, Real X, Real Y .........................................16-57

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16.3.4.6.1 Coefficients and Sample Data Buffers ...........16-57

16.3.4.6.2 IIR Function Descriptor ..................................16-58

16.3.4.6.3 IIR Parameter Packet .....................................16-59

16.3.4.6.4 Application Example ......................................16-59

16.3.4.7 MOD–Real Sin, Real Cos, Complex X, and

Real/Complex Y ..........................................................16-60

16.3.4.7.1 Modulation Table and Sample Data Buffers ..16-60

16.3.4.7.2 MOD Function Descriptor ..............................16-61

16.3.4.7.3 MOD Parameter Packet .................................16-62

16.3.4.7.4 Application Example ......................................16-62

16.3.4.8 DEMOD–Real Sin; Real Cos, Real X, and

Complex Y ..................................................................16-62

16.3.4.8.1 Modulation Table, Sample Data Buffers,

and AGC Constant .........................................16-63

16.3.4.8.2 DEMOD Function Descriptor .........................16-63

16.3.4.8.3 DEMOD Parameter Packet ............................16-64

16.3.4.8.4 Application Example ......................................16-65

16.3.4.9 LMS1–Complex Coefficients, Complex Samples,

and Real/Complex Scalar ...........................................16-65

16.3.4.9.1 Coefficients and Sample Data Buffers ...........16-65

16.3.4.9.2 LMS1 Function Descriptor .............................16-66

16.3.4.9.3 LMS1 Parameter Packet ................................16-67

16.3.4.9.4 Application Example ......................................16-67

16.3.4.10 LMS2–Complex Coefficients, Complex Samples,

and Real/Complex Scalar ...........................................16-67

16.3.4.10.1 Coefficients and Sample Data Buffers ...........16-68

16.3.4.10.2 LMS2 Function Descriptor .............................16-68

16.3.4.10.3 LMS2 Parameter Packet ................................16-70

16.3.4.10.4 Application Example ......................................16-70

16.3.4.11 WADD–Real X and Real Y .........................................16-70

16.3.4.11.1 Coefficients and Sample Data Buffers ...........16-71

16.3.4.11.2 WADD Function Descriptor ............................16-71

16.3.4.11.3 WADD Parameter Packet ..............................16-72

16.3.4.11.4 Application Example ......................................16-73

16.3.4.12 The DSP Execution Times .........................................16-73

16.4 Timers ...............................................................................................16-75

16.4.1 Features .................................................................................16-75

16.4.2 Timer Operation .....................................................................16-76

16.4.2.1 Cascaded Mode .........................................................16-77

16.4.2.2 Timer Global Configuration Register ..........................16-78

16.4.2.3 Timer Mode Registers ................................................16-79

16.4.2.4 Timer Reference Registers .........................................16-80

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16.4.2.5 Timer Capture Registers .............................................16-81

16.4.2.6 Timer Counter Registers .............................................16-81

16.4.2.7 Timer Event Registers ................................................16-82

16.4.3 Initializing the Timers ..............................................................16-82

16.5 The SDMA Channels ........................................................................16-83

16.5.1 SDMA Bus Arbitration and Transfers .....................................16-85

16.5.2 The SDMA Registers ..............................................................16-86

16.5.2.1 SDMA Configuration Register .....................................16-86

16.5.2.2 SDMA Status Register ................................................16-88

16.5.2.3 SDMA Mask Register .................................................16-89

16.5.2.4 SDMA Address Register .............................................16-90

16.6 Emulating IDMA ................................................................................16-90

16.6.1 Features .................................................................................16-91

16.6.2 IDMA Interface Signals ...........................................................16-91

16.6.2.1 DREQx

and SDACKx .................................................16-91

16.6.3 IDMA Operation ......................................................................16-91

16.6.3.1 AutoBuffer and Buffer Chaining ..................................16-92

16.6.3.2 IDMA Parameter RAM Memory Map ..........................16-93

16.6.3.3 IDMA Status Registers ...............................................16-95

16.6.3.4 IDMA Mask Registers .................................................16-96

16.6.3.5 IDMA Buffer Descriptors .............................................16-97

16.6.3.6 IDMA Commands .....................................................16-101

16.6.3.7 Starting IDMA ...........................................................16-102

16.6.3.8 Requesting IDMA Transfers .....................................16-102

16.6.3.9 Level-Sensitive Mode ...............................................16-102

16.6.3.10 Edge-Sensitive Mode ................................................16-102

16.6.3.11 IDMA Operand Transfers ..........................................16-103

16.6.3.11.1 Transfer Identification ...................................16-103

16.6.3.11.2 Dual-Address Mode .....................................16-103

16.6.3.11.3 Single-Address Mode (Fly-By Transfers) .....16-104

16.6.3.11.4 Single-Buffer Burst Fly-By Mode ..................16-106

16.6.3.12 IDMA Status Registers .............................................16-110

16.6.3.13 IDMA Mask Registers ...............................................16-111

16.6.3.14 Single-Buffer Timing .................................................16-111

16.6.3.15 DownLoad Sequence ...............................................16-112

16.6.3.16 Bus Exceptions .........................................................16-113

16.7 The Serial Interface with Time-Slot Assigner ..................................16-113

16.7.1 Features ...............................................................................16-115

16.7.2 Configuring the Time-Slot Assigner ......................................16-115

16.7.3 Enabling Connections to the Time-Slot Assigner .................16-118

16.7.4 Serial Interface RAM Operation ...........................................16-118

16.7.4.1 One Multiplexed Channel with Static Frames ...........16-119

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16.7.4.2 One Multiplexed Channel With Dynamic Frames......16-120

16.7.4.3 Two multiplexed Channels with Static Frames..........16-121

16.7.4.4 tWO Multiplexed Channels With Dynamic Frames....16-122

16.7.4.5 Programming the Serial Interface RAM Entries ........16-123

16.7.4.6 Serial Interface RAM Dynamic Changes ..................16-126

16.7.5 Serial Interface Programming Model ....................................16-129

16.7.5.1 Serial Interface Global Mode Register ......................16-129

16.7.5.2 Serial Interface Mode Register .................................16-130

16.7.5.3 Serial Interface Clock Route Register ......................16-137

16.7.5.4 Serial Interface Command Register .........................16-140

16.7.5.5 Serial Interface Status Register ................................16-141

16.7.5.6 Serial Interface RAM Pointer Register ......................16-142

16.7.5.6.1 SIRP Indication When RDM = 00 ................16-143

16.7.5.6.2 SIRP Indication When RDM = 01 ................16-144

16.7.5.6.3 SIRP When RDM = 10 .................................16-144

16.7.5.6.4 SIRP When RDM = 11 .................................16-144

16.7.6 IDL Interface Operation ........................................................16-145

16.7.6.1 IDL Interface Implementation ...................................16-146

16.7.6.2 Programming the IDL Interface ................................16-149

16.7.6.2.1 IDL Interface Programming Example ...........16-150

16.7.7 GCI Interface Operation .......................................................16-151

16.7.7.1 GCI Activation/Deactivation Procedure ....................16-152

16.7.7.2 Programming the GCI Interface ................................16-153

16.7.7.2.1 Normal Mode ...............................................16-153

16.7.7.2.2 SCIT Mode ...................................................16-153

16.7.7.3 GCI Interface Programming Example .......................16-154

16.7.8 Nonmultiplexed Serial Interface Configuration .....................16-155

16.8 The Baud Rate Generators .............................................................16-158

16.8.1 Autobaud Operation .............................................................16-160

16.8.2 Baud Rate Generator Configuration Registers ....................16-161

16.8.3 UART Baud Rate Examples .................................................16-163

16.9 The Serial Communication Controllers ...........................................16-165

16.9.1 Features ...............................................................................16-167

16.9.2 The General SCCx Mode Registers .....................................16-168

16.9.3 Protocol-Specific Mode Register ..........................................16-178

16.9.4 Data Synchronization Register .............................................16-179

16.9.5 Transmit-on-Demand Register .............................................16-179

16.9.6 SCCx Buffer Descriptor Operation .......................................16-180

16.9.7 SCCx Parameter RAM Memory Map ...................................16-184

16.9.8 Handling Interrupts In the SCCs ..........................................16-189

16.9.8.1 Interrupt Handling in the SCC Event Register ..........16-189

16.9.8.2 Interrupt Handling in the SCC Mask Register ...........16-189

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16.9.8.3 Interrupt Handling in the SCC Status Register .........16-189

16.9.9 Initializing the Serial Communication Controllers .................16-190

16.9.10 Controlling SCCx Timing ......................................................16-191

16.9.10.1 Synchronous Protocols .............................................16-191

16.9.10.2 Asynchronous Protocols ...........................................16-195

16.9.11 Digital Phase-Locked Loop Operation ..................................16-195

16.9.11.1 Encoding and Decoding Data with a DPLL ...............16-198

16.9.12 Clock Glitches ......................................................................16-199

16.9.13 DPLL and Serial Infrared Encoder/Decoder .........................16-200

16.9.14 Disabling the SCCs On-the-Fly ............................................16-201

16.9.14.1 Disabling the Entire SCCx Transmitter .....................16-201

16.9.14.2 Disabling Part of the SCCx Transmitter ....................16-201

16.9.14.3 Disabling the Entire SCCx Receiver .........................16-202

16.9.14.4 Disabling Part of the SCCx Receiver ........................16-202

16.9.14.5 Switching Protocols ..................................................16-202

16.9.15 The SCCs in UART Mode ....................................................16-203

16.9.15.1 Features ....................................................................16-204

16.9.15.2 Normal Asynchronous Mode ....................................16-205

16.9.15.3 Synchronous Mode ...................................................16-205

16.9.15.4 SCCx UART Parameter RAM Memory Map .............16-206

16.9.15.5 Programming the SCCx in UART Mode ...................16-208

16.9.15.6 SCCx UART Commands ..........................................16-209

16.9.15.7 Recognizing Addresses in SCCx UART Mode .........16-210

16.9.15.8 SCCx UART Control Characters ..............................16-211

16.9.15.9 Wake-Up Timer .........................................................16-213

16.9.15.10 Break Support ...........................................................16-213

16.9.15.11 Sending a Break .......................................................16-214

16.9.15.12 Sending a Preamble .................................................16-214

16.9.15.13 Fractional Stop Bits ...................................................16-215

16.9.15.14 SCCx UART Controller Errors ..................................16-217

16.9.15.15 SCCx UART Mode Register .....................................16-220

16.9.15.16 SCCx UART Receive Buffer Descriptors ..................16-223

16.9.15.17 SCCx UART Transmit Buffer Descriptor ...................16-227

16.9.15.18 SCCx UART Event Register .....................................16-230

16.9.15.19 SCCx UART Mask Register ......................................16-232

16.9.15.20 SCCx UART Status Register ....................................16-233

16.9.15.21 SCC2 UART Programming Example ........................16-233

16.9.15.22 S-Record Programming Example .............................16-235

16.9.16 The SCCs In HDLC Mode ....................................................16-236

16.9.16.1 Features ....................................................................16-237

16.9.16.2 SCCx HDLC Channel Frame Transmission

Process .....................................................................16-237

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16.9.16.3 SCCx HDLC Channel Frame Reception Process .....16-238

16.9.16.4 SCCx HDLC Parameter RAM Memory Map .............16-239

16.9.16.5 Programming the SCCs in HDLC Mode ...................16-241

16.9.16.6 SCCx HDLC Commands ..........................................16-242

16.9.16.7 SCCx HDLC Controller Errors ..................................16-243

16.9.16.8 SCCx HDLC Mode Register .....................................16-245

16.9.16.9 SCCx HDLC Receive Buffer Descriptor ...................16-247

16.9.16.10 SCCx HDLC Transmit Buffer Descriptor ..................16-251

16.9.16.11 SCCx HDLC Event Register .....................................16-253

16.9.16.12 SCCx HDLC Mask Register .....................................16-256

16.9.16.13 SCCx HDLC Status Register ....................................16-257

16.9.16.14 SCC2 HDLC Programming Example #1 ...................16-258

16.9.16.15 SCC2 HDLC Programming Example #2 ...................16-259

16.9.17 The HDLC Bus Controller ....................................................16-260

16.9.17.1 Features ...................................................................16-262

16.9.17.2 Accessing the HDLC Bus .........................................16-263

16.9.17.2.1 Improving Performance ................................16-264

16.9.17.2.2 Delaying RTS

Mode .....................................16-265

16.9.17.2.3 Using the Time-Slot Assigner ......................16-266

16.9.17.3 HDLC Bus Memory Map and Programming .............16-267

16.9.17.3.1 HDLC Bus Controller Programming

Example ........................................................16-267

16.9.18 The SCCs in AppleTalk Mode ..............................................16-268

16.9.18.1 Operating the LocalTalk Bus ....................................16-268

16.9.18.2 Features ...................................................................16-269

16.9.18.3 Connecting to AppleTalk ..........................................16-270

16.9.18.4 Programming the SCCs in AppleTalk Mode .............16-271

16.9.18.5 SCCx AppleTalk Programming Example ..................16-273

16.9.19 The SCCx in Asynchronous HDLC Mode ............................16-273

16.9.19.1 Features ...................................................................16-273

16.9.19.2 SCCx ASYNC HDLC Channel Frame

Transmission Process ..............................................16-273

16.9.19.3 SCCx ASYNC HDLC Channel Frame Reception

Process .....................................................................16-274

16.9.19.4 Transmitter Transparency Encoding ........................16-271

16.9.19.5 Receiver Transparency Decoding ............................16-271

16.9.19.6 Exceptions to RFC 1549 ...........................................16-273

16.9.19.7 SCCx ASYNC HDLC Implementation ......................16-273

16.9.19.8 SCCx ASYNC HDLC Parameter RAM

Memory Map .............................................................16-274

16.9.19.9 Configuring the SCCx ASYNC HDLC Parameters....16-276

16.9.19.10 SCCx ASYNC HDLC Commands .............................16-277

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Motorola MPC823E Reference guide

Motorola MPC823E Reference guide

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