NXP MPC823E Reference guide

Type
Reference guide
©
2000 Motorola, Inc. All Rights Reserved. Revision 0
PowerPC
MPC823e
Reference Manual
The Microprocessor for Mobile Computing
Fr
ees
cale S
em
iconduct
or
, I
For More Information On This Product,
Go to: www.freescale.com
nc...
Freescale Semiconductor
Trademarks
QUICC
is a registered trademark of Motorola, Inc. PowerPC
is a registered trademark of IBM Corporation
and is used by Motorola under license from IBM. I
2
C
®
is a registered tradmark of Philips Corporation.
AppleTalk
®
is a trademark of Apple Computer, Inc.
All other trademarks are the property of their respective owners.
Acknowledgments
The MPC823e Support Team would like to thank the following people for their
contribution to the success of the MPC823e:
Art Miller, CW Clark, Ken Edwards, Kevin Owen, Ray Burgess, Tom Gunter, John Round, Mike Shoemake,
James Wilson, Chris Lines, Ricardo Berger, Yehuda Rudin, Yair Liebman, Udi Barel, the rest of the Israel
design team, Stu Werbner, Tiffany Huling-Broadous, John Dailey, Lan Nguyen, Richard Hendricks,
Darcy Volden, Trish Sierer, Arnaldo Cruz, Danny Nguyen, Myle Buchanan, Joseph Mayfield, Rodolfo Guillen,
the rest of the product/test engineering team, Brian McCalley, Alan Weiss, Steve Rosebaugh, Jasmine Hsiao,
Mike Collier, John Southard, Joseph Lee, Pat Carr, Mark VandenBrink, the rest of the Systems Software team,
Yoichi Kimura, Yuzo Kuramochi, Tanamachi Goro, Fumihiko Kondo, Keiji Momozaki, Jean-Paul Davi,
Per-Eric Josefsson, Rodney Watt, Axel Streicher, Pierre Juste, Gary Segal, Mark DiPerri, Kurt Miller,
Steve Shoap, Rob Wackerman, Rick Heider, Gary Wilson, Thomas Yeh, Bill Durrenberger, Dave Hyder,
the rest of the Field Applications Engineering/Sales support team, Pamela Mitchell, Nina Friedman,
the rest of the Technical Information Center support team, Dan Malek, Jim Belesiu, Clark Liang, Ronny
Svensson, Mark Wagner, Bulent Egilmez, Kurt Fuqua, Robert Applebaum, Nick Vaccaro, Weifu Shi,
Roozbeh Ghorishi, Robert Ritchey, Brad Scott, Dan Malek, the rest of our customers,
the gang at comp.sys.powerpc.tech and linuxppc-embedded, and to many others.
Fr
eescale S
emiconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be
provided in Freescale Semiconductor data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Semiconductor was negligent regarding the design or manufacture of the part.
MPC823e REFERENCE MANUAL
TABLE OF CONTENTS
Paragraph Page
Number Title Number
Section 1
Introduction
1.1 Features ................................................................................................1-1
1.2 Architecture ...........................................................................................1-6
1.2.1 The Embedded PowerPC Core ..................................................1-8
1.2.2 The System Interface Unit ..........................................................1-8
1.2.3 The Communication Processor Module .....................................1-9
1.2.4 The Video/LCD Controller ........................................................1-10
1.2.4.1 The Video Controller .....................................................1-10
1.2.4.2 The LCD Controller .......................................................1-10
1.3 The PCMCIA-ATA Controller ..............................................................1-10
1.4 Power Management ............................................................................1-11
1.5 System Debug Support .......................................................................1-11
1.6 Applications .........................................................................................1-11
1.7 Differences Between MPC823 (Rev B) and MPC823e .......................1-12
1.8 MPC823e Glueless System Design ....................................................1-12
Section 2
External Signals
2.1 The System Bus Signals .......................................................................2-2
Section 3
Memory Map
Section 4
Reset
4.1 Types of Reset ......................................................................................4-2
4.1.1 Power-On Reset .........................................................................4-2
4.1.2 External Hard Reset ...................................................................4-3
4.1.3 Internal Hard Reset ....................................................................4-3
4.1.3.1 Loss of Lock ....................................................................4-3
4.1.3.2 Software Watchdog Reset ..............................................4-3
4.1.3.3 Checkstop Reset ............................................................4-3
4.1.3.4 Debug Port Hard Reset ..................................................4-4
4.1.3.5 JTAG Reset ....................................................................4-4
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
4.1.4 External Soft Reset ....................................................................4-4
4.1.5 Internal Soft Reset .....................................................................4-4
4.1.5.1 Debug Port Soft Reset ....................................................4-4
4.2 Reset Status Register ...........................................................................4-5
4.3 How to Configure Reset ........................................................................4-7
4.3.1 Hard Reset .................................................................................4-7
4.3.1.1 Hard Reset Configuration Word ...................................4-10
4.3.2 Soft Reset ................................................................................4-12
Section 5
Clocks and Power Control
5.1 Features ................................................................................................5-1
5.2 Register Model ......................................................................................5-3
5.2.1 System Clock and Reset Control Register .................................5-3
5.2.2 PLL, Low-Power, and Reset Control Register ...........................5-7
5.3 The Clock Module ...............................................................................5-10
5.3.1 On-Chip Oscillators and External Clock Input ..........................5-12
5.3.2 System PLL ..............................................................................5-12
5.3.2.1 SPLL Stability ...............................................................5-13
5.3.3 The Low-Power Clock Divider ..................................................5-14
5.3.4 Internal Clock Signals ..............................................................5-16
5.3.4.1 The General System Clocks .........................................5-16
5.3.4.2 The Baud Rate Generator Clock ..................................5-19
5.3.4.3 The Synchronization Clocks .........................................5-20
5.3.4.4 The LCD Clocks ...........................................................5-21
5.3.5 Clock Configuration ..................................................................5-22
5.3.5.1 Mode Clock Pins ...........................................................5-22
5.3.5.2 The System Phase-Locked Loop Pins .........................5-23
5.4 Power Control .....................................................................................5-24
5.4.1 Power Rails ..............................................................................5-24
5.4.2 Keep-Alive Power .....................................................................5-25
5.4.2.1 Power Switching Example ............................................5-26
5.4.2.2 Register Lock ................................................................5-27
5.5 Low-Power Operation .........................................................................5-28
Section 6
The PowerPC Core
6.1 Features ................................................................................................6-1
6.2 Basic Structure of the Core ...................................................................6-2
6.2.1 Instruction Flow Within the Core ................................................6-2
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
6.2.2 Basic Instruction Pipeline ...........................................................6-4
6.3 Sequencer Unit .....................................................................................6-4
6.3.1 Flow Control ...............................................................................6-5
6.3.2 Issuing Instructions .....................................................................6-6
6.3.3 Interrupts ....................................................................................6-7
6.3.4 Implementing the Precise Exception Model ...............................6-8
6.3.4.1 Restartability After An Interrupt .....................................6-10
6.3.5 Processing an Interrupt ............................................................6-11
6.3.6 Serialization ..............................................................................6-12
6.3.6.1 Latency .........................................................................6-12
6.3.7 The External Interrupt ...............................................................6-13
6.3.7.1 Latency .........................................................................6-13
6.3.8 Interrupt Ordering .....................................................................6-14
6.4 The Register Unit ................................................................................6-15
6.4.1 Control Registers ......................................................................6-16
6.4.1.1 Physical Location of Special Registers .........................6-19
6.4.1.2 PowerPC Standard Control Register Bit Assignment....6-20
6.4.1.2.1 Machine State Register ....................................6-20
6.4.1.2.2 The Condition Register ....................................6-22
6.4.1.2.3 Fixed-Point Exception Cause Register ............6-23
6.4.1.3 Initializing the Control Registers ...................................6-24
6.4.1.3.1 System Reset Interrupt ....................................6-24
6.4.1.3.2 Hard/Soft Reset ................................................6-24
6.5 The Fixed-Point Unit ...........................................................................6-24
6.5.1 XER Update In Divide Instructions ...........................................6-24
6.6 The Load/Store Unit ............................................................................6-25
6.6.1 Issuing Load/Store Instructions ................................................6-26
6.6.2 Serializing Load/Store Instructions ...........................................6-27
6.6.3 Instructions Issued to the Data Cache .....................................6-27
6.6.4 Issuing Store Instruction Cycles ...............................................6-27
6.6.5 Issuing Nonspeculative Load Instructions ................................6-27
6.6.6 Executing Unaligned Instructions .............................................6-28
6.6.7 Little-Endian Mode Support ......................................................6-29
6.6.8 Atomic Update Primitives .........................................................6-29
6.6.9 Instruction Timing .....................................................................6-30
6.6.10 Stalling Storage Control Instructions ........................................6-30
6.6.11 Accessing Off-Core Special Registers .....................................6-30
6.6.12 Storage Control Instructions .....................................................6-31
6.6.13 Exceptions ................................................................................6-31
6.6.13.1 DAR, DSISR, and BAR Operation ................................6-31
Section 7
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
PowerPC Architecture Compliance
7.1 PowerPC User Instruction Set Architecture (Book I) ............................7-1
7.1.1 Computation Modes ...................................................................7-1
7.1.2 Reserved Fields .........................................................................7-1
7.1.3 Classes of Instructions ...............................................................7-1
7.1.4 Exceptions ..................................................................................7-2
7.1.5 The Branch Processor ...............................................................7-2
7.1.6 Fetching Instructions ..................................................................7-2
7.1.7 Branch Instructions ....................................................................7-2
7.1.7.1 Invalid Branch Instruction Forms ....................................7-2
7.1.7.2 Branch Prediction ...........................................................7-2
7.1.8 The Fixed-Point Processor .........................................................7-2
7.1.8.1 Move To/From System Register Instructions .................7-3
7.1.8.2 Fixed-Point Arithmetic Instructions .................................7-3
7.1.9 The Load/Store Processor .........................................................7-3
7.1.9.1 Fixed-Point Load With Update and Store
With Update Instructions ................................................7-3
7.1.9.2 Fixed-Point Load and Store Multiple Instructions ...........7-3
7.1.9.3 Fixed-Point Load String Instructions ...............................7-3
7.1.9.4 Storage Synchronization Instructions .............................7-4
7.1.9.5 Optional Instructions .......................................................7-4
7.1.9.6 Little-Endian Byte Ordering ............................................7-4
7.2 PowerPC Virtual Environment Architecture (Book II) ............................7-4
7.2.1 Storage Model ............................................................................7-4
7.2.1.1 Memory Coherence ........................................................7-4
7.2.1.2 Atomic Update Primitives ...............................................7-4
7.2.2 The Effect Of Operand Placement on Performance ..................7-5
7.2.3 The Storage Control Instructions ...............................................7-5
7.2.4 Timebase ...................................................................................7-6
7.3 PowerPC Operating Environment Architecture (Book III) .....................7-6
7.3.1 The Branch Processor ...............................................................7-6
7.3.1.1 Machine State Register ..................................................7-6
7.3.1.2 Processor Version Register ............................................7-6
7.3.1.3 Branch Processors Instructions ......................................7-6
7.3.2 The Fixed-Point Processor .........................................................7-6
7.3.2.1 Unsupported Registers ...................................................7-6
7.3.2.2 Added Registers .............................................................7-6
7.3.3 Storage Model ............................................................................7-6
7.3.3.1 Address Translation ........................................................7-6
7.3.4 Reference and Change Bits .......................................................7-7
7.3.5 Storage Protection .....................................................................7-7
7.3.6 Storage Control Instructions .......................................................7-7
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
7.3.6.1 Data Cache Block Invalidate (dcbi) .................................7-7
7.3.6.2 TLB Invalidate Entry (tlbie) .............................................7-7
7.3.6.3 TLB Invalidate All (tlbia) ..................................................7-7
7.3.6.4 TLB Synchronize (tlbsync) ..............................................7-7
7.3.7 Interrupts ....................................................................................7-7
7.3.7.1 Classes ...........................................................................7-7
7.3.7.2 Processing ......................................................................7-8
7.3.7.3 Definitions .......................................................................7-8
7.3.7.3.1 System Reset Interrupt ......................................7-9
7.3.7.3.2 Machine Check Interrupt ....................................7-9
7.3.7.3.3 Data Storage Interrupt ......................................7-10
7.3.7.3.4 Instruction Storage Interrupt .............................7-10
7.3.7.3.5 Alignment Interrupt ...........................................7-10
7.3.7.3.6 Program Interrupt .............................................7-11
7.3.7.3.7 Floating-Point Unavailable Interrupt .................7-11
7.3.7.3.8 Trace Interrupt ..................................................7-11
7.3.7.3.9 Floating-Point Assist Interrupt ..........................7-11
7.3.7.3.10 Implementation-Dependent Software
Emulation Interrupt ............................................7-12
7.3.7.3.11 Implementation-Specific Instruction TLB
Miss Interrupt ....................................................7-12
7.3.7.3.12 Implementation-Specific Instruction TLB
Error Interrupt ....................................................7-13
7.3.7.3.13 Implementation-Specific Data TLB Miss
Interrupt .............................................................7-14
7.3.7.3.14 Implementation-Specific Data TLB Error
Interrupt .............................................................7-14
7.3.7.3.15 Implementation-Specific Debug Register .........7-15
7.3.7.4 Partially Executed Instructions ......................................7-17
7.3.8 Timer Facilities .........................................................................7-17
7.3.9 Optional Facilities and Instructions ...........................................7-17
Section 8
Instruction Execution Timing
8.1 Instruction Timing List ...........................................................................8-1
8.2 Instruction Execution Timing Examples ................................................8-4
8.2.1 Data Cache Load .......................................................................8-4
8.2.2 Writeback ...................................................................................8-5
8.2.2.1 Writeback Arbitration ......................................................8-5
8.2.2.2 Private Writeback Bus Load ...........................................8-6
8.2.3 Fastest External Load (Data Cache Miss) ..................................8-7
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
8.2.4 A Full History Buffer ...................................................................8-8
8.2.5 Branch Folding ...........................................................................8-9
8.2.6 Branch Prediction .....................................................................8-10
Section 9
Instruction Cache
9.1 Features ................................................................................................9-1
9.2 Programming the Instruction Cache .....................................................9-4
9.2.1 Instruction Cache Control and Status Register ..........................9-5
9.2.2 Instruction Cache Address Register ...........................................9-6
9.2.3 Instruction Cache Data Port Register .........................................9-7
9.3 Instruction Cache Operation .................................................................9-7
9.3.1 Instruction Cache Hit ..................................................................9-7
9.3.2 Instruction Cache Miss ...............................................................9-8
9.3.3 Instruction Fetch On A Predicted Path .......................................9-8
9.4 instruction Cache Commands ...............................................................9-8
9.4.1 Invalidating the Instruction Cache ..............................................9-9
9.4.2 Loading and Locking the Instruction Cache .............................9-10
9.4.3 Unlocking A Line ......................................................................9-10
9.4.4 Unlocking the Entire Instruction Cache ....................................9-11
9.4.5 Inhibiting the Instruction Cache ................................................9-11
9.4.6 Instruction Cache Read ............................................................9-12
9.4.7 Instruction Cache Write ............................................................9-14
9.5 Restrictions .........................................................................................9-14
9.6 Instruction Cache Coherency ..............................................................9-14
9.7 Updating Code And Memory Region Attributes ..................................9-14
9.8 Reset Sequence .................................................................................9-14
9.9 Debug Support ....................................................................................9-15
9.9.1 Fetching Instructions From The Development Port ..................9-15
Section 10
Data Cache
10.1 Features ..............................................................................................10-1
10.2 Organization of the Data Cache ..........................................................10-2
10.3 Programming the Data Cache ............................................................10-3
10.3.1 PowerPC Architecture Instructions ..........................................10-3
10.3.1.1 PowerPC User Instruction Set Architecture (Book I).....10-3
10.3.1.2 PowerPC Virtual Environment Architecture (Book II)....10-4
10.3.1.3 PowerPC Operating Environment Architecture
(Book III) .......................................................................10-4
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
10.3.2 Implementation-Specific Operations ........................................10-4
10.3.3 Special Registers of the Data Cache .......................................10-4
10.3.3.1 Data Cache Control and Status Register ......................10-5
10.3.3.2 Data Cache Address Register ......................................10-7
10.3.3.3 Reading the Cache Structures ......................................10-7
10.4 Operating the Data Cache ................................................................10-10
10.4.1 Data Cache Read ...................................................................10-10
10.4.2 Data Cache Write ...................................................................10-10
10.4.2.1 Copyback Mode ..........................................................10-11
10.4.2.2 Writethrough Mode .....................................................10-12
10.4.3 Data Cache Inhibited Accesses .............................................10-12
10.4.4 Data Cache Freeze ................................................................10-12
10.4.5 Data Cache Coherency ..........................................................10-13
10.5 Data Cache Commands ....................................................................10-13
10.5.1 Flushing and Invalidating the Cache ......................................10-13
10.5.2 Enabling and Disabling the Cache .........................................10-13
10.5.3 Locking and Unlocking the Cache ..........................................10-13
10.5.4 Data Cache Instructions .........................................................10-14
10.5.4.1 dcbi, dcbst, dcbf And dcbz Instructions ......................10-14
10.5.4.2 Touch ..........................................................................10-14
10.5.4.3 Storage Synchronization/Reservation ........................10-14
10.5.5 Data Cache Read ...................................................................10-14
Section 11
Memory Management Unit
11.1 Features ..............................................................................................11-1
11.2 Address Translation ............................................................................11-2
11.2.1 Translation Lookaside Buffer Operation ...................................11-2
11.3 Protection ............................................................................................11-3
11.4 Storage Control ...................................................................................11-4
11.5 Translation Table Structure .................................................................11-5
11.5.1 Level One Descriptor ................................................................11-9
11.5.2 Level Two Descriptor ..............................................................11-10
11.6 Programming the Memory Management Unit ...................................11-15
11.6.1 Control Registers ....................................................................11-16
11.6.1.1 MMU Instruction Control Register ...............................11-16
11.6.1.2 MMU Data Control Register ........................................11-17
11.6.1.3 MMU Current Address Space ID Register ..................11-18
11.6.1.4 MMU Instruction Effective Page Number Register .....11-19
11.6.1.5 MMU Data Effective Page Number Register ..............11-20
11.6.1.6 MMU Instruction Real Page Number Register ............11-21
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
11.6.1.7 MMU Data Real Page Number Register ....................11-26
11.6.1.8 MMU Instruction Access Protection Register .............11-31
11.6.1.9 MMU Data Access Protection Register ......................11-32
11.6.1.10 MMU Instruction Tablewalk Control Register .............11-33
11.6.1.11 MMU Data Tablewalk Control Register ......................11-34
11.6.1.12 MMU Tablewalk Base Register ..................................11-36
11.6.1.13 MMU Tablewalk Special Register ...............................11-37
11.6.2 MMU Data Content-Addressable Registers ...........................11-37
11.6.2.1 MMU Data CAM Entry Read Register ........................11-38
11.6.2.2 MMU Data RAM Entry Read Register 0 .....................11-39
11.6.2.3 MMU Data RAM Entry Read Register 1 .....................11-41
11.6.3 MMU Instruction Content-Addressable Registers ..................11-43
11.6.3.1 MMU Instruction CAM Entry Read Register ...............11-43
11.6.3.2 MMU Instruction RAM Entry Read Register 0 ............11-45
11.6.3.3 MMU Instruction RAM Entry Read Register 1 ............11-46
11.7 Interrupts ...........................................................................................11-47
11.7.1 Implementation-Specific Instruction TLB Miss .......................11-47
11.7.2 Implementation-Specific Data TLB Miss ................................11-47
11.7.3 Implementation-Specific Instruction TLB Error .......................11-48
11.7.4 Implementation-Specific Data TLB Error ................................11-48
11.8 Manipulating the Translation Lookaside Buffer .................................11-49
11.8.1 Reloading the Translation Lookaside Buffer ..........................11-49
11.8.1.1 Translation Reload Examples .....................................11-50
11.8.2 Controlling the TLB Replacement Counter ............................11-51
11.8.3 Invalidating the Translation Lookaside Buffer ........................11-51
11.8.4 Loading the Reserved TLB Entries ........................................11-51
11.9 Requirements For Accessing The Memory Management Unit
Control Registers ..............................................................................11-52
Section 12
System Interface Unit
12.1 Features ..............................................................................................12-2
12.2 System Configuration and Protection .................................................12-2
12.3 Interrupt Configuration ........................................................................12-5
12.3.1 The Interrupt Structure .............................................................12-5
12.3.2 Priority of the Interrupt Sources ...............................................12-6
12.3.3 Programming the Interrupt Controller .......................................12-7
12.3.3.1 SIU Interrupt Pending Register .....................................12-7
12.3.3.2 SIU Interrupt Mask Register .........................................12-8
12.3.3.3 SIU Interrupt Edge/Level Register ................................12-9
12.3.3.4 SIU Interrupt Vector Register .....................................12-10
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
12.4 The Bus Monitor ................................................................................12-11
12.5 The PowerPC Decrementer ..............................................................12-12
12.5.1 Decrementer Register ............................................................12-13
12.6 The PowerPC Timebase ...................................................................12-14
12.6.1 Timebase Register .................................................................12-14
12.6.2 Timebase Reference Registers ..............................................12-15
12.6.3 Timebase Status and Control Register ..................................12-16
12.7 The Real-Time Clock ........................................................................12-17
12.7.1 Real-Time Clock Status and Control Register ........................12-18
12.7.2 Real-Time Clock Register ......................................................12-19
12.7.3 Real-Time Clock Alarm Seconds Register .............................12-20
12.7.4 Real-Time Clock Alarm Register ............................................12-21
12.8 The Periodic Interrupt Timer .............................................................12-22
12.8.1 Periodic Interrupt Status and Control Register .......................12-23
12.8.2 Periodic Interrupt Timer Count Register .................................12-24
12.8.3 Periodic Interrupt Timer Register ...........................................12-25
12.9 The Software Watchdog Timer .........................................................12-26
12.9.1 Software Service Register ......................................................12-27
12.10 Freeze Operation ..............................................................................12-28
12.10.1 Low-Power Stop Operation ....................................................12-28
12.11 Multiplexing the System Interface Unit Pins ......................................12-29
12.12 Programming the System Interface Unit ...........................................12-30
12.12.1 System Configuration and Protection Registers .....................12-30
12.12.1.1 SIU Module Configuration Register ............................12-30
12.12.1.2 Internal Memory Map Register ...................................12-34
12.12.1.3 System Protection Control Register ............................12-35
12.12.1.4 Transfer Error Status Register ....................................12-36
Section 13
External Bus Interface
13.1 Features ..............................................................................................13-1
13.2 Transfer Signals ..................................................................................13-1
13.2.1 Control Signals .........................................................................13-3
13.3 Bus Signal Descriptions ......................................................................13-4
13.4 Bus Interface Operation ......................................................................13-7
13.4.1 Basic Transfers ........................................................................13-8
13.4.2 Single Beat Transfers ...............................................................13-8
13.4.2.1 Single Beat Read Flow .................................................13-9
13.4.2.2 Single Beat Write Flow ...............................................13-12
13.4.3 Burst Transfers .......................................................................13-16
13.4.4 The Burst Mechanism ............................................................13-16
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
13.4.5 Transfer Alignment and Packaging ........................................13-25
13.4.6 Arbitration Phase-Related Signals .........................................13-27
13.4.6.1 Bus Request Signal ....................................................13-28
13.4.6.2 Bus Grant Signal ........................................................13-29
13.4.6.3 Bus Busy Signal .........................................................13-29
13.4.7 Address Transfer Phase-Related Signals ..............................13-31
13.4.7.1 Transfer Start Signal ...................................................13-31
13.4.7.2 Address Bus ...............................................................13-32
13.4.7.3 Transfer Attributes ......................................................13-32
13.4.7.3.1 Read/Write Signal ..........................................13-32
13.4.7.3.2 Burst Signal ....................................................13-32
13.4.7.3.3 Transfer Size Signal .......................................13-33
13.4.7.3.4 Address Space Attributes ..............................13-33
13.4.7.3.5 Special Transfer Start Signal .........................13-33
13.4.7.3.6 Burst Data in Progress Signal ........................13-36
13.4.8 Data Transfer Phase-Related Signals ....................................13-36
13.4.8.1 Data Signal .................................................................13-36
13.4.9 Termination Phase-Related Signals .......................................13-36
13.4.9.1 Transfer Acknowledge Signal .....................................13-36
13.4.9.2 Burst Inhibit Signal ......................................................13-36
13.4.9.3 Transfer Error Acknowledge Signal ............................13-36
13.4.9.4 Protocol for Termination Signals ................................13-37
13.4.10 Storage Reservation Protocol ................................................13-38
13.4.11 Exception Control Cycles .......................................................13-41
13.4.11.1 RETRY Signal ............................................................13-42
Section 14
Endian Modes
14.1 Little-Endian Features .........................................................................14-3
14.2 Big-Endian System Features ..............................................................14-5
14.3 PowerPC Little-Endian System Features ............................................14-5
14.4 Setting the Endian Mode Of Operation .............................................. 14-5
Section 15
Memory Controller
15.1 Features ..............................................................................................15-1
15.2 Architecture .........................................................................................15-4
15.3 Register Model ....................................................................................15-7
15.3.1 Register Descriptions ...............................................................15-9
15.3.1.1 Base Registers .............................................................15-9
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
15.3.1.2 Option Registers .........................................................15-11
15.3.1.3 Memory Status Register .............................................15-15
15.3.1.4 Memory Command Register .......................................15-17
15.3.1.5 Machine A Mode Register ..........................................15-19
15.3.1.6 Machine B Mode Register ..........................................15-22
15.3.1.7 Memory Data Register ................................................15-26
15.3.1.8 Memory Address Register ..........................................15-26
15.3.1.9 Memory Periodic Timer Prescaler Register ................15-27
15.4 The General-Purpose Chip-Select Machine .....................................15-27
15.4.1 Configuration ..........................................................................15-27
15.4.1.1 Programmable Wait State Configuration ....................15-34
15.4.1.2 Extended Hold Time on Read Accesses ....................15-34
15.4.1.3 Boot Chip-Select Operation ........................................15-37
15.4.1.4 SRAM Interface ..........................................................15-38
15.4.1.5 External Asynchronous Master support ......................15-38
15.5 User-Programmable Machines .........................................................15-41
15.5.1 Requests ................................................................................15-42
15.5.1.1 Internal/External Memory Access Requests ...............15-43
15.5.1.2 Memory Periodic Timer Requests ..............................15-43
15.5.1.3 Software Requests .....................................................15-44
15.5.1.4 Exception Requests ....................................................15-44
15.5.2 Programming the User-Programmable Machine ....................15-44
15.5.3 Clock Timing ...........................................................................15-45
15.5.4 The RAM Array .......................................................................15-49
15.5.4.1 The RAM Word ...........................................................15-50
15.5.4.1.1 RAM Word Format .........................................15-50
15.5.4.2 RAM Word Operation .................................................15-55
15.5.4.2.1 Start Addresses ..............................................15-55
15.5.4.2.2 Chip-Select Signals ........................................15-56
15.5.4.2.3 Byte-Select Signals ........................................15-57
15.5.4.2.4 General-Purpose Signals ...............................15-59
15.5.4.2.5 Loop Control ...................................................15-60
15.5.4.2.6 Exception Handling ........................................15-60
15.5.4.2.7 Address Multiplexing ......................................15-61
15.5.4.2.8 Transfer Acknowledge and Data Sample
Control ............................................................15-65
15.5.4.2.9 Disable Timer Mechanism ..............................15-65
15.5.4.2.10 Last Word .......................................................15-65
15.5.5 The Wait Mechanism ..............................................................15-66
15.5.5.1 Internal and External Synchronous Master .................15-66
15.5.5.2 External Asynchronous Master ...................................15-67
15.5.5.3 Handling Variable Access Time and Slow Devices ....15-68
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
15.5.5.3.1 Hierarchical Bus Interface Example ...............15-68
15.5.5.3.2 Slow Device Interface Example .....................15-68
15.6 External Master Support ...................................................................15-69
15.6.1 External Master Examples .....................................................15-73
15.6.1.1 Memory System Interface Examples ..........................15-77
15.6.2 Page Mode DRAM Interface Example ...................................15-77
15.6.3 Page Mode Extended Data-Out DRAM Interface Example ....15-89
Section 16
Communication Processor Module
16.1 Features ..............................................................................................16-1
16.2 The RISC Microcontroller ....................................................................16-4
16.2.1 RISC Microcontroller Features .................................................16-5
16.2.2 Communication Between the Microcontroller and Core ...........16-6
16.2.3 Communication Between the Microcontroller
and Peripherals .........................................................................16-6
16.2.4 Executing Microcode From RAM or ROM ................................16-7
16.2.5 RISC Configuration and Control Registers ..............................16-7
16.2.6 RISC Microcontroller Commands .............................................16-9
16.2.6.1 CPM Command Register ..............................................16-9
16.2.6.2 Command Definitions .................................................16-11
16.2.6.2.1 CPM Command Register Example ................16-13
16.2.6.3 Dual-Port RAM ...........................................................16-13
16.2.6.3.1 Buffer Descriptors ..........................................16-15
16.2.6.3.2 Parameter RAM .............................................16-15
16.2.6.4 The RISC Timer Tables ..............................................16-17
16.2.6.4.1 RISC Timer Table Parameter RAM
Memory Map ...................................................16-18
16.2.6.4.2 RISC Timer Table Entries ..............................16-22
16.2.6.4.3 The SET TIMER Command ...........................16-22
16.2.6.4.4 PWM Mode ....................................................16-22
16.2.6.5 RISC Timer Event Register ........................................16-23
16.2.6.6 RISC Timer Mask Register .........................................16-23
16.2.6.7 RISC Timer Initialization Sequence Example .............16-24
16.2.6.8 RISC Timer Interrupt Handling Example ....................16-25
16.2.6.9 RISC Timer Table Algorithm .......................................16-25
16.2.6.10 Using the Timers to Track Microcontroller Loading.....16-25
16.3 Digital Signal Processing ..................................................................16-26
16.3.1 Features .................................................................................16-26
16.3.2 DSP Operation .......................................................................16-26
16.3.2.1 Hardware ....................................................................16-27
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
16.3.2.2 Software ......................................................................16-27
16.3.2.3 Firmware .....................................................................16-27
16.3.3 Programming the DSP Functions ...........................................16-27
16.3.3.1 Data Representation ...................................................16-28
16.3.3.2 Modulo Addressing .....................................................16-29
16.3.3.2.1 DSP Function Descriptors ..............................16-29
16.3.3.2.2 DSP Parameter RAM Memory Map ...............16-30
16.3.3.2.3 DSP Commands ............................................16-32
16.3.3.3 DSP Event Register ....................................................16-33
16.3.3.4 DSP Mask Register ....................................................16-34
16.3.3.5 DSP Implementation ...................................................16-35
16.3.3.5.1 DSP Programming Example (Core Only) .......16-36
16.3.3.5.2 DSP Programming Example
(Core and CPM) ..............................................16-37
16.3.4 DSP On-Chip Library Functions .............................................16-38
16.3.4.1 FIR1–Real C, Real X, and Real Y ..............................16-39
16.3.4.1.1 Coefficients and Sample Data Buffers ...........16-39
16.3.4.1.2 FIR1 Function Descriptor ...............................16-40
16.3.4.1.3 FIR1 Parameter Packet ..................................16-41
16.3.4.1.4 Application Example .......................................16-41
16.3.4.2 FIR2–Real C, Complex X, and Complex Y .................16-42
16.3.4.2.1 Coefficients and Sample Data Buffers ...........16-42
16.3.4.2.2 FIR2 Function Descriptor ...............................16-43
16.3.4.2.3 FIR2 Parameter Packet ..................................16-45
16.3.4.2.4 Application Example .......................................16-45
16.3.4.3 FIR3–Complex C, Complex X, and
Real/Complex Y .........................................................16-46
16.3.4.3.1 Coefficients and Sample Data Buffers ...........16-47
16.3.4.3.2 FIR3 Function Descriptor ...............................16-47
16.3.4.3.3 FIR3 Parameter Packet ..................................16-49
16.3.4.3.4 Application Example .......................................16-49
16.3.4.4 FIR5–Complex C, Complex X, and Complex Y ..........16-50
16.3.4.4.1 Coefficients and Sample Data Buffers ...........16-50
16.3.4.4.2 FIR5 Function Descriptor ...............................16-51
16.3.4.4.3 FIR5 Parameter Packet ..................................16-53
16.3.4.4.4 Application Example .......................................16-53
16.3.4.5 FIR6–Complex C, Real X, and Complex Y .................16-54
16.3.4.5.1 Coefficients and Sample Data Buffers ...........16-54
16.3.4.5.2 FIR6 Function Descriptor ...............................16-55
16.3.4.5.3 FIR6 Parameter Packet ..................................16-57
16.3.4.6 IIR–Real C, Real X, Real Y .........................................16-57
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
16.3.4.6.1 Coefficients and Sample Data Buffers ...........16-57
16.3.4.6.2 IIR Function Descriptor ..................................16-58
16.3.4.6.3 IIR Parameter Packet .....................................16-59
16.3.4.6.4 Application Example ......................................16-59
16.3.4.7 MOD–Real Sin, Real Cos, Complex X, and
Real/Complex Y ..........................................................16-60
16.3.4.7.1 Modulation Table and Sample Data Buffers ..16-60
16.3.4.7.2 MOD Function Descriptor ..............................16-61
16.3.4.7.3 MOD Parameter Packet .................................16-62
16.3.4.7.4 Application Example ......................................16-62
16.3.4.8 DEMOD–Real Sin; Real Cos, Real X, and
Complex Y ..................................................................16-62
16.3.4.8.1 Modulation Table, Sample Data Buffers,
and AGC Constant .........................................16-63
16.3.4.8.2 DEMOD Function Descriptor .........................16-63
16.3.4.8.3 DEMOD Parameter Packet ............................16-64
16.3.4.8.4 Application Example ......................................16-65
16.3.4.9 LMS1–Complex Coefficients, Complex Samples,
and Real/Complex Scalar ...........................................16-65
16.3.4.9.1 Coefficients and Sample Data Buffers ...........16-65
16.3.4.9.2 LMS1 Function Descriptor .............................16-66
16.3.4.9.3 LMS1 Parameter Packet ................................16-67
16.3.4.9.4 Application Example ......................................16-67
16.3.4.10 LMS2–Complex Coefficients, Complex Samples,
and Real/Complex Scalar ...........................................16-67
16.3.4.10.1 Coefficients and Sample Data Buffers ...........16-68
16.3.4.10.2 LMS2 Function Descriptor .............................16-68
16.3.4.10.3 LMS2 Parameter Packet ................................16-70
16.3.4.10.4 Application Example ......................................16-70
16.3.4.11 WADD–Real X and Real Y .........................................16-70
16.3.4.11.1 Coefficients and Sample Data Buffers ...........16-71
16.3.4.11.2 WADD Function Descriptor ............................16-71
16.3.4.11.3 WADD Parameter Packet ..............................16-72
16.3.4.11.4 Application Example ......................................16-73
16.3.4.12 The DSP Execution Times .........................................16-73
16.4 Timers ...............................................................................................16-75
16.4.1 Features .................................................................................16-75
16.4.2 Timer Operation .....................................................................16-76
16.4.2.1 Cascaded Mode .........................................................16-77
16.4.2.2 Timer Global Configuration Register ..........................16-78
16.4.2.3 Timer Mode Registers ................................................16-79
16.4.2.4 Timer Reference Registers .........................................16-80
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
16.4.2.5 Timer Capture Registers .............................................16-81
16.4.2.6 Timer Counter Registers .............................................16-81
16.4.2.7 Timer Event Registers ................................................16-82
16.4.3 Initializing the Timers ..............................................................16-82
16.5 The SDMA Channels ........................................................................16-83
16.5.1 SDMA Bus Arbitration and Transfers .....................................16-85
16.5.2 The SDMA Registers ..............................................................16-86
16.5.2.1 SDMA Configuration Register .....................................16-86
16.5.2.2 SDMA Status Register ................................................16-88
16.5.2.3 SDMA Mask Register .................................................16-89
16.5.2.4 SDMA Address Register .............................................16-90
16.6 Emulating IDMA ................................................................................16-90
16.6.1 Features .................................................................................16-91
16.6.2 IDMA Interface Signals ...........................................................16-91
16.6.2.1 DREQx
and SDACKx .................................................16-91
16.6.3 IDMA Operation ......................................................................16-91
16.6.3.1 AutoBuffer and Buffer Chaining ..................................16-92
16.6.3.2 IDMA Parameter RAM Memory Map ..........................16-93
16.6.3.3 IDMA Status Registers ...............................................16-95
16.6.3.4 IDMA Mask Registers .................................................16-96
16.6.3.5 IDMA Buffer Descriptors .............................................16-97
16.6.3.6 IDMA Commands .....................................................16-101
16.6.3.7 Starting IDMA ...........................................................16-102
16.6.3.8 Requesting IDMA Transfers .....................................16-102
16.6.3.9 Level-Sensitive Mode ...............................................16-102
16.6.3.10 Edge-Sensitive Mode ................................................16-102
16.6.3.11 IDMA Operand Transfers ..........................................16-103
16.6.3.11.1 Transfer Identification ...................................16-103
16.6.3.11.2 Dual-Address Mode .....................................16-103
16.6.3.11.3 Single-Address Mode (Fly-By Transfers) .....16-104
16.6.3.11.4 Single-Buffer Burst Fly-By Mode ..................16-106
16.6.3.12 IDMA Status Registers .............................................16-110
16.6.3.13 IDMA Mask Registers ...............................................16-111
16.6.3.14 Single-Buffer Timing .................................................16-111
16.6.3.15 DownLoad Sequence ...............................................16-112
16.6.3.16 Bus Exceptions .........................................................16-113
16.7 The Serial Interface with Time-Slot Assigner ..................................16-113
16.7.1 Features ...............................................................................16-115
16.7.2 Configuring the Time-Slot Assigner ......................................16-115
16.7.3 Enabling Connections to the Time-Slot Assigner .................16-118
16.7.4 Serial Interface RAM Operation ...........................................16-118
16.7.4.1 One Multiplexed Channel with Static Frames ...........16-119
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
16.7.4.2 One Multiplexed Channel With Dynamic Frames......16-120
16.7.4.3 Two multiplexed Channels with Static Frames..........16-121
16.7.4.4 tWO Multiplexed Channels With Dynamic Frames....16-122
16.7.4.5 Programming the Serial Interface RAM Entries ........16-123
16.7.4.6 Serial Interface RAM Dynamic Changes ..................16-126
16.7.5 Serial Interface Programming Model ....................................16-129
16.7.5.1 Serial Interface Global Mode Register ......................16-129
16.7.5.2 Serial Interface Mode Register .................................16-130
16.7.5.3 Serial Interface Clock Route Register ......................16-137
16.7.5.4 Serial Interface Command Register .........................16-140
16.7.5.5 Serial Interface Status Register ................................16-141
16.7.5.6 Serial Interface RAM Pointer Register ......................16-142
16.7.5.6.1 SIRP Indication When RDM = 00 ................16-143
16.7.5.6.2 SIRP Indication When RDM = 01 ................16-144
16.7.5.6.3 SIRP When RDM = 10 .................................16-144
16.7.5.6.4 SIRP When RDM = 11 .................................16-144
16.7.6 IDL Interface Operation ........................................................16-145
16.7.6.1 IDL Interface Implementation ...................................16-146
16.7.6.2 Programming the IDL Interface ................................16-149
16.7.6.2.1 IDL Interface Programming Example ...........16-150
16.7.7 GCI Interface Operation .......................................................16-151
16.7.7.1 GCI Activation/Deactivation Procedure ....................16-152
16.7.7.2 Programming the GCI Interface ................................16-153
16.7.7.2.1 Normal Mode ...............................................16-153
16.7.7.2.2 SCIT Mode ...................................................16-153
16.7.7.3 GCI Interface Programming Example .......................16-154
16.7.8 Nonmultiplexed Serial Interface Configuration .....................16-155
16.8 The Baud Rate Generators .............................................................16-158
16.8.1 Autobaud Operation .............................................................16-160
16.8.2 Baud Rate Generator Configuration Registers ....................16-161
16.8.3 UART Baud Rate Examples .................................................16-163
16.9 The Serial Communication Controllers ...........................................16-165
16.9.1 Features ...............................................................................16-167
16.9.2 The General SCCx Mode Registers .....................................16-168
16.9.3 Protocol-Specific Mode Register ..........................................16-178
16.9.4 Data Synchronization Register .............................................16-179
16.9.5 Transmit-on-Demand Register .............................................16-179
16.9.6 SCCx Buffer Descriptor Operation .......................................16-180
16.9.7 SCCx Parameter RAM Memory Map ...................................16-184
16.9.8 Handling Interrupts In the SCCs ..........................................16-189
16.9.8.1 Interrupt Handling in the SCC Event Register ..........16-189
16.9.8.2 Interrupt Handling in the SCC Mask Register ...........16-189
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
16.9.8.3 Interrupt Handling in the SCC Status Register .........16-189
16.9.9 Initializing the Serial Communication Controllers .................16-190
16.9.10 Controlling SCCx Timing ......................................................16-191
16.9.10.1 Synchronous Protocols .............................................16-191
16.9.10.2 Asynchronous Protocols ...........................................16-195
16.9.11 Digital Phase-Locked Loop Operation ..................................16-195
16.9.11.1 Encoding and Decoding Data with a DPLL ...............16-198
16.9.12 Clock Glitches ......................................................................16-199
16.9.13 DPLL and Serial Infrared Encoder/Decoder .........................16-200
16.9.14 Disabling the SCCs On-the-Fly ............................................16-201
16.9.14.1 Disabling the Entire SCCx Transmitter .....................16-201
16.9.14.2 Disabling Part of the SCCx Transmitter ....................16-201
16.9.14.3 Disabling the Entire SCCx Receiver .........................16-202
16.9.14.4 Disabling Part of the SCCx Receiver ........................16-202
16.9.14.5 Switching Protocols ..................................................16-202
16.9.15 The SCCs in UART Mode ....................................................16-203
16.9.15.1 Features ....................................................................16-204
16.9.15.2 Normal Asynchronous Mode ....................................16-205
16.9.15.3 Synchronous Mode ...................................................16-205
16.9.15.4 SCCx UART Parameter RAM Memory Map .............16-206
16.9.15.5 Programming the SCCx in UART Mode ...................16-208
16.9.15.6 SCCx UART Commands ..........................................16-209
16.9.15.7 Recognizing Addresses in SCCx UART Mode .........16-210
16.9.15.8 SCCx UART Control Characters ..............................16-211
16.9.15.9 Wake-Up Timer .........................................................16-213
16.9.15.10 Break Support ...........................................................16-213
16.9.15.11 Sending a Break .......................................................16-214
16.9.15.12 Sending a Preamble .................................................16-214
16.9.15.13 Fractional Stop Bits ...................................................16-215
16.9.15.14 SCCx UART Controller Errors ..................................16-217
16.9.15.15 SCCx UART Mode Register .....................................16-220
16.9.15.16 SCCx UART Receive Buffer Descriptors ..................16-223
16.9.15.17 SCCx UART Transmit Buffer Descriptor ...................16-227
16.9.15.18 SCCx UART Event Register .....................................16-230
16.9.15.19 SCCx UART Mask Register ......................................16-232
16.9.15.20 SCCx UART Status Register ....................................16-233
16.9.15.21 SCC2 UART Programming Example ........................16-233
16.9.15.22 S-Record Programming Example .............................16-235
16.9.16 The SCCs In HDLC Mode ....................................................16-236
16.9.16.1 Features ....................................................................16-237
16.9.16.2 SCCx HDLC Channel Frame Transmission
Process .....................................................................16-237
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
TABLE OF CONTENTS (Continued)
Paragraph Page
Number Title Number
MPC823e REFERENCE MANUAL
16.9.16.3 SCCx HDLC Channel Frame Reception Process .....16-238
16.9.16.4 SCCx HDLC Parameter RAM Memory Map .............16-239
16.9.16.5 Programming the SCCs in HDLC Mode ...................16-241
16.9.16.6 SCCx HDLC Commands ..........................................16-242
16.9.16.7 SCCx HDLC Controller Errors ..................................16-243
16.9.16.8 SCCx HDLC Mode Register .....................................16-245
16.9.16.9 SCCx HDLC Receive Buffer Descriptor ...................16-247
16.9.16.10 SCCx HDLC Transmit Buffer Descriptor ..................16-251
16.9.16.11 SCCx HDLC Event Register .....................................16-253
16.9.16.12 SCCx HDLC Mask Register .....................................16-256
16.9.16.13 SCCx HDLC Status Register ....................................16-257
16.9.16.14 SCC2 HDLC Programming Example #1 ...................16-258
16.9.16.15 SCC2 HDLC Programming Example #2 ...................16-259
16.9.17 The HDLC Bus Controller ....................................................16-260
16.9.17.1 Features ...................................................................16-262
16.9.17.2 Accessing the HDLC Bus .........................................16-263
16.9.17.2.1 Improving Performance ................................16-264
16.9.17.2.2 Delaying RTS
Mode .....................................16-265
16.9.17.2.3 Using the Time-Slot Assigner ......................16-266
16.9.17.3 HDLC Bus Memory Map and Programming .............16-267
16.9.17.3.1 HDLC Bus Controller Programming
Example ........................................................16-267
16.9.18 The SCCs in AppleTalk Mode ..............................................16-268
16.9.18.1 Operating the LocalTalk Bus ....................................16-268
16.9.18.2 Features ...................................................................16-269
16.9.18.3 Connecting to AppleTalk ..........................................16-270
16.9.18.4 Programming the SCCs in AppleTalk Mode .............16-271
16.9.18.5 SCCx AppleTalk Programming Example ..................16-273
16.9.19 The SCCx in Asynchronous HDLC Mode ............................16-273
16.9.19.1 Features ...................................................................16-273
16.9.19.2 SCCx ASYNC HDLC Channel Frame
Transmission Process ..............................................16-273
16.9.19.3 SCCx ASYNC HDLC Channel Frame Reception
Process .....................................................................16-274
16.9.19.4 Transmitter Transparency Encoding ........................16-271
16.9.19.5 Receiver Transparency Decoding ............................16-271
16.9.19.6 Exceptions to RFC 1549 ...........................................16-273
16.9.19.7 SCCx ASYNC HDLC Implementation ......................16-273
16.9.19.8 SCCx ASYNC HDLC Parameter RAM
Memory Map .............................................................16-274
16.9.19.9 Configuring the SCCx ASYNC HDLC Parameters....16-276
16.9.19.10 SCCx ASYNC HDLC Commands .............................16-277
Fr
ees
cale S
em
iconduct
or
, I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
nc...
  • Page 1 1
  • Page 2 2
  • Page 3 3
  • Page 4 4
  • Page 5 5
  • Page 6 6
  • Page 7 7
  • Page 8 8
  • Page 9 9
  • Page 10 10
  • Page 11 11
  • Page 12 12
  • Page 13 13
  • Page 14 14
  • Page 15 15
  • Page 16 16
  • Page 17 17
  • Page 18 18
  • Page 19 19
  • Page 20 20
  • Page 21 21
  • Page 22 22
  • Page 23 23
  • Page 24 24
  • Page 25 25
  • Page 26 26
  • Page 27 27
  • Page 28 28
  • Page 29 29
  • Page 30 30
  • Page 31 31
  • Page 32 32
  • Page 33 33
  • Page 34 34
  • Page 35 35
  • Page 36 36
  • Page 37 37
  • Page 38 38
  • Page 39 39
  • Page 40 40
  • Page 41 41
  • Page 42 42
  • Page 43 43
  • Page 44 44
  • Page 45 45
  • Page 46 46
  • Page 47 47
  • Page 48 48
  • Page 49 49
  • Page 50 50
  • Page 51 51
  • Page 52 52
  • Page 53 53
  • Page 54 54
  • Page 55 55
  • Page 56 56
  • Page 57 57
  • Page 58 58
  • Page 59 59
  • Page 60 60
  • Page 61 61
  • Page 62 62
  • Page 63 63
  • Page 64 64
  • Page 65 65
  • Page 66 66
  • Page 67 67
  • Page 68 68
  • Page 69 69
  • Page 70 70
  • Page 71 71
  • Page 72 72
  • Page 73 73
  • Page 74 74
  • Page 75 75
  • Page 76 76
  • Page 77 77
  • Page 78 78
  • Page 79 79
  • Page 80 80
  • Page 81 81
  • Page 82 82
  • Page 83 83
  • Page 84 84
  • Page 85 85
  • Page 86 86
  • Page 87 87
  • Page 88 88
  • Page 89 89
  • Page 90 90
  • Page 91 91
  • Page 92 92
  • Page 93 93
  • Page 94 94
  • Page 95 95
  • Page 96 96
  • Page 97 97
  • Page 98 98
  • Page 99 99
  • Page 100 100
  • Page 101 101
  • Page 102 102
  • Page 103 103
  • Page 104 104
  • Page 105 105
  • Page 106 106
  • Page 107 107
  • Page 108 108
  • Page 109 109
  • Page 110 110
  • Page 111 111
  • Page 112 112
  • Page 113 113
  • Page 114 114
  • Page 115 115
  • Page 116 116
  • Page 117 117
  • Page 118 118
  • Page 119 119
  • Page 120 120
  • Page 121 121
  • Page 122 122
  • Page 123 123
  • Page 124 124
  • Page 125 125
  • Page 126 126
  • Page 127 127
  • Page 128 128
  • Page 129 129
  • Page 130 130
  • Page 131 131
  • Page 132 132
  • Page 133 133
  • Page 134 134
  • Page 135 135
  • Page 136 136
  • Page 137 137
  • Page 138 138
  • Page 139 139
  • Page 140 140
  • Page 141 141
  • Page 142 142
  • Page 143 143
  • Page 144 144
  • Page 145 145
  • Page 146 146
  • Page 147 147
  • Page 148 148
  • Page 149 149
  • Page 150 150
  • Page 151 151
  • Page 152 152
  • Page 153 153
  • Page 154 154
  • Page 155 155
  • Page 156 156
  • Page 157 157
  • Page 158 158
  • Page 159 159
  • Page 160 160
  • Page 161 161
  • Page 162 162
  • Page 163 163
  • Page 164 164
  • Page 165 165
  • Page 166 166
  • Page 167 167
  • Page 168 168
  • Page 169 169
  • Page 170 170
  • Page 171 171
  • Page 172 172
  • Page 173 173
  • Page 174 174
  • Page 175 175
  • Page 176 176
  • Page 177 177
  • Page 178 178
  • Page 179 179
  • Page 180 180
  • Page 181 181
  • Page 182 182
  • Page 183 183
  • Page 184 184
  • Page 185 185
  • Page 186 186
  • Page 187 187
  • Page 188 188
  • Page 189 189
  • Page 190 190
  • Page 191 191
  • Page 192 192
  • Page 193 193
  • Page 194 194
  • Page 195 195
  • Page 196 196
  • Page 197 197
  • Page 198 198
  • Page 199 199
  • Page 200 200
  • Page 201 201
  • Page 202 202
  • Page 203 203
  • Page 204 204
  • Page 205 205
  • Page 206 206
  • Page 207 207
  • Page 208 208
  • Page 209 209
  • Page 210 210
  • Page 211 211
  • Page 212 212
  • Page 213 213
  • Page 214 214
  • Page 215 215
  • Page 216 216
  • Page 217 217
  • Page 218 218
  • Page 219 219
  • Page 220 220
  • Page 221 221
  • Page 222 222
  • Page 223 223
  • Page 224 224
  • Page 225 225
  • Page 226 226
  • Page 227 227
  • Page 228 228
  • Page 229 229
  • Page 230 230
  • Page 231 231
  • Page 232 232
  • Page 233 233
  • Page 234 234
  • Page 235 235
  • Page 236 236
  • Page 237 237
  • Page 238 238
  • Page 239 239
  • Page 240 240
  • Page 241 241
  • Page 242 242
  • Page 243 243
  • Page 244 244
  • Page 245 245
  • Page 246 246
  • Page 247 247
  • Page 248 248
  • Page 249 249
  • Page 250 250
  • Page 251 251
  • Page 252 252
  • Page 253 253
  • Page 254 254
  • Page 255 255
  • Page 256 256
  • Page 257 257
  • Page 258 258
  • Page 259 259
  • Page 260 260
  • Page 261 261
  • Page 262 262
  • Page 263 263
  • Page 264 264
  • Page 265 265
  • Page 266 266
  • Page 267 267
  • Page 268 268
  • Page 269 269
  • Page 270 270
  • Page 271 271
  • Page 272 272
  • Page 273 273
  • Page 274 274
  • Page 275 275
  • Page 276 276
  • Page 277 277
  • Page 278 278
  • Page 279 279
  • Page 280 280
  • Page 281 281
  • Page 282 282
  • Page 283 283
  • Page 284 284
  • Page 285 285
  • Page 286 286
  • Page 287 287
  • Page 288 288
  • Page 289 289
  • Page 290 290
  • Page 291 291
  • Page 292 292
  • Page 293 293
  • Page 294 294
  • Page 295 295
  • Page 296 296
  • Page 297 297
  • Page 298 298
  • Page 299 299
  • Page 300 300
  • Page 301 301
  • Page 302 302
  • Page 303 303
  • Page 304 304
  • Page 305 305
  • Page 306 306
  • Page 307 307
  • Page 308 308
  • Page 309 309
  • Page 310 310
  • Page 311 311
  • Page 312 312
  • Page 313 313
  • Page 314 314
  • Page 315 315
  • Page 316 316
  • Page 317 317
  • Page 318 318
  • Page 319 319
  • Page 320 320
  • Page 321 321
  • Page 322 322
  • Page 323 323
  • Page 324 324
  • Page 325 325
  • Page 326 326
  • Page 327 327
  • Page 328 328
  • Page 329 329
  • Page 330 330
  • Page 331 331
  • Page 332 332
  • Page 333 333
  • Page 334 334
  • Page 335 335
  • Page 336 336
  • Page 337 337
  • Page 338 338
  • Page 339 339
  • Page 340 340
  • Page 341 341
  • Page 342 342
  • Page 343 343
  • Page 344 344
  • Page 345 345
  • Page 346 346
  • Page 347 347
  • Page 348 348
  • Page 349 349
  • Page 350 350
  • Page 351 351
  • Page 352 352
  • Page 353 353
  • Page 354 354
  • Page 355 355
  • Page 356 356
  • Page 357 357
  • Page 358 358
  • Page 359 359
  • Page 360 360
  • Page 361 361
  • Page 362 362
  • Page 363 363
  • Page 364 364
  • Page 365 365
  • Page 366 366
  • Page 367 367
  • Page 368 368
  • Page 369 369
  • Page 370 370
  • Page 371 371
  • Page 372 372
  • Page 373 373
  • Page 374 374
  • Page 375 375
  • Page 376 376
  • Page 377 377
  • Page 378 378
  • Page 379 379
  • Page 380 380
  • Page 381 381
  • Page 382 382
  • Page 383 383
  • Page 384 384
  • Page 385 385
  • Page 386 386
  • Page 387 387
  • Page 388 388
  • Page 389 389
  • Page 390 390
  • Page 391 391
  • Page 392 392
  • Page 393 393
  • Page 394 394
  • Page 395 395
  • Page 396 396
  • Page 397 397
  • Page 398 398
  • Page 399 399
  • Page 400 400
  • Page 401 401
  • Page 402 402
  • Page 403 403
  • Page 404 404
  • Page 405 405
  • Page 406 406
  • Page 407 407
  • Page 408 408
  • Page 409 409
  • Page 410 410
  • Page 411 411
  • Page 412 412
  • Page 413 413
  • Page 414 414
  • Page 415 415
  • Page 416 416
  • Page 417 417
  • Page 418 418
  • Page 419 419
  • Page 420 420
  • Page 421 421
  • Page 422 422
  • Page 423 423
  • Page 424 424
  • Page 425 425
  • Page 426 426
  • Page 427 427
  • Page 428 428
  • Page 429 429
  • Page 430 430
  • Page 431 431
  • Page 432 432
  • Page 433 433
  • Page 434 434
  • Page 435 435
  • Page 436 436
  • Page 437 437
  • Page 438 438
  • Page 439 439
  • Page 440 440
  • Page 441 441
  • Page 442 442
  • Page 443 443
  • Page 444 444
  • Page 445 445
  • Page 446 446
  • Page 447 447
  • Page 448 448
  • Page 449 449
  • Page 450 450
  • Page 451 451
  • Page 452 452
  • Page 453 453
  • Page 454 454
  • Page 455 455
  • Page 456 456
  • Page 457 457
  • Page 458 458
  • Page 459 459
  • Page 460 460
  • Page 461 461
  • Page 462 462
  • Page 463 463
  • Page 464 464
  • Page 465 465
  • Page 466 466
  • Page 467 467
  • Page 468 468
  • Page 469 469
  • Page 470 470
  • Page 471 471
  • Page 472 472
  • Page 473 473
  • Page 474 474
  • Page 475 475
  • Page 476 476
  • Page 477 477
  • Page 478 478
  • Page 479 479
  • Page 480 480
  • Page 481 481
  • Page 482 482
  • Page 483 483
  • Page 484 484
  • Page 485 485
  • Page 486 486
  • Page 487 487
  • Page 488 488
  • Page 489 489
  • Page 490 490
  • Page 491 491
  • Page 492 492
  • Page 493 493
  • Page 494 494
  • Page 495 495
  • Page 496 496
  • Page 497 497
  • Page 498 498
  • Page 499 499
  • Page 500 500
  • Page 501 501
  • Page 502 502
  • Page 503 503
  • Page 504 504
  • Page 505 505
  • Page 506 506
  • Page 507 507
  • Page 508 508
  • Page 509 509
  • Page 510 510
  • Page 511 511
  • Page 512 512
  • Page 513 513
  • Page 514 514
  • Page 515 515
  • Page 516 516
  • Page 517 517
  • Page 518 518
  • Page 519 519
  • Page 520 520
  • Page 521 521
  • Page 522 522
  • Page 523 523
  • Page 524 524
  • Page 525 525
  • Page 526 526
  • Page 527 527
  • Page 528 528
  • Page 529 529
  • Page 530 530
  • Page 531 531
  • Page 532 532
  • Page 533 533
  • Page 534 534
  • Page 535 535
  • Page 536 536
  • Page 537 537
  • Page 538 538
  • Page 539 539
  • Page 540 540
  • Page 541 541
  • Page 542 542
  • Page 543 543
  • Page 544 544
  • Page 545 545
  • Page 546 546
  • Page 547 547
  • Page 548 548
  • Page 549 549
  • Page 550 550
  • Page 551 551
  • Page 552 552
  • Page 553 553
  • Page 554 554
  • Page 555 555
  • Page 556 556
  • Page 557 557
  • Page 558 558
  • Page 559 559
  • Page 560 560
  • Page 561 561
  • Page 562 562
  • Page 563 563
  • Page 564 564
  • Page 565 565
  • Page 566 566
  • Page 567 567
  • Page 568 568
  • Page 569 569
  • Page 570 570
  • Page 571 571
  • Page 572 572
  • Page 573 573
  • Page 574 574
  • Page 575 575
  • Page 576 576
  • Page 577 577
  • Page 578 578
  • Page 579 579
  • Page 580 580
  • Page 581 581
  • Page 582 582
  • Page 583 583
  • Page 584 584
  • Page 585 585
  • Page 586 586
  • Page 587 587
  • Page 588 588
  • Page 589 589
  • Page 590 590
  • Page 591 591
  • Page 592 592
  • Page 593 593
  • Page 594 594
  • Page 595 595
  • Page 596 596
  • Page 597 597
  • Page 598 598
  • Page 599 599
  • Page 600 600
  • Page 601 601
  • Page 602 602
  • Page 603 603
  • Page 604 604
  • Page 605 605
  • Page 606 606
  • Page 607 607
  • Page 608 608
  • Page 609 609
  • Page 610 610
  • Page 611 611
  • Page 612 612
  • Page 613 613
  • Page 614 614
  • Page 615 615
  • Page 616 616
  • Page 617 617
  • Page 618 618
  • Page 619 619
  • Page 620 620
  • Page 621 621
  • Page 622 622
  • Page 623 623
  • Page 624 624
  • Page 625 625
  • Page 626 626
  • Page 627 627
  • Page 628 628
  • Page 629 629
  • Page 630 630
  • Page 631 631
  • Page 632 632
  • Page 633 633
  • Page 634 634
  • Page 635 635
  • Page 636 636
  • Page 637 637
  • Page 638 638
  • Page 639 639
  • Page 640 640
  • Page 641 641
  • Page 642 642
  • Page 643 643
  • Page 644 644
  • Page 645 645
  • Page 646 646
  • Page 647 647
  • Page 648 648
  • Page 649 649
  • Page 650 650
  • Page 651 651
  • Page 652 652
  • Page 653 653
  • Page 654 654
  • Page 655 655
  • Page 656 656
  • Page 657 657
  • Page 658 658
  • Page 659 659
  • Page 660 660
  • Page 661 661
  • Page 662 662
  • Page 663 663
  • Page 664 664
  • Page 665 665
  • Page 666 666
  • Page 667 667
  • Page 668 668
  • Page 669 669
  • Page 670 670
  • Page 671 671
  • Page 672 672
  • Page 673 673
  • Page 674 674
  • Page 675 675
  • Page 676 676
  • Page 677 677
  • Page 678 678
  • Page 679 679
  • Page 680 680
  • Page 681 681
  • Page 682 682
  • Page 683 683
  • Page 684 684
  • Page 685 685
  • Page 686 686
  • Page 687 687
  • Page 688 688
  • Page 689 689
  • Page 690 690
  • Page 691 691
  • Page 692 692
  • Page 693 693
  • Page 694 694
  • Page 695 695
  • Page 696 696
  • Page 697 697
  • Page 698 698
  • Page 699 699
  • Page 700 700
  • Page 701 701
  • Page 702 702
  • Page 703 703
  • Page 704 704
  • Page 705 705
  • Page 706 706
  • Page 707 707
  • Page 708 708
  • Page 709 709
  • Page 710 710
  • Page 711 711
  • Page 712 712
  • Page 713 713
  • Page 714 714
  • Page 715 715
  • Page 716 716
  • Page 717 717
  • Page 718 718
  • Page 719 719
  • Page 720 720
  • Page 721 721
  • Page 722 722
  • Page 723 723
  • Page 724 724
  • Page 725 725
  • Page 726 726
  • Page 727 727
  • Page 728 728
  • Page 729 729
  • Page 730 730
  • Page 731 731
  • Page 732 732
  • Page 733 733
  • Page 734 734
  • Page 735 735
  • Page 736 736
  • Page 737 737
  • Page 738 738
  • Page 739 739
  • Page 740 740
  • Page 741 741
  • Page 742 742
  • Page 743 743
  • Page 744 744
  • Page 745 745
  • Page 746 746
  • Page 747 747
  • Page 748 748
  • Page 749 749
  • Page 750 750
  • Page 751 751
  • Page 752 752
  • Page 753 753
  • Page 754 754
  • Page 755 755
  • Page 756 756
  • Page 757 757
  • Page 758 758
  • Page 759 759
  • Page 760 760
  • Page 761 761
  • Page 762 762
  • Page 763 763
  • Page 764 764
  • Page 765 765
  • Page 766 766
  • Page 767 767
  • Page 768 768
  • Page 769 769
  • Page 770 770
  • Page 771 771
  • Page 772 772
  • Page 773 773
  • Page 774 774
  • Page 775 775
  • Page 776 776
  • Page 777 777
  • Page 778 778
  • Page 779 779
  • Page 780 780
  • Page 781 781
  • Page 782 782
  • Page 783 783
  • Page 784 784
  • Page 785 785
  • Page 786 786
  • Page 787 787
  • Page 788 788
  • Page 789 789
  • Page 790 790
  • Page 791 791
  • Page 792 792
  • Page 793 793
  • Page 794 794
  • Page 795 795
  • Page 796 796
  • Page 797 797
  • Page 798 798
  • Page 799 799
  • Page 800 800
  • Page 801 801
  • Page 802 802
  • Page 803 803
  • Page 804 804
  • Page 805 805
  • Page 806 806
  • Page 807 807
  • Page 808 808
  • Page 809 809
  • Page 810 810
  • Page 811 811
  • Page 812 812
  • Page 813 813
  • Page 814 814
  • Page 815 815
  • Page 816 816
  • Page 817 817
  • Page 818 818
  • Page 819 819
  • Page 820 820
  • Page 821 821
  • Page 822 822
  • Page 823 823
  • Page 824 824
  • Page 825 825
  • Page 826 826
  • Page 827 827
  • Page 828 828
  • Page 829 829
  • Page 830 830
  • Page 831 831
  • Page 832 832
  • Page 833 833
  • Page 834 834
  • Page 835 835
  • Page 836 836
  • Page 837 837
  • Page 838 838
  • Page 839 839
  • Page 840 840
  • Page 841 841
  • Page 842 842
  • Page 843 843
  • Page 844 844
  • Page 845 845
  • Page 846 846
  • Page 847 847
  • Page 848 848
  • Page 849 849
  • Page 850 850
  • Page 851 851
  • Page 852 852
  • Page 853 853
  • Page 854 854
  • Page 855 855
  • Page 856 856
  • Page 857 857
  • Page 858 858
  • Page 859 859
  • Page 860 860
  • Page 861 861
  • Page 862 862
  • Page 863 863
  • Page 864 864
  • Page 865 865
  • Page 866 866
  • Page 867 867
  • Page 868 868
  • Page 869 869
  • Page 870 870
  • Page 871 871
  • Page 872 872
  • Page 873 873
  • Page 874 874
  • Page 875 875
  • Page 876 876
  • Page 877 877
  • Page 878 878
  • Page 879 879
  • Page 880 880
  • Page 881 881
  • Page 882 882
  • Page 883 883
  • Page 884 884
  • Page 885 885
  • Page 886 886
  • Page 887 887
  • Page 888 888
  • Page 889 889
  • Page 890 890
  • Page 891 891
  • Page 892 892
  • Page 893 893
  • Page 894 894
  • Page 895 895
  • Page 896 896
  • Page 897 897
  • Page 898 898
  • Page 899 899
  • Page 900 900
  • Page 901 901
  • Page 902 902
  • Page 903 903
  • Page 904 904
  • Page 905 905
  • Page 906 906
  • Page 907 907
  • Page 908 908
  • Page 909 909
  • Page 910 910
  • Page 911 911
  • Page 912 912
  • Page 913 913
  • Page 914 914
  • Page 915 915
  • Page 916 916
  • Page 917 917
  • Page 918 918
  • Page 919 919
  • Page 920 920
  • Page 921 921
  • Page 922 922
  • Page 923 923
  • Page 924 924
  • Page 925 925
  • Page 926 926
  • Page 927 927
  • Page 928 928
  • Page 929 929
  • Page 930 930
  • Page 931 931
  • Page 932 932
  • Page 933 933
  • Page 934 934
  • Page 935 935
  • Page 936 936
  • Page 937 937
  • Page 938 938
  • Page 939 939
  • Page 940 940
  • Page 941 941
  • Page 942 942
  • Page 943 943
  • Page 944 944
  • Page 945 945
  • Page 946 946
  • Page 947 947
  • Page 948 948
  • Page 949 949
  • Page 950 950
  • Page 951 951
  • Page 952 952
  • Page 953 953
  • Page 954 954
  • Page 955 955
  • Page 956 956
  • Page 957 957
  • Page 958 958
  • Page 959 959
  • Page 960 960
  • Page 961 961
  • Page 962 962
  • Page 963 963
  • Page 964 964
  • Page 965 965
  • Page 966 966
  • Page 967 967
  • Page 968 968
  • Page 969 969
  • Page 970 970
  • Page 971 971
  • Page 972 972
  • Page 973 973
  • Page 974 974
  • Page 975 975
  • Page 976 976
  • Page 977 977
  • Page 978 978
  • Page 979 979
  • Page 980 980
  • Page 981 981
  • Page 982 982
  • Page 983 983
  • Page 984 984
  • Page 985 985
  • Page 986 986
  • Page 987 987
  • Page 988 988
  • Page 989 989
  • Page 990 990
  • Page 991 991
  • Page 992 992
  • Page 993 993
  • Page 994 994
  • Page 995 995
  • Page 996 996
  • Page 997 997
  • Page 998 998
  • Page 999 999
  • Page 1000 1000
  • Page 1001 1001
  • Page 1002 1002
  • Page 1003 1003
  • Page 1004 1004
  • Page 1005 1005
  • Page 1006 1006
  • Page 1007 1007
  • Page 1008 1008
  • Page 1009 1009
  • Page 1010 1010
  • Page 1011 1011
  • Page 1012 1012
  • Page 1013 1013
  • Page 1014 1014
  • Page 1015 1015
  • Page 1016 1016
  • Page 1017 1017
  • Page 1018 1018
  • Page 1019 1019
  • Page 1020 1020
  • Page 1021 1021
  • Page 1022 1022
  • Page 1023 1023
  • Page 1024 1024
  • Page 1025 1025
  • Page 1026 1026
  • Page 1027 1027
  • Page 1028 1028
  • Page 1029 1029
  • Page 1030 1030
  • Page 1031 1031
  • Page 1032 1032
  • Page 1033 1033
  • Page 1034 1034
  • Page 1035 1035
  • Page 1036 1036
  • Page 1037 1037
  • Page 1038 1038
  • Page 1039 1039
  • Page 1040 1040
  • Page 1041 1041
  • Page 1042 1042
  • Page 1043 1043
  • Page 1044 1044
  • Page 1045 1045
  • Page 1046 1046
  • Page 1047 1047
  • Page 1048 1048
  • Page 1049 1049
  • Page 1050 1050
  • Page 1051 1051
  • Page 1052 1052
  • Page 1053 1053
  • Page 1054 1054
  • Page 1055 1055
  • Page 1056 1056
  • Page 1057 1057
  • Page 1058 1058
  • Page 1059 1059
  • Page 1060 1060
  • Page 1061 1061
  • Page 1062 1062
  • Page 1063 1063
  • Page 1064 1064
  • Page 1065 1065
  • Page 1066 1066
  • Page 1067 1067
  • Page 1068 1068
  • Page 1069 1069
  • Page 1070 1070
  • Page 1071 1071
  • Page 1072 1072
  • Page 1073 1073
  • Page 1074 1074
  • Page 1075 1075
  • Page 1076 1076
  • Page 1077 1077
  • Page 1078 1078
  • Page 1079 1079
  • Page 1080 1080
  • Page 1081 1081
  • Page 1082 1082
  • Page 1083 1083
  • Page 1084 1084
  • Page 1085 1085
  • Page 1086 1086
  • Page 1087 1087
  • Page 1088 1088
  • Page 1089 1089
  • Page 1090 1090
  • Page 1091 1091
  • Page 1092 1092
  • Page 1093 1093
  • Page 1094 1094
  • Page 1095 1095
  • Page 1096 1096
  • Page 1097 1097
  • Page 1098 1098
  • Page 1099 1099
  • Page 1100 1100
  • Page 1101 1101
  • Page 1102 1102
  • Page 1103 1103
  • Page 1104 1104
  • Page 1105 1105
  • Page 1106 1106
  • Page 1107 1107
  • Page 1108 1108
  • Page 1109 1109
  • Page 1110 1110
  • Page 1111 1111
  • Page 1112 1112
  • Page 1113 1113
  • Page 1114 1114
  • Page 1115 1115
  • Page 1116 1116
  • Page 1117 1117
  • Page 1118 1118
  • Page 1119 1119
  • Page 1120 1120
  • Page 1121 1121
  • Page 1122 1122
  • Page 1123 1123
  • Page 1124 1124
  • Page 1125 1125
  • Page 1126 1126
  • Page 1127 1127
  • Page 1128 1128
  • Page 1129 1129
  • Page 1130 1130
  • Page 1131 1131
  • Page 1132 1132
  • Page 1133 1133
  • Page 1134 1134
  • Page 1135 1135
  • Page 1136 1136
  • Page 1137 1137
  • Page 1138 1138
  • Page 1139 1139
  • Page 1140 1140
  • Page 1141 1141
  • Page 1142 1142
  • Page 1143 1143
  • Page 1144 1144
  • Page 1145 1145
  • Page 1146 1146
  • Page 1147 1147
  • Page 1148 1148
  • Page 1149 1149
  • Page 1150 1150
  • Page 1151 1151
  • Page 1152 1152
  • Page 1153 1153
  • Page 1154 1154
  • Page 1155 1155
  • Page 1156 1156
  • Page 1157 1157
  • Page 1158 1158
  • Page 1159 1159
  • Page 1160 1160
  • Page 1161 1161
  • Page 1162 1162
  • Page 1163 1163
  • Page 1164 1164
  • Page 1165 1165
  • Page 1166 1166
  • Page 1167 1167
  • Page 1168 1168
  • Page 1169 1169
  • Page 1170 1170
  • Page 1171 1171
  • Page 1172 1172
  • Page 1173 1173
  • Page 1174 1174
  • Page 1175 1175
  • Page 1176 1176
  • Page 1177 1177
  • Page 1178 1178
  • Page 1179 1179
  • Page 1180 1180
  • Page 1181 1181
  • Page 1182 1182
  • Page 1183 1183
  • Page 1184 1184
  • Page 1185 1185
  • Page 1186 1186
  • Page 1187 1187
  • Page 1188 1188
  • Page 1189 1189
  • Page 1190 1190
  • Page 1191 1191
  • Page 1192 1192
  • Page 1193 1193
  • Page 1194 1194
  • Page 1195 1195
  • Page 1196 1196
  • Page 1197 1197
  • Page 1198 1198
  • Page 1199 1199
  • Page 1200 1200
  • Page 1201 1201
  • Page 1202 1202
  • Page 1203 1203
  • Page 1204 1204
  • Page 1205 1205
  • Page 1206 1206
  • Page 1207 1207
  • Page 1208 1208
  • Page 1209 1209
  • Page 1210 1210
  • Page 1211 1211
  • Page 1212 1212
  • Page 1213 1213
  • Page 1214 1214
  • Page 1215 1215
  • Page 1216 1216
  • Page 1217 1217
  • Page 1218 1218
  • Page 1219 1219
  • Page 1220 1220
  • Page 1221 1221
  • Page 1222 1222
  • Page 1223 1223
  • Page 1224 1224
  • Page 1225 1225
  • Page 1226 1226
  • Page 1227 1227
  • Page 1228 1228
  • Page 1229 1229
  • Page 1230 1230
  • Page 1231 1231
  • Page 1232 1232
  • Page 1233 1233
  • Page 1234 1234
  • Page 1235 1235
  • Page 1236 1236
  • Page 1237 1237
  • Page 1238 1238
  • Page 1239 1239
  • Page 1240 1240
  • Page 1241 1241
  • Page 1242 1242
  • Page 1243 1243
  • Page 1244 1244
  • Page 1245 1245
  • Page 1246 1246
  • Page 1247 1247
  • Page 1248 1248
  • Page 1249 1249
  • Page 1250 1250
  • Page 1251 1251
  • Page 1252 1252
  • Page 1253 1253
  • Page 1254 1254
  • Page 1255 1255
  • Page 1256 1256
  • Page 1257 1257
  • Page 1258 1258
  • Page 1259 1259
  • Page 1260 1260
  • Page 1261 1261
  • Page 1262 1262
  • Page 1263 1263
  • Page 1264 1264
  • Page 1265 1265
  • Page 1266 1266
  • Page 1267 1267
  • Page 1268 1268
  • Page 1269 1269
  • Page 1270 1270
  • Page 1271 1271
  • Page 1272 1272
  • Page 1273 1273
  • Page 1274 1274
  • Page 1275 1275
  • Page 1276 1276
  • Page 1277 1277
  • Page 1278 1278
  • Page 1279 1279
  • Page 1280 1280
  • Page 1281 1281
  • Page 1282 1282
  • Page 1283 1283
  • Page 1284 1284
  • Page 1285 1285
  • Page 1286 1286
  • Page 1287 1287
  • Page 1288 1288
  • Page 1289 1289
  • Page 1290 1290
  • Page 1291 1291
  • Page 1292 1292
  • Page 1293 1293
  • Page 1294 1294
  • Page 1295 1295
  • Page 1296 1296
  • Page 1297 1297
  • Page 1298 1298
  • Page 1299 1299
  • Page 1300 1300
  • Page 1301 1301
  • Page 1302 1302
  • Page 1303 1303
  • Page 1304 1304
  • Page 1305 1305
  • Page 1306 1306
  • Page 1307 1307
  • Page 1308 1308
  • Page 1309 1309
  • Page 1310 1310
  • Page 1311 1311
  • Page 1312 1312
  • Page 1313 1313
  • Page 1314 1314
  • Page 1315 1315
  • Page 1316 1316
  • Page 1317 1317
  • Page 1318 1318
  • Page 1319 1319
  • Page 1320 1320
  • Page 1321 1321
  • Page 1322 1322
  • Page 1323 1323
  • Page 1324 1324
  • Page 1325 1325
  • Page 1326 1326
  • Page 1327 1327
  • Page 1328 1328
  • Page 1329 1329
  • Page 1330 1330
  • Page 1331 1331
  • Page 1332 1332
  • Page 1333 1333
  • Page 1334 1334
  • Page 1335 1335
  • Page 1336 1336
  • Page 1337 1337
  • Page 1338 1338
  • Page 1339 1339
  • Page 1340 1340
  • Page 1341 1341
  • Page 1342 1342
  • Page 1343 1343
  • Page 1344 1344
  • Page 1345 1345
  • Page 1346 1346
  • Page 1347 1347
  • Page 1348 1348
  • Page 1349 1349
  • Page 1350 1350
  • Page 1351 1351
  • Page 1352 1352
  • Page 1353 1353

NXP MPC823E Reference guide

Type
Reference guide

Ask a question and I''ll find the answer in the document

Finding information in a document is now easier with AI