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MPC860 Overview
Memory Map
Hardware Interface Overview
PowerPC Core Overview
PowerPC Core Register Set
MPC860 Instruction Set
PowerPC Exceptions
Instruction and Data Caches
Memory Management Unit
Instruction Execution Timing
System Interface Unit
Reset
External Signals
MPC860 External Bus Interface
Clocks and Power Control
Memory Controller
PCMCIA Interface
Communications Processor Module and CPM Timers
Communications Processor
SDMA Channels and IDMA Emulation
Serial Interface
SCC Introduction
SCC UART Mode
SCC HDLC Mode
SCC AppleTalk Mode
SCC Asynchronous HDLC Mode and IrDA
SCC BISYNC Mode
SCC Ethernet Mode
SCC Transparent Mode
Serial Management Controller
Serial Peripheral Interface
I C Controller
Parallel Interface Port
Parallel I/O Port
CPM Interrupt Controller
Digital Signal Processing
System Development and Debugging
IEEE 1149.1 Test Access Port
Byte Ordering
Serial Communciation Performance
Register Quick Reference Guide
MPC860 Instruction Set
Glossary
Index
2
2
3
4
5
6
7
8
9
A
B
C
1
GLO
IND
11
12
13
14
15
16
17
18
10
19
21
22
23
24
25
26
27
28
20
29
31
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MPC860 Overview
Memory Map
Hardware Interface Overview
PowerPC Core Overview
PowerPC Core Register Set
MPC860 Instruction Set
PowerPC Exceptions
Instruction and Data Caches
Memory Management Unit
Instruction Execution Timing
System Interface Unit
Reset
External Signals
MPC860 External Bus Interface
Clocks and Power Control
Memory Controller
PCMCIA Interface
Communications Processor Module and CPM Timers
Communications Processor
SDMA Channels and IDMA Emulation
Serial Interface
SCC Introduction
SCC UART Mode
SCC HDLC Mode
SCC AppleTalk Mode
SCC Asynchronous HDLC Mode and IrDA
SCC BISYNC Mode
SCC Ethernet Mode
SCC Transparent Mode
Serial Management Controller
Serial Peripheral Interface
I C Controller
Parallel Interface Port
Parallel I/O Port
CPM Interrupt Controller
Digital Signal Processing
System Development and Debugging
IEEE 1149.1 Test Access Port
Byte Ordering
Serial Communciation Performance
Register Quick Reference Guide
MPC860 Instruction Set
Glossary
Index
2
2
3
4
5
6
7
8
9
A
B
C
1
GLO
IND
11
12
13
14
15
16
17
18
10
19
21
22
23
24
25
26
27
28
20
29
31
32
33
34
35
36
37
38
30
D
MPC860UM/AD
07/98
REV. 1
MPC860 PowerQUICC
ª
UserÕs Manual
This document contains information on a new product under development. Motorola reserves the right to change or discontinue this product without
notice. Information in this document is provided solely to enable system and software implementers to use PowerPC microprocessors. There are no
express or implied copyright licenses granted hereunder to design or fabricate PowerPC integrated circuits or integrated circuits based on the information
in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product
or circuit, and speciÞcally disclaims any and all liability, including without limitation consequential or incidental damages. ÒTypicalÓ parameters can and do
vary in different applications. All operating parameters, including ÒTypicalsÓ must be validated for each customer application by customerÕs technical
experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized
for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other
application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its ofÞcers, employees, subsidiaries,
afÞliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent
regarding the design or manufacture of the part.
Motorola and are registered trademarks and QUICC and PowerQUICC are trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/
AfÞrmative Action Employer.
The PowerPC name, the PowerPC logotype, PowerPC 601, PowerPC 603, PowerPC 603e, PowerPC 604, and RS/6000 are trademarks of International
Business Machines Corporation used by Motorola under license from International Business Machines Corporation.
I2C is a registered trademark of Phillips Corporation.
© Motorola Inc. 1998. All rights reserved.
Portions hereof © International Business Machines Corp. 1991Ð1998. All rights reserved.
MOTOROLA
Contents
v
CONTENTS
Paragraph
Number
Title
Page
Number
About This Book
Before Using this Manual ...................................................................................lxiii
Audience..............................................................................................................lxiii
Organization ........................................................................................................lxiv
Suggested Reading ............................................................................................lxviii
MPC8xx Documentation.................................................................................. lxviii
PowerPC Documentation ................................................................................. lxviii
Conventions.........................................................................................................lxix
Acronyms and Abbreviations............................................................................... lxx
PowerPC Architecture Terminology Conventions............................................lxxiii
Intended Audience.............................................................................................. lxxv
Contents.............................................................................................................. lxxv
Conventions........................................................................................................ lxxv
Acronyms and Abbreviations............................................................................lxxvi
Chapter 1
MPC860 Overview
1.1 Features ................................................................................................................1-1
1.2 Architecture Overview .........................................................................................1-5
1.3 Embedded PowerPC Core....................................................................................1-6
1.4 System Interface Unit (SIU).................................................................................1-7
1.5 PCMCIA Controller .............................................................................................1-7
1.6 Power Management..............................................................................................1-7
1.7 Communications Processor Module (CPM) ........................................................1-8
1.8 Software Compatibility Issues .............................................................................1-9
Chapter 2
Memory Map
Chapter 3
Hardware Interface Overview
3.1 System Bus Signals ..............................................................................................3-3
3.2 System Bus Signals ..............................................................................................3-3
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Page
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Chapter 4
The PowerPC Core
4.1 PowerPC Architecture Overview .........................................................................4-1
4.1.1 Levels of the PowerPC Architecture ................................................................4-3
4.2 Features.................................................................................................................4-4
4.3 Basic Structure of the Core...................................................................................4-5
4.3.1 Instruction Flow................................................................................................4-6
4.3.2 Basic Instruction Pipeline.................................................................................4-7
4.3.3 Instruction Unit.................................................................................................4-7
4.3.3.1 Branch Operations........................................................................................4-7
4.3.3.2 Dispatching Instructions...............................................................................4-9
4.4 Register Set...........................................................................................................4-9
4.5 Execution Units ....................................................................................................4-9
4.5.1 Branch Processing Unit ..................................................................................4-10
4.5.2 Integer Unit.....................................................................................................4-10
4.5.3 Load/Store Unit ..............................................................................................4-10
4.5.3.1 Executing Load/Store Instructions .............................................................4-12
4.5.3.2 Serializing Load/Store Instructions ............................................................4-12
4.5.3.3 Store Accesses............................................................................................4-12
4.5.3.4 Nonspeculative Load Instructions ..............................................................4-12
4.5.3.5 Unaligned Accesses....................................................................................4-13
4.5.3.6 Atomic Update Primitives ..........................................................................4-13
4.6 The MPC860 and the PowerPC Architecture.....................................................4-14
Chapter 5
PowerPC Core Register Set
5.1 MPC860 Register Implementation .......................................................................5-1
5.1.1 PowerPC RegistersÑUser Registers................................................................5-2
5.1.1.1 PowerPC User-Level Register Bit Assignments ..........................................5-2
5.1.1.1.1 Condition Register (CR)...........................................................................5-2
5.1.1.1.2 Condition Register CR0 Field Definition.................................................5-3
5.1.1.1.3 XER..........................................................................................................5-3
5.1.1.1.4 Time Base Registers.................................................................................5-4
5.1.2 PowerPC RegistersÑSupervisor Registers......................................................5-4
5.1.2.1 DAR, DSISR, and BAR Operation ..............................................................5-5
5.1.2.2 Unsupported Registers .................................................................................5-6
5.1.2.3 PowerPC Supervisor-Level Register Bit Assignments ................................5-6
5.1.2.3.1 Machine State Register (MSR) ................................................................5-6
5.1.2.3.2 Processor Version Register ......................................................................5-8
5.1.3 MPC860-Specific SPRs....................................................................................5-8
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5.1.3.1 Accessing SPRs..........................................................................................5-11
5.2 Register Initialization at Reset ...........................................................................5-11
Chapter 6
MPC860 Instruction Set
6.1 Operand Conventions...........................................................................................6-1
6.1.1 Data Organization in Memory and Data Transfers ..........................................6-1
6.1.2 Aligned and Misaligned Accesses ...................................................................6-1
6.2 Instruction Set Summary......................................................................................6-2
6.2.1 Classes of Instructions......................................................................................6-3
6.2.1.1 Definition of Boundedly Undefined ............................................................6-4
6.2.1.2 Defined Instruction Class.............................................................................6-4
6.2.1.3 Illegal Instruction Class ...............................................................................6-4
6.2.1.4 Reserved Instruction Class...........................................................................6-5
6.2.2 Addressing Modes............................................................................................6-5
6.2.2.1 Memory Addressing.....................................................................................6-5
6.2.2.2 Effective Address Calculation .....................................................................6-6
6.2.2.3 Synchronization ...........................................................................................6-6
6.2.2.3.1 Context Synchronization..........................................................................6-6
6.2.2.3.2 Execution Synchronization ......................................................................6-7
6.2.2.3.3 Instruction-Related Exceptions................................................................6-7
6.2.3 Instruction Set Overview..................................................................................6-7
6.2.4 PowerPC UISA Instructions ............................................................................6-8
6.2.4.1 Integer Instructions ......................................................................................6-8
6.2.4.1.1 Integer Arithmetic Instructions ................................................................6-8
6.2.4.1.2 Integer Compare Instructions...................................................................6-9
6.2.4.1.3 Integer Logical Instructions ...................................................................6-10
6.2.4.1.4 Integer Rotate and Shift Instructions .....................................................6-10
6.2.4.2 Load and Store Instructions .......................................................................6-11
6.2.4.2.1 Integer Load and Store Address Generation ..........................................6-11
6.2.4.2.2 Register Indirect Integer Load Instructions ...........................................6-12
6.2.4.2.3 Integer Store Instructions.......................................................................6-13
6.2.4.2.4 Integer Load and Store with Byte-Reverse Instructions ........................6-13
6.2.4.2.5 Integer Load and Store Multiple Instructions ........................................6-14
6.2.4.2.6 Integer Load and Store String Instructions ............................................6-14
6.2.4.3 Branch and Flow Control Instructions .......................................................6-15
6.2.4.3.1 Branch Instruction Address Calculation ................................................6-15
6.2.4.3.2 Branch Instructions ................................................................................6-16
6.2.4.3.3 Condition Register Logical Instructions ................................................6-16
6.2.4.4 Trap Instructions ........................................................................................6-17
6.2.4.5 Processor Control Instructions ...................................................................6-17
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6.2.4.5.1 Move to/from Condition Register Instructions ......................................6-17
6.2.4.6 Memory Synchronization InstructionsÑUISA..........................................6-17
6.2.5 PowerPC VEA Instructions............................................................................6-19
6.2.5.1 Processor Control Instructions ...................................................................6-20
6.2.5.2 Memory Synchronization InstructionsÑVEA...........................................6-20
6.2.5.2.1 eieio Behavior ........................................................................................6-20
6.2.5.2.2 isync Behavior........................................................................................6-21
6.2.5.3 Memory Control InstructionsÑVEA.........................................................6-21
6.2.6 PowerPC OEA Instructions............................................................................6-22
6.2.6.1 System Linkage Instructions ......................................................................6-22
6.2.6.2 Processor Control InstructionsÑOEA .......................................................6-22
6.2.6.2.1 Move to/from Machine State Register Instructions ...............................6-22
6.2.6.2.2 Move to/from Special-Purpose Register Instructions ............................6-23
6.2.6.3 Memory Control InstructionsÑOEA.........................................................6-23
6.2.6.3.1 Supervisor-Level Cache Management Instruction .................................6-23
6.2.6.3.2 Translation Lookaside Buffer Management Instructions.......................6-23
6.2.7 Recommended Simplified Mnemonics ..........................................................6-24
Chapter 7
Exceptions
7.1 Exceptions ............................................................................................................7-2
7.1.1 Exception Ordering ..........................................................................................7-3
7.1.2 PowerPC-Defined Exceptions ..........................................................................7-4
7.1.2.1 System Reset Interrupt (0x00100)................................................................7-5
7.1.2.2 Machine Check Interrupt (0x00200) ............................................................7-5
7.1.2.3 DSI Exception (0x00300).............................................................................7-6
7.1.2.4 ISI Exception (0x00400) ..............................................................................7-6
7.1.2.5 External Interrupt Exception (0x00500).......................................................7-6
7.1.2.6 Alignment Exception (0x00600) ..................................................................7-7
7.1.2.6.1 Integer Alignment Exceptions..................................................................7-8
7.1.2.7 Program Exception (0x00700) .....................................................................7-9
7.1.2.8 Decrementer Exception (0x00900) ............................................................7-10
7.1.2.9 System Call Exception (0x00C00) .............................................................7-10
7.1.2.10 Trace Exception (0x00D00) .......................................................................7-11
7.1.2.11 Floating-Point Assist Exception.................................................................7-12
7.1.3 Implementation-Specific Exceptions..............................................................7-12
7.1.3.1 Software Emulation Exception (0x01000) .................................................7-12
7.1.3.2 Instruction TLB Miss Exception (0x01100) ..............................................7-12
7.1.3.3 Data TLB Miss Exception (0x01200) ........................................................7-13
7.1.3.4 Instruction TLB Error Exception (0x01300)..............................................7-13
7.1.3.5 Data TLB Error Exception (0x014000)......................................................7-14
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7.1.3.6 Debug Exceptions (0x01C00Ð0x01F00)....................................................7-15
7.1.4 Implementing the Precise Exception Model ..................................................7-16
7.1.5 Recoverability after an Exception..................................................................7-17
7.1.6 Exception Latency..........................................................................................7-18
7.1.7 Partially Completed Instructions....................................................................7-19
Chapter 8
Instruction and Data Caches
8.1 Instruction Cache Organization............................................................................8-2
8.2 Data Cache Organization .....................................................................................8-5
8.3 Cache Control Registers.......................................................................................8-6
8.3.1 Instruction Cache Control Registers ................................................................8-6
8.3.1.1 Reading Data and Tags within the Instruction Cache..................................8-8
8.3.1.2 IC_CST Commands .....................................................................................8-9
8.3.1.2.1 Instruction Cache Enable/Disable Commands.........................................8-9
8.3.1.2.2 Instruction Cache Load & Lock Cache Block Command......................8-10
8.3.1.2.3 Instruction Cache Unlock Cache Block Command ...............................8-11
8.3.1.2.4 Instruction Cache Unlock All Command...............................................8-11
8.3.1.2.5 Instruction Cache Invalidate All Command...........................................8-11
8.3.2 Data Cache Control Registers ........................................................................8-11
8.3.2.1 Reading Data Cache Tags and Copyback Buffer.......................................8-14
8.3.2.2 DC_CST Commands..................................................................................8-15
8.3.2.2.1 Data Cache Enable/Disable Commands ................................................8-16
8.3.2.2.2 Data Cache Load & Lock Cache Block Command ...............................8-16
8.3.2.2.3 Data Cache Unlock Cache Block Command .........................................8-17
8.3.2.2.4 Data Cache Unlock All Command ........................................................8-17
8.3.2.2.5 Data Cache Invalidate All Command ....................................................8-17
8.3.2.2.6 Data Cache Flush Cache Block Command............................................8-17
8.4 PowerPC Cache Control Instructions.................................................................8-18
8.4.1 Instruction Cache Block Invalidate (
icbi
) ......................................................8-18
8.4.2 Data Cache Block Touch (
dcbt
) and Data Cache Block Touch
for Store (
dcbtst
) .......................................................................................8-18
8.4.3 Data Cache Block Zero (
dcbz
) ......................................................................8-19
8.4.4 Data Cache Block Store (
dcbst
) ....................................................................8-19
8.4.5 Data Cache Block Flush (
dcbf
)......................................................................8-20
8.4.6 Data Cache Block Invalidate (
dcbi
)...............................................................8-20
8.5 Instruction Cache Operations .............................................................................8-20
8.5.1 Instruction Cache Hit .....................................................................................8-22
8.5.2 Instruction Cache Miss...................................................................................8-22
8.5.3 Instruction Fetching on a Predicted Path .......................................................8-23
8.5.4 Fetching Instructions from Caching-Inhibited Regions.................................8-23
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8.5.5 Updating Code And Memory Region Attributes............................................8-24
8.6 Data Cache Operation.........................................................................................8-24
8.6.1 Data Cache Load Hit ......................................................................................8-25
8.6.2 Data Cache Read Miss....................................................................................8-25
8.6.3 Write-Through Mode......................................................................................8-26
8.6.3.1 Data Cache Store Hit in Write-Through Mode ..........................................8-26
8.6.3.2 Data Cache Store Miss in Write-Through Mode........................................8-26
8.6.4 Write-Back Mode ...........................................................................................8-26
8.6.4.1 Data Cache Store Hit in Write-Back Mode................................................8-26
8.6.4.2 Data Cache Store Miss in Write-Back Mode .............................................8-27
8.6.5 Data Accesses to Caching-Inhibited Memory Regions..................................8-27
8.6.6 Atomic Memory References...........................................................................8-28
8.7 Cache Initialization after Reset...........................................................................8-29
8.8 Debug Support....................................................................................................8-29
8.8.1 Instruction and Data Cache Operation in Debug Mode .................................8-29
8.8.2 Instruction and Data Cache Operation with a Software Monitor Debugger ..8-30
Chapter 9
Memory Management Unit (MMU)
9.1 Features.................................................................................................................9-1
9.2 PowerPC Architecture Compliance......................................................................9-2
9.3 Address Translation..............................................................................................9-3
9.3.1 Translation Disabled.........................................................................................9-3
9.3.2 Translation Enabled..........................................................................................9-3
9.3.3 TLB Operation..................................................................................................9-5
9.4 Using Access Protection Groups ..........................................................................9-6
9.5 Protection Resolution Modes................................................................................9-7
9.6 Memory Attributes ...............................................................................................9-8
9.7 Translation Table Structure ..................................................................................9-9
9.7.1 Level-One Descriptor .....................................................................................9-13
9.7.2 Level-Two Descriptor ....................................................................................9-14
9.8 Programming Model...........................................................................................9-14
9.8.1 IMMU Control Register (MI_CTR)...............................................................9-16
9.8.2 DMMU Control Register (MD_CTR)............................................................9-17
9.8.3 IMMU/DMMU Effective Page Number Register (Mx_EPN) .......................9-18
9.8.4 IMMU Tablewalk Control Register (MI_TWC)............................................9-18
9.8.5 DMMU Tablewalk Control Register (MD_TWC).........................................9-19
9.8.6 IMMU Real Page Number Register (MI_RPN).............................................9-20
9.8.7 DMMU Real Page Number Register (MD_RPN)..........................................9-22
9.8.8 MMU Tablewalk Base Register (M_TWB) ...................................................9-23
9.8.9 MMU Current Address Space ID Register (M_CASID) ...............................9-23
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9.8.10 MMU Access Protection Registers (MI_AP/MD_AP)..................................9-24
9.8.11 MMU Tablewalk Special Register (M_TW) .................................................9-24
9.8.12 MMU Debug Registers ..................................................................................9-25
9.8.12.1 IMMU CAM Entry Read Register (MI_CAM) .........................................9-25
9.8.12.2 IMMU RAM Entry Read Register 0 (MI_RAM0) ....................................9-26
9.8.12.3 IMMU RAM Entry Read Register 1 (MI_RAM1) ....................................9-27
9.8.12.4 DMMU CAM Entry Read Register (MD_CAM) ......................................9-28
9.8.12.5 DMMU RAM Entry Read Register 0 (MD_RAM0) .................................9-29
9.8.13 DMMU RAM Entry Read Register 1 (MD_RAM1) .....................................9-30
9.9 Memory Management Unit Exceptions .............................................................9-32
9.10 TLB Manipulation..............................................................................................9-32
9.10.1 TLB Reload....................................................................................................9-32
9.10.1.1 Translation Reload Examples ....................................................................9-33
9.10.2 Locking TLB Entries......................................................................................9-33
9.10.3 Loading Locked TLB Entries.........................................................................9-34
9.10.4 TLB Invalidation............................................................................................9-34
Chapter 10
Instruction Execution Timing
10.1 Instruction Execution Timing Examples............................................................10-1
10.1.1 Data Cache Load with a Data Dependency....................................................10-1
10.1.2 Writeback Arbitration ....................................................................................10-2
10.1.3 Private Writeback Bus Load ..........................................................................10-3
10.1.4 Fastest External Load (Data Cache Miss)......................................................10-3
10.1.5 A Full Completion Queue ..............................................................................10-4
10.1.6 Branch Instruction Handling ..........................................................................10-4
10.1.7 Branch Prediction...........................................................................................10-5
10.2 Instruction Timing List.......................................................................................10-6
10.2.1 Load/Store Instruction Timing.......................................................................10-7
10.2.2 String Instruction Latency..............................................................................10-8
10.2.3 Accessing Off-Core SPRs ..............................................................................10-8
Chapter 11
System Interface Unit
11.1 Features ..............................................................................................................11-1
11.2 System Configuration and Protection ................................................................11-2
11.3 Multiplexing SIU Pins........................................................................................11-3
11.4 Programming the SIU.........................................................................................11-4
11.4.1 Internal Memory Map Register (IMMR) .......................................................11-4
11.4.2 SIU Module Configuration Register (SIUMCR) ...........................................11-5
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11.4.3 System Protection Control Register (SYPCR) ...............................................11-9
11.4.4 Transfer Error Status Register (TESR).........................................................11-10
11.4.5 Register Lock Mechanism............................................................................11-11
11.5 System Configuration.......................................................................................11-12
11.5.1 Interrupt Structure ........................................................................................11-12
11.5.2 Priority of Interrupt Sources.........................................................................11-14
11.5.3 SIU Interrupt Processing ..............................................................................11-15
11.5.3.1 Nonmaskable InterruptsÑIRQ0 and SWT ..............................................11-15
11.5.4 Programming the SIU Interrupt Controller ..................................................11-16
11.5.4.1 SIU Interrupt Pending Register (SIPEND) ..............................................11-16
11.5.4.2 SIU Interrupt Mask Register (SIMASK)..................................................11-17
11.5.4.3 SIU Interrupt Edge/Level Register (SIEL)...............................................11-18
11.5.4.4 SIU Interrupt Vector Register (SIVEC) ...................................................11-19
11.6 The Bus Monitor...............................................................................................11-20
11.7 The Software Watchdog Timer ........................................................................11-21
11.7.1 Software Service Register (SWSR)..............................................................11-22
11.8 The PowerPC Decrementer ..............................................................................11-23
11.8.1 Decrementer Register (DEC) .......................................................................11-23
11.9 The PowerPC Timebase ...................................................................................11-24
11.9.1 Timebase Register (TBU and TBL) .............................................................11-24
11.9.2 Timebase Reference Registers (TBREFA and TBREFB)............................11-25
11.9.3 Timebase Status and Control Register (TBSCR) .........................................11-26
11.10 The Real-Time Clock .......................................................................................11-27
11.10.1 Real-Time Clock Status and Control Register (RTCSC) .............................11-27
11.10.2 Real-Time Clock Register (RTC).................................................................11-28
11.10.3 Real-Time Clock Alarm Register (RTCAL) ................................................11-29
11.10.4 Real-Time Clock Alarm Seconds Register (RTSEC) ..................................11-29
11.11 The Periodic Interrupt Timer (PIT) ..................................................................11-30
11.11.1 Periodic Interrupt Status and Control Register (PISCR)..............................11-31
11.11.2 PIT Count Register (PITC)...........................................................................11-32
11.11.3 PIT Register (PITR) .....................................................................................11-33
11.12 General SIU Timers Operation.........................................................................11-33
11.12.1 Freeze Operation ..........................................................................................11-33
11.12.2 Low-Power Stop Operation..........................................................................11-34
Chapter 12
Reset
12.1 Types of Reset ....................................................................................................12-1
12.1.1 Power-On Reset..............................................................................................12-2
12.1.2 External Hard Reset........................................................................................12-2
12.1.3 Internal Hard Reset.........................................................................................12-2
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12.1.3.1 PLL Loss of Lock ......................................................................................12-3
12.1.3.2 Software Watchdog Reset..........................................................................12-3
12.1.3.3 Checkstop Reset.........................................................................................12-3
12.1.4 Debug Port Hard or Soft Reset.......................................................................12-3
12.1.5 JTAG Reset ....................................................................................................12-3
12.1.6 Power-On and Hard Reset Sequence .............................................................12-4
12.1.7 External Soft Reset.........................................................................................12-4
12.1.8 Internal Soft Reset..........................................................................................12-4
12.1.9 Soft Reset Sequence.......................................................................................12-5
12.2 Reset Status Register (RSR)...............................................................................12-5
12.3 MPC860 Reset Configuration ............................................................................12-6
12.3.1 Hard Reset......................................................................................................12-6
12.3.1.1 Hard Reset Configuration Word ................................................................12-9
12.3.2 Soft Reset .....................................................................................................12-11
Chapter 13
External Signals
13.1 System Bus Signals ............................................................................................13-5
13.2 Active Pull-Up Buffers.....................................................................................13-21
13.3 Internal Pull-Up and Pull-Down Resistors......................................................13-22
13.4 Recommended Basic Pin Connections.............................................................13-22
13.4.1 Reset Configuration .....................................................................................13-23
13.4.1.1 Bus Control Signals and Interrupts ..........................................................13-23
13.4.2 JTAG and Debug Ports ................................................................................13-23
13.4.3 Unused Inputs...............................................................................................13-24
13.4.4 Unused Outputs............................................................................................13-24
13.5 Signal States during Hardware Reset ...............................................................13-24
Chapter 14
MPC860 External Bus Interface
14.1 Features ..............................................................................................................14-1
14.2 Bus Transfer Overview ......................................................................................14-1
14.3 Bus Interface Signal Descriptions ......................................................................14-2
14.4 Bus Operations ...................................................................................................14-6
14.4.1 Basic Transfer Protocol..................................................................................14-6
14.4.2 Single-Beat Transfer ......................................................................................14-7
14.4.2.1 Single-Beat Read Flow ..............................................................................14-7
14.4.2.2 Single-Beat Write Flow .............................................................................14-9
14.4.3 Burst Transfers .............................................................................................14-13
14.4.4 Burst Operations...........................................................................................14-14
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14.4.5 Alignment and Data Packing on Transfers...................................................14-23
14.4.6 Arbitration Phase ..........................................................................................14-25
14.4.6.1 Bus Request..............................................................................................14-26
14.4.6.2 Bus Grant..................................................................................................14-26
14.4.6.3 Bus Busy...................................................................................................14-27
14.4.6.4 External Bus Parking................................................................................14-29
14.4.7 Address Transfer Phase-Related Signals......................................................14-29
14.4.7.1 Transfer Start............................................................................................14-29
14.4.7.2 Address Bus..............................................................................................14-30
14.4.7.3 Transfer Attributes ...................................................................................14-30
14.4.7.3.1 Read/Write ...........................................................................................14-30
14.4.7.3.2 Burst Indicator......................................................................................14-30
14.4.7.3.3 Transfer Size ........................................................................................14-30
14.4.7.3.4 Address Types ......................................................................................14-30
14.4.7.3.5 Burst Data in Progress (BDIP) .............................................................14-33
14.4.8 Termination Signals......................................................................................14-33
14.4.8.1 Transfer Acknowledge (TA) ....................................................................14-33
14.4.8.2 Burst Inhibit (BI) ......................................................................................14-33
14.4.8.3 Transfer Error Acknowledge (TEA) ........................................................14-33
14.4.8.4 Termination Signals Protocol...................................................................14-33
14.4.9 Memory Reservation ....................................................................................14-34
14.4.9.1 Cancel Reservation (CR)..........................................................................14-35
14.4.9.2 Kill Reservation (KR) ..............................................................................14-36
14.4.10 Bus Exception Control Cycles......................................................................14-37
14.4.10.1 RETRY.....................................................................................................14-38
Chapter 15
Clocks and Power Control
15.1 Features...............................................................................................................15-1
15.2 The Clock Module..............................................................................................15-3
15.2.1 External Reference Clocks .............................................................................15-3
15.2.1.1 Off-Chip Oscillator Input (EXTCLK)........................................................15-4
15.2.1.2 Crystal Oscillator Support (EXTAL and XTAL).......................................15-4
15.2.2 System PLL ....................................................................................................15-5
15.2.2.1 SPLL Reset Configuration .........................................................................15-6
15.2.2.2 SPLL Output Characteristics and Stability ................................................15-7
15.2.2.3 The System Phase-Locked Loop Pins (VDDSYN, VSSSYN,
VSSSYN1, XFC) ...................................................................................15-8
15.2.2.4 Disabling the SPLL ....................................................................................15-9
15.3 Clock Signals......................................................................................................15-9
15.3.1 Clocks Derived from the SPLL Output ..........................................................15-9
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15.3.1.1 The Internal General System Clocks (GCLK1C, GCLK2C,
GCLK1, GCLK2) ................................................................................15-10
15.3.1.2 Memory Controller and External Bus Clocks (GCLK1_50,
GCLK2_50, CLKOUT) .......................................................................15-11
15.3.1.3 CLKOUT Special Considerations: 1:2:1 Mode .......................................15-14
15.3.1.4 The Baud Rate Generator Clock (BRGCLK) ..........................................15-14
15.3.1.5 The Synchronization Clock (SYNCCLK, SYNCCLKS) ........................15-14
15.3.2 The PIT and RTC Clock (PITRTCLK)........................................................15-15
15.3.3 The Time Base and Decrementer Clock (TMBCLK) ..................................15-16
15.4 Power Distribution ...........................................................................................15-16
15.4.1 I/O Buffer Power (VDDH)...........................................................................15-17
15.4.2 Internal Logic Power (VDDL) .....................................................................15-18
15.4.3 Clock Synthesizer Power (VDDSYN, VSSSYN, VSSYN1).......................15-18
15.4.4 Keep-Alive Power (KAPWR)......................................................................15-18
15.5 Power Control (Low-Power Modes) ................................................................15-18
15.5.1 Normal High Mode ......................................................................................15-21
15.5.2 Normal Low Mode.......................................................................................15-21
15.5.3 Doze High Mode ..........................................................................................15-21
15.5.4 Doze Low Mode...........................................................................................15-22
15.5.5 Sleep Mode...................................................................................................15-23
15.5.6 Deep-Sleep Mode.........................................................................................15-23
15.5.7 Power-Down Mode ......................................................................................15-24
15.5.7.1 Software Initiation of Power-Down Mode, with Automatic Wake-up....15-24
15.5.7.2 Maintaining the Real-Time Clock (RTC) During Shutdown or
Power Failure .......................................................................................15-25
15.5.7.3 Register Lock Mechanism: Protecting SIU Registers in
Power-Down Mode..............................................................................15-26
15.5.8 TMIST: Facilitating Nesting of SIU Timer Interrupts.................................15-26
15.6 Clock and Power Control Registers .................................................................15-27
15.6.1 System Clock and Reset Control Register ...................................................15-27
15.6.2 PLL, Low-Power, and Reset Control Register (PLPRCR) ..........................15-29
Chapter 16
Memory Controller
16.1 Features ..............................................................................................................16-1
16.2 Basic Architecture ..............................................................................................16-4
16.3 Chip-Select Programming Common to the GPCM and UPM ...........................16-6
16.3.1 Address Space Programming .........................................................................16-7
16.3.2 Register Programming Order .........................................................................16-7
16.3.3 Memory Bank Write Protection .....................................................................16-7
16.3.4 Address Type Protection ................................................................................16-7
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16.3.5 8-, 16-, and 32Bit Port Size Configuration.....................................................16-7
16.3.6 Parity Configuration .......................................................................................16-8
16.3.7 Memory Bank Protection Status.....................................................................16-8
16.3.8 UPM-Specific Registers .................................................................................16-8
16.3.9 GPCM-Specific Registers ..............................................................................16-8
16.4 Register Descriptions..........................................................................................16-8
16.4.1 Base Registers (BRx) .....................................................................................16-8
16.4.2 Option Registers (ORx)................................................................................16-10
16.4.3 Memory Status Register (MSTAT) ..............................................................16-13
16.4.4 Machine A Mode Register/Machine B Mode Registers (MxMR) ...............16-13
16.4.5 Memory Command Register (MCR)............................................................16-15
16.4.6 Memory Data Register (MDR).....................................................................16-16
16.4.7 Memory Address Register (MAR) ...............................................................16-17
16.4.8 Memory Periodic Timer Prescaler Register (MPTPR) ................................16-17
16.5 General-Purpose Chip-Select Machine (GPCM) .............................................16-18
16.5.1 Timing Configuration...................................................................................16-18
16.5.1.1 Chip-Select Assertion Timing ..................................................................16-19
16.5.1.2 Chip-Select and Write Enable Deassertion Timing .................................16-20
16.5.1.3 Relaxed Timing ........................................................................................16-22
16.5.1.4 Output Enable (OE) Timing .....................................................................16-25
16.5.1.5 Programmable Wait State Configuration .................................................16-25
16.5.1.6 Extended Hold Time on Read Accesses...................................................16-25
16.5.2 Boot Chip-Select Operation .........................................................................16-27
16.5.3 External Asynchronous Master Support.......................................................16-28
16.5.4 Special Case: Bursting with External Transfer Acknowledge: ....................16-29
16.6 User-Programmable Machines (UPMs) ...........................................................16-30
16.6.1 Requests........................................................................................................16-31
16.6.1.1 Internal/External Memory Access Requests ............................................16-31
16.6.1.2 UPM Periodic Timer Requests.................................................................16-32
16.6.1.3 Software RequestsÑMCR run Command ...............................................16-32
16.6.1.4 Exception Requests ..................................................................................16-32
16.6.2 Programming the UPM.................................................................................16-33
16.6.3 Clock Timing................................................................................................16-33
16.6.4 The RAM Array ...........................................................................................16-35
16.6.4.1 RAM Words .............................................................................................16-36
16.6.4.2 Chip-Select Signals (CxTx)......................................................................16-39
16.6.4.3 Byte-Select Signals (BxTx)......................................................................16-39
16.6.4.4 General-Purpose Signals (GxTx, GOx)....................................................16-40
16.6.4.5 Loop Control (LOOP) ..............................................................................16-42
16.6.4.6 Exception Pattern Entry (EXEN) .............................................................16-43
16.6.4.7 Address Multiplexing (AMX) ..................................................................16-43
16.6.4.8 Transfer Acknowledge and Data Sample Control (UTA, DLT3) ............16-47
16.6.4.9 Disable Timer Mechanism (TODT) .........................................................16-48
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16.6.4.10 The Last Word (LAST)............................................................................16-48
16.6.4.11 The Wait Mechanism (WAEN) ...............................................................16-48
16.6.4.11.1 Internal and External Synchronous Masters ........................................16-48
16.6.4.11.2 External Asynchronous Masters ..........................................................16-49
16.7 Handling Devices with Slow or Variable Access Times .................................16-50
16.7.1 Hierarchical Bus Interface Example ............................................................16-51
16.7.2 Slow Devices Example ................................................................................16-51
16.8 External Master Support...................................................................................16-51
16.8.1 Synchronous External Masters.....................................................................16-51
16.8.2 Asynchronous External Masters ..................................................................16-52
16.8.3 Special Case: Address Type Signals for External Masters ..........................16-52
16.8.4 UPM Features Supporting External Masters................................................16-52
16.8.4.1 Address Incrementing for External Synchronous Bursting Masters........16-52
16.8.4.2 Handshake Mechanism for Asynchronous Bursting Masters ..................16-52
16.8.4.3 Special Signal for External Address Multiplexer Control .......................16-53
16.8.5 External Master Examples ...........................................................................16-53
16.8.5.1 External Masters and the GPCM .............................................................16-53
16.8.5.2 External Masters and the UPM ................................................................16-54
16.9 Memory System Interface Examples ...............................................................16-58
16.9.1 Page-Mode DRAM Interface Example........................................................16-59
16.9.2 Page Mode Extended Data-Out Interface Example .....................................16-70
Chapter 17
PCMCIA Interface
17.1 System Configuration.........................................................................................17-1
17.2 PCMCIA Module Signal Definitions.................................................................17-1
17.2.1 PCMCIA Cycle Control Signals ....................................................................17-3
17.2.2 PCMCIA Input Port Signals...........................................................................17-4
17.2.3 PCMCIA Output Port Signals (OP[0Ð4]) ......................................................17-5
17.2.4 Other PCMCIA Signals..................................................................................17-5
17.3 Operation Description ........................................................................................17-5
17.3.1 Memory-Only Cards ......................................................................................17-6
17.3.2 I/O Cards ........................................................................................................17-6
17.3.3 Interrupts ........................................................................................................17-6
17.3.4 Power Control ................................................................................................17-7
17.3.5 Reset and Three-State Control .......................................................................17-7
17.3.6 DMA ..............................................................................................................17-7
17.4 Programming Model ..........................................................................................17-8
17.4.1 PCMCIA Interface Input Pins Register (PIPR) .............................................17-8
17.4.2 PCMCIA Interface Status Changed Register (PSCR) ...................................17-9
17.4.3 PCMCIA Interface Enable Register (PER)..................................................17-10
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17.4.4 PCMCIA Interface General Control Register (PGCRx) ..............................17-12
17.4.5 PCMCIA Base Registers 0Ð7 (PBR0ÐPBR7) ..............................................17-12
17.4.6 PCMCIA Option Register 0Ð7 (POR0ÐPOR7) ............................................17-13
17.5 PCMCIA Controller Timing Examples............................................................17-16
Chapter 18
Communications Processor Module and CPM Timers
18.1 Features...............................................................................................................18-1
18.2 CPM General-Purpose Timers............................................................................18-4
18.2.1 Features...........................................................................................................18-5
18.2.2 CPM Timer Operation....................................................................................18-5
18.2.2.1 Timer Clock Source....................................................................................18-6
18.2.2.2 Timer Reference Count ..............................................................................18-6
18.2.2.3 Timer Capture.............................................................................................18-6
18.2.2.4 Timer Gating ..............................................................................................18-6
18.2.2.5 Cascaded Mode ..........................................................................................18-7
18.2.3 CPM Timer Register Set ................................................................................18-8
18.2.3.1 Timer Global Configuration Register (TGCR) ..........................................18-8
18.2.3.2 Timer Mode Registers (TMR1ÐTMR4) .....................................................18-9
18.2.3.3 Timer Reference Registers (TRR1ÐTRR4)..............................................18-10
18.2.3.4 Timer Capture Registers (TCR1ÐTCR4) .................................................18-10
18.2.3.5 Timer Counter Registers (TCN1ÐTCN4).................................................18-10
18.2.3.6 Timer Event Registers (TER1ÐTER4) .....................................................18-11
18.2.4 Timer Initialization Examples ......................................................................18-12
Chapter 19
Communications Processor
19.1 Features...............................................................................................................19-1
19.2 Communicating with the Core............................................................................19-2
19.3 Communicating with the Peripherals .................................................................19-2
19.4 CP Microcode Revision Number........................................................................19-4
19.5 CP Register Set and CP Commands...................................................................19-4
19.5.1 RISC Controller Configuration Register (RCCR)..........................................19-4
19.5.2 CP Command Register (CPCR) .....................................................................19-6
19.5.3 CP Commands ................................................................................................19-7
19.5.3.1 CP Command Examples.............................................................................19-8
19.5.3.2 CP Command Execution Latency ..............................................................19-9
19.6 Dual-Port RAM ..................................................................................................19-9
19.6.1 System RAM and Microcode Packages .......................................................19-10
19.6.2 The Buffer Descriptor (BD) .........................................................................19-11
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19.6.3 Parameter RAM ...........................................................................................19-11
19.7 The RISC Timer Table.....................................................................................19-12
19.7.1 RISC Timer Table Scan Algorithm..............................................................19-12
19.7.2 The
SET
TIMER
Command ............................................................................19-13
19.7.3 RISC Timer Table Parameter RAM and Timer Table Entries.....................19-13
19.7.3.1 RISC Timer Command Register (TM_CMD) .........................................19-14
19.7.3.2 RISC Timer Table Entries........................................................................19-15
19.7.4 RISC Timer Event Register (RTER)/Mask Register (RTMR) ....................19-15
19.7.5 PWM Mode..................................................................................................19-15
19.7.6 RISC Timer Initialization.............................................................................19-16
19.7.7 RISC Timer Interrupt Handling ...................................................................19-17
19.7.8 Using the RISC Timers to Track CP Loading .............................................19-17
Chapter 20
SDMA Channels and IDMA Emulation
20.1 SDMA Channels ................................................................................................20-1
20.1.1 SDMA Transfers ............................................................................................20-2
20.1.2 U-Bus Arbitration and the SDMA Channels .................................................20-2
20.2 SDMA Registers ............................................................................................... 20-3
20.2.1 SDMA Configuration Register (SDCR) ........................................................20-3
20.2.2 SDMA Status Register (SDSR) .....................................................................20-4
20.2.3 SDMA Mask Register (SDMR) .....................................................................20-5
20.2.4 SDMA Address Register (SDAR) .................................................................20-5
20.3 IDMA Emulation................................................................................................20-5
20.3.1 IDMA Features...............................................................................................20-6
20.3.2 IDMA Parameter RAM..................................................................................20-6
20.3.3 IDMA Registers .............................................................................................20-7
20.3.3.1 DMA Channel Mode Registers (DCMR) ..................................................20-7
20.3.3.2 IDMA Status Registers (IDSR1 and IDSR2).............................................20-8
20.3.3.3 IDMA Mask Registers (IDMR1 and IDMR2)...........................................20-9
20.3.4 IDMA Buffer Descriptors (BD) .....................................................................20-9
20.3.4.1 Function Code RegistersÑSFCR and DFCR ..........................................20-11
20.3.4.2 Auto-Buffering and Buffer-Chaining.......................................................20-12
20.3.5 IDMA CP Commands ..................................................................................20-12
20.3.6 IDMA Channel Operation............................................................................20-12
20.3.6.1 Activating an IDMA Channel ..................................................................20-13
20.3.6.2 Suspending an IDMA Channel ................................................................20-13
20.3.7 IDMA Interface SignalsÑDREQ and SDACK...........................................20-13
20.3.7.1 IDMA Requests for Memory/Memory Transfers ....................................20-13
20.3.7.2 IDMA Requests for Peripheral/Memory Transfers .................................20-14
20.3.7.2.1 Level-Sensitive Requests .....................................................................20-14
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20.3.7.2.2 Edge-Sensitive Requests ......................................................................20-14
20.3.8 IDMA TransfersÑDual-Address and Single-Address.................................20-15
20.3.8.1 Dual-Address (Dual-Cycle) Transfer .......................................................20-15
20.3.8.2 Single-Address (Single-Cycle) Transfer (Fly-By) ...................................20-15
20.3.9 Single-Buffer Mode on IDMA1ÑA Special Case.......................................20-18
20.3.9.1 IDMA1 Channel Mode Register (DCMR) (Single-Buffer Mode)...........20-19
20.3.9.2 IDMA1 Status Register (IDSR1) (Single-Buffer Mode) .........................20-19
20.3.9.3 IDMA1 Mask Register (IDMR1) (Single-Buffer Mode) .........................20-20
20.3.9.4 Burst Timing (Single-Buffer Mode).........................................................20-20
20.3.10 External Recognition of an IDMA Transfer.................................................20-21
20.3.11 Interrupts During an IDMA Bus Transfer ....................................................20-22
Chapter 21
Serial Interface
21.1 SI Features ..........................................................................................................21-3
21.2 The Time-Slot Assigner (TSA) ..........................................................................21-3
21.2.1 TSA Signals....................................................................................................21-7
21.2.2 Enabling Connections to the TSA ..................................................................21-8
21.2.3 SI RAM ..........................................................................................................21-8
21.2.3.1 Disabling and Reenabling the TSA ............................................................21-9
21.2.3.2 One TDM Channel with Static Frames ......................................................21-9
21.2.3.3 Two TDM Channels with Static Frames..................................................21-10
21.2.3.4 SI RAM Dynamic Changes......................................................................21-10
21.2.3.5 One TDM Channel with Dynamic Frames...............................................21-13
21.2.3.6 Two TDM Channels with Dynamic Frames ............................................21-13
21.2.3.7 Programming the SI RAM .......................................................................21-14
21.2.3.8 SI RAM Programming Example ..............................................................21-15
21.2.4 The SI Registers ...........................................................................................21-16
21.2.4.1 SI Global Mode Register (SIGMR)..........................................................21-16
21.2.4.2 SI Mode Register (SIMODE)...................................................................21-17
21.2.4.3 SI Clock Route Register (SICR) ..............................................................21-23
21.2.4.4 SI Command Register (SICMR) ..............................................................21-24
21.2.4.5 SI Status Register (SISTR).......................................................................21-25
21.2.4.6 SI RAM Pointer Register (SIRP) .............................................................21-26
21.2.5 IDL Bus Implementation..............................................................................21-28
21.2.5.1 ISDN Terminal Adaptor Application .......................................................21-28
21.2.5.2 Programming the IDL Interface ...............................................................21-31
21.2.6 GCI Bus Implementation..............................................................................21-32
21.2.6.1 GCI Activation/Deactivation....................................................................21-34
21.2.6.2 Programming the GCI Interface ...............................................................21-34
21.2.6.2.1 Normal Mode .......................................................................................21-34
/