Texas Instruments TLK100 Internal Voltages EVM User guide

Texas Instruments
Brand
Texas Instruments
Model
TLK100 Internal Voltages EVM
Type
User guide
User's Guide
SLLU118–September 2009
TLK100 Internal Voltages EVM
This User Guide details the design and operation of the evaluation module (EVM) for the TLK100.
Contents
1 TLK100INTEVM Purpose and Content .................................................................................. 1
2 Information and Specifications ............................................................................................ 1
2.1 Usage Setup and Configuration .................................................................................. 2
2.2 Address Settings ................................................................................................... 2
2.3 TLK100INTEVM Connections .................................................................................... 2
3 TLK100INTEVM Specification ............................................................................................. 2
3.1 Overview ............................................................................................................ 2
3.2 Required Resources ............................................................................................... 2
3.3 Features ............................................................................................................. 3
3.4 EVM Block Diagram ............................................................................................... 4
3.5 PCB Physical Layout .............................................................................................. 5
4 Software ...................................................................................................................... 5
5 EVM Schematics ............................................................................................................ 5
List of Figures
1 EVM Block Diagram ........................................................................................................ 4
2 EVM Layout.................................................................................................................. 5
List of Tables
1 TLK100INTEVM Connections............................................................................................. 2
1 TLK100INTEVM Purpose and Content
The purpose of TLK100INTEVM is to provide Texas Instruments customers the ability to quickly design
and market systems containing the TLK100 chip. Customers are encouraged to copy EVM components to
expedite their design process.
TLK100INTEVM operates using only a single voltage (5V from the MII). All other voltages are internally
produced.
The EVM kit contains:
• TLK100INTEVM Unit
• Printed copy of this User's Guide
• TLK100INTEVM Schematic
2 Information and Specifications
This section contains specifications of the TLK100INTEVM card, as well as a description of the card's
interfaces, connectors, jumpers and LEDs.
1
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TLK100INTEVM Specification
www.ti.com
2.1 Usage Setup and Configuration
Power for the TLK100INTEVM is supplied via MIl connector.
• If 5V is supplied, the on-board U100 voltage regulator converts the 5V to 3.3V for the device. J100
should be removed.
• If 3.3V is supplied from the MIl connector, J100 needs to be on; R101 should be assembled and R102
should be removed.
2.2 Address Settings
The PMD address for TLK100INTEVM Physical Layer device is set by the following jumpers:
J107: PHY ID [0]
J106: PHY ID [1]
J105: PHY ID [2]
• Default board setting for the PHY Address is 01 h
• The board may be set to PHY Address 00h-07h by adding jumper J105-J107.
2.3 TLK100INTEVM Connections
The following table describes the connections of the TLK100INTEVM:
Table 1. TLK100INTEVM Connections
Jumper Name Function
P100 MII Male Connector MII interface
J100 MII 3V3 option Use 3V3 MII supply
J102 RESET N Reset the device
J108 Central Tap voltage selector Use 3.3V/1.8V central tap voltage
U105 RJ45 RJ45 Ethernet connector
J105-J107(Not populated) PHY ID[0:2] Config PHY ID address
J103 25M out 25M clock output
J101 MDI_EN Disable auto crossover and enable.
3 TLK100INTEVM Specification
3.1 Overview
The TLK100INTEVM is a Texas Instruments platform that allows evaluation of the TLK100 device; and, it
demonstrates the advanced features specified in the TLK100 data sheet. The EVM supports 10/100
Base-T and is compliant with IEEE 802.3 standard.
The TLK100INTEVM works with a single supply (5V or 3.3V) from the MII. All other voltages required for
the TLK100 are internally generated in the device.
The TLK100INTEVM is designed to work in industrial temperatures.
3.2 Required Resources
Any equipment that provides a standard IEEE 802.3, Clause 22 MII DTE interface; e.g. SmartBits/Netcom
box.
2
TLK100 Internal Voltages EVM SLLU118–September 2009
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TLK100INTEVM Specification
3.3 Features
The TLK100INTEVM features:
• Industrial temperatures (–40°C to +85°C )
• Industrial temperature external magnetics.
• Control and status:
– Configurable 8 PHY Addresses – 01h (default) or any other address between 00h-07h using
jumpers as described in Table 1.
– 4 LEDs – 1 power, 3 status (Speed, Link, and Active Data)
• Strap Options:
– MDI_EN jumper (Crossover disable)
– Resistor strapping options:
• Configurable PHY Addresses 08h–31h
• CFG_ANEG_MODE
• CFG_ANAEG_SPD_0,1
• LED_CONFIGURATION
– RESET _N jumper
• Connections for the following interfaces:
– MIl connector
– RJ-45
• Single-sided component placement
• On-board clock – Crystal/Oscillator Dual Footprint
• On-board power supplied by MIl connector only; jumper to configure 5V or 3.3V
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Copyright © 2009, Texas Instruments Incorporated
TLK100
MIIConnector
Leds
LEDLINK
LEDPOWER
LED ACT/COL
JTAG
Reset
3.3 V
Regulator
5 V/3.3VFROMMII
POR
MagneticsPulseHX1188
RJ45
25MCLKOUT
25MHzCrystalorOscilator
LEDSPEED
BootResistors/
Jumpers
BUS MII
TLK100INTEVM Specification
www.ti.com
3.4 EVM Block Diagram
Figure 1. EVM Block Diagram
4
TLK100 Internal Voltages EVM SLLU118–September 2009
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Software
3.5 PCB Physical Layout
• FR4 material
• Trace impedance Differential impedance 100 Ω, ±5%
• Uniform supply and ground plane
• 4 layers
• Combination of through-hole and surface mount technology
Figure 2. EVM Layout
4 Software
The EVM does not require any specific software and can be controlled from networking equipment that
supports MII interface. However for SmartBits users, TI can provide proprietary GUI that simplifies the
controllability of the TLK100INTEVM through SmartBits and allows advanced features such as a cable
diagnostic tool.
5 EVM Schematics
The schematics are appended to the User's Guide.
5
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Copyright © 2009, Texas Instruments Incorporated
EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have
electronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be complete
in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmental
measures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit does
not fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling
(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYER
AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF
MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claims
arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all
appropriate precautions with regard to electrostatic discharge.
EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY
INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or
services described herein.
Please read the User’s Guide and, specifically, the Warnings and Restrictions notice in the User’s Guide prior to handling the product. This
notice contains important safety information about temperatures and voltages. For additional information on TI’s environmental and/or
safety programs, please contact the TI application engineer or visit www.ti.com/esh.
No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, or
combination in which such TI products or services might be or are used.
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES
ONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radio
frequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which are
designed to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments may
cause interference with radio communications, in which case the user at his own expense will be required to take whatever measures may
be required to correct this interference.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the power supply voltage range of 5 V or 3.3 V.
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions
concerning the input range, please contact a TI field representative prior to connecting the input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 60°C. The EVM is designed to operate
properly with certain components above 60°C as long as the input and output ranges are maintained. These components include but are
not limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identified
using the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,
please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2009, Texas Instruments Incorporated
DUT
3.3V
MII_3V3
OFF = MII 5V
TLK100 DUT
POR
CONFIGURATION_PINS_DUT
5V
MII_CONECTOR
ROOM=3_3V_MAIN
LED_ACTIVE_DUT
LED_ACTIVE_DUT
LED_SPEED_DUT
LED_SPEED_DUT
LED_LINK_DUT
LED_LINK_DUT
TX_CLK_DUT
XFMRP_B_DUT
LED_ACTIVE_DUT
3V3_OUT
MII_CRS_DUT
MII_COL_DUT
MDC_DUT
0
IGNORE
IGNORE
IGNORE
17_21SYGC_S530
GREEN
IGNORE
470
IGNORE
IGNORE
GREEN
17_21SYGC_S530
RC0805D
3V3_OUT
RC0805D
17_21SYGC_S530
GREEN
17_21SYGC_S530
GREEN
I58
ROOM=TLK100_DUT
RESET_N_DUT
DUT_TXD<3..0>
RX_ER_DUT
RX_DV_DUT
RX_CLK_DUT
3V3_OUT
I46
I56
XFMRM_A_DUT
MII_CRS_DUT
XFMRM_B_DUT
XFMRP_A_DUT
TX_EN_DUT
TX_CLK_DUT
XFMRP_B_DUT
XFMRP_A_DUT
XFMRM_B_DUT
XFMRM_A_DUT
ROOM=MAG_DUT
ROOM=POR
RESET_N_DUT
RX_DV_DUT
RX_CLK_DUT
DUT_RXD<3..0>
MDIO_DUT
PN0035R
MTLW-103-23-S-S-260
LED_SPEED_DUT
MII_COL_DUT
DUT_RXD<3..0>
MII_CRS_DUT
RX_ER_DUT
RC0805D
RC0805D
I51
470
3V3_OUT
470
MDIO_DUT
MII_COL_DUT
DUT_RXD<3..0>
TX_EN_DUT
470
GREEN
RC0805D
I63
17_21SYGC_S530
GREEN
RC0805D
470
I66
470
ROOM=MII_CONNECTOR
ROOM=CONFIG_PINS_DUT
3V3_OUT
VDDLDOA1P8OUT_DUT
3V3_OUT
3V3_OUT
MDC_DUT
LED_SPEED_DUT
LED_LINK_DUT
LED_ACTIVE_DUT
LED_LINK_DUT
M100
1
M101
1
M103
1
M102
1
J108
1
2
3
J100
2
LD104
2
1
LD102
2
1
LD105
2
1
LD103
2
1
R190
1
2
R191
1
2
LD101
2
1
R187
1
2
LD106
2
1
R193
1
2
R188
1
2
R194
1
2
R1
1
2
11
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DUT_TXD<3..0>
RX_ER_DUT
17_21SYGC_S530
VDDLDOA1P8OUT_DUT
1
TLK100_DEVICE_REV1
3.3V_IN
POR_INPUT
LED_ACT_BID
LED_LINK_BID
LED_SPEED_BID
MDC
MDIO
MII_COL
MII_CRS
MII_RX<3..0>
MII_RX_CLK
MII_RX_DV
MII_RX_ER
MII_TX<3..0>
MII_TX_CLK_OUT
MII_TX_EN
VDDLDOA1P8_OUT
XFMRM_A_BID
XFMRM_B_BID
XFMRP_A_BID
XFMRP_B_BID
CONFIGURATION_PINS_REV1
3.3V_IN
LED_ACTIVE
LED_LINK
LED_SPEED
MII_COL
MII_RX<3..0>
MII_CRS
MII_RX_ERR
OF
OF
PART NO:
COPYRIGHT (C) TI 2006
USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION
TO TEXAS INSTRUMENTS - DSP SYSTEMS ISRAEL
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY
INSTRUMENTS
TEXAS
DRW PAGE:
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ASSY NAME:
EDGE NUMBER:
ENGINEER:
3_3v_ps_ldo_rev1
3_3V_OUT
5V_IN
MII_REV1
5V_OUT
TX_EN
TX_CLK
TXD<3..0>
RX_ER
RX_DV
RX_CLK
RXD<3..0>
MDIO
MDC
CRS
COL
MAGNETICS_REV1
XFMRP_B
XFMRP_A
XFMRM_B
XFMRM_A
1.8V_CT_INPUT
KA
KA
KA
K A
K A
K A
JUMPER
3xjumper
IN3
IN2 IN1
VIA
VIA
VIA
VIA
POR_REV1
RESET_N_DUT
3.3V
POR
RESET
TPS3825-33DBVT
MX0052
RESET_N_DUT
0
3.3V
I10
1NF
I11
1NF
R104
1
2
U101
24
1
3
5
C113
1
2
C108
1
2
J102
2
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1
OF
OF
PART NO:
COPYRIGHT (C) TI 2006
USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION
TO TEXAS INSTRUMENTS - DSP SYSTEMS ISRAEL
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY
INSTRUMENTS
TEXAS
DRW PAGE:
1
IS EXPRESSLY FORBIDDEN.
DATE:
3
REV:
8
F F
8
A
B
C
D
E
4567
1
234567
A
B
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DESIGN PAGE:
ASSY NAME:
EDGE NUMBER:
ENGINEER:
tps3825-33dbvt
RESET_OUT_PIN3
MR_N_IN_PIN4
VDD_PWR_PIN5 RESET_N_OUT_PIN1
GND_PWR_PIN2
IN
JUMPER
OUT
PLACE RESISTORS NEAR TO CHIP
CLOSE TO OUTPUT PIN
25M_OUT
CLOSE TO OUTPUT PIN
GND
0805 FOOTPRINT
1.8V CT
CLOSE TO OUTPUT PIN
0805 FOOTPRINT
CLOSE TO U9 PIN 4
IGNORE
4.7K
VDDLDOA1P8
VSS_OSC
I29
33PF
0
HH2500-18-E-25PPM
OS0035
VDDIO3P3
VDDLDOD1P1
VDDLDOA1P1
2.2K
2.2K
IGNORE
JTAG_TMS
JTAG_TRSTN
JTAG_TDI
0
1
2.2K
2.2K
MII_RX<3..0>
2.2K
IGNORE
IGNORE
IGNORE
IGNORE
JTAG_TDI
I225
1
100PF
I269
1NF
I270
JTAG_TMS
VDDLDOA1P8_OUT
10NF
I256
10UF
100PF
I295
I268
100PF
I306
100PF
I300
1NF
10NF
I297
10NF
I303
10NF
TLK100
0
VDDLDOA1P8
0
I28
I271
I298
0
10UF
1UF
10UF
I309
1NF
1UF
10NF
I307
10NF
1UF
I280
1NF
1NF
3.3V_IN
0 0
3.3V_IN
1M
1
22
0 0
LED_LINK_BID
LED_ACT_BID
XFMRP_A_BID
XFMRM_A_BID
XFMRP_B_BID
XFMRM_B_BID
I301
1NF
100NF
I281
I328
I316
1NF
I317
10NF
I253
100PF
I254
I255
2
CLK25OUT
VDDLDOA1P1
0
0
3.3V_IN
POR_INPUT
OX0040R
JTAG_TRSTN
2
MII_TX_EN
MII_RX_DV
VDDLDOA1P8
IGNORE
JTAG_TMS
2.2K
JTAG_TCK
2.2K
JTAG_TDO
2.2K
JTAG_TDI
IGNORE
2.2K
JTAG_TMS
IGNORE
2.2K
JTAG_TCK
IGNORE
2.2K
JTAG_TDO
IGNORE
2.2K
JTAG_TDI
IGNORE
2.2K
IGNORE
JTAG_TRSTN
2.2K
JTAG_TRSTN
3.3V_IN
LB0037R
MDIO
2.2K
VDDLDOA1P8
JTAG_TDO
MII_COL
MII_TX<3..0>
3.3V_IN
2.2K
3.3V_IN
2
3
IGNORE
2.2K
JTAG_TCK
JTAG_TDO
MTLW-105-23-GD-260
MII_RX_CLK
3
MII_RX_ER
MDC
MII_TXD2
MII_TXD1
MII_TXD3
IGNORE
2.2K
VDDLDOD1P1
LED_SPEED_BID
MII_CRS
3
2.2K
IGNORE
IGNORE
IGNORE
IGNORE
PN0048
33PF
IGNORE
IGNORE
IGNORE
IGNORE
IGNORE
4.99K
4.7K
IGNORE
22
VSS_OSC
MII_TX_CLK_OUT
JTAG_TCK
3.3V_IN
2.2K
IGNORE
I296
4.7K
IGNORE
IGNORE
D37F25.0000NTS
R154
1
2
R164
1
2
C109
1
2
C114
1
2
R138
1
2
R143
1
2
R162
1
2
R147
1
2
R140
1
2
TP30MIL120 TP30MIL100
TP30MIL101
R168
1
2
XTAL100
1
2
R145
1
2
R139
1
2
R159
1
2
C110
1
2
C124
1
2
C129
1
2
C112
1
2
C123
1
2
C125
1
2
C127
1
2
C128
1
2
U102
3
12
44
45
47
46
48
34
36
35
32
33
24
22
23
25
26
27
28
30
31
19
13
14
15
16
18
49
42
43
2
4
1
7
17
29
11
10
41
40
21
20
38
8
5
9
6
39
37
J103
2
C140
1
2
C122
1
2
C130
1
2
C116
1
2
C121
1
2
C120
1
2
C126
1
2
C118
1
2
C115
1
2
C117
1
2
C119
1
2
C134
1
2
C133
1
2
C132
1
2
C135
1
2
R130
1
2
C131
1
2
C111
1
2
P101
6
10
8
4
2
1
3
5
7
9
R136
1
2
R153
1
2
R134
1
2
C139
1
2
R176
1
2
R179
1
2
R182
1
2
R184
1
2
R186
1
2
R178
1
2
R170
1
2
R183
1
2
R185
1
2
R175
1
2
R124
1
2
R132
1
2
R127
1
2
R125
1
2
R128
1
2
R126
1
2
R149
1
2
R157
1
2
R152
1
2
R131
1
2
U103
1
2
34
R141
1
2
11
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1 1 1
1
OF
OF
PART NO:
COPYRIGHT (C) TI 2006
USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION
TO TEXAS INSTRUMENTS - DSP SYSTEMS ISRAEL
THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY
INSTRUMENTS
TEXAS
DRW PAGE:
1
IS EXPRESSLY FORBIDDEN.
DATE:
3
REV:
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F F
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DESIGN PAGE:
ASSY NAME:
EDGE NUMBER:
ENGINEER:
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
VDD_4
OUTPUT_3
GND_2 E_D_1
mtlw-105-23-gd-260
PIN_9
PIN_7
PIN_5
PIN_3
PIN_1
JTAG_TDI_10
JTAG_TDO_8
JTAG_TCK_6
JTAG_TMS_4
JTAG_TRSTN_2
+ + +
JUMPER
TLK100_CHIP
VSSOSC_PWR_P38
POWER PAD_PWR_P49
VDDLDOA1P8OUT_PWR_P40
VDDLDOD1P1OUT_PWR_P20
VDDLDOA1P1OUT_PWR_P10
VDDIO3P3_PWR_P29
VDDIO3P3_PWR_P17
VDDLDOD1P1IN_PWR_P21
VDDLDOA1P8IN_PWR_P41
VDDLDOA1P1IN_PWR_P11
VDDARECL_PWR_P1
VDDARECL_PWR_P7
VDDARECH_PWR_P2
VDDARECH_PWR_P4
PWRDNN_BID_P42
LED_LINK_BID_P36
JTAG_TDO_OUT_P47
CLK25OUT_OUT_P12
MDC_IN_P32
MII_RX_ER_BID_P31
MII_RX_DV_BID_P30
MDIO_BID_P33
MII_RX_D3_BID_P28
MII_RX_D2_BID_P27
MII_RX_D1_BID_P26
MII_RX_D0_BID_P25
MII_COL_BID_P24
MII_RX_CLK_OUT_P23
LED_SPEED_BID_P35
LED_ACT_BID_P34
XFMRM_B_BID_P5
XFMRP_B_BID_P6
XFMRM_A_BID_P8
XFMRP_A_BID_P9
MII_CRS_BID_P22
MII_TX_CLK_BID_P19
MII_TX_EN_BID_P18
MII_TX_D3_IN_P16
MII_TX_D2_IN_P15
MII_TX_D1_IN_P14
MII_TX_D0_IN_P13
BG_REFREXT_IN_P3
RESETN_IN_P43
JTAG_TMS_IIN_P46
JTAG_TDI_IN_P45
JTAG_TCK_IN_P44
XO_OUT_P37
XI_IN_P39
JTAG_TRSTN_IN_P48
XTAL
P1 P2
OUT
OUT
OUT
OUT
OUT
IN
TP30MIL
1
TP30MIL
1
TP30MIL
1
PULLUP RESISTOR
3.3V_PS
10NF
I10
1NF
100PF
I9
I8
3_3V_OUT
100UF
100UF
0
I18
I3
VR0095R
RC0805D
17_21SYGC_S530
GREEN
220NF
TPS75433Q
0
3.3K
IGNORE
5V_IN
3_3V_OUT
402
LD100
2
1
C106
1
2
C104
1
2
C105
1
2
C107
1
2
R103
1
2
C103
1
2
C102
1
2
U100
21
R102
1
2
R101
1
2
R100
1
2
11
6511835
TLK100_INT_EVM
PC0119
2
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17
Wed May 20 17:07:26 2009
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USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION
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THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY
INSTRUMENTS
TEXAS
DRW PAGE:
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IS EXPRESSLY FORBIDDEN.
DATE:
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REV:
8
F F
8
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A
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DESIGN PAGE:
ASSY NAME:
EDGE NUMBER:
ENGINEER:
+
OUT
K A
tps75433q
PWR_PAD_GND
GND/HEATSINK_PWR_PIN1
GND/HEATSINK_PWR_PIN11
GND_PWR_PIN17
GND/HEATSINK_PWR_PIN10
GND/HEATSINK_PWR_PIN20
RESET/PG_OUT_PIN6
EN_IN_PIN5
IN_IN_PIN4
NC_PIN2
NC_PIN12
NC_PIN14
NC_PIN13
NC_PIN18
NC_PIN16
NC_PIN15
NC_PIN19
OUTPUT_OUT_PIN9
OUTPUT_OUT_PIN8
IN_IN_PIN3
FB/SENSE_IN_PIN7
IN
+
LED_CONFIGURATION
CFG_ANEG_MODE
CFG_ANEG_SPD_0
CFG_ANEG_SPD_1
CFG_CROSSOVR
CFG_PHY_ID [3]
CFG_PHY_ID [2]
CFG_PHY_ID [0]
CFG_PHY_ID [1]
CFG_PHY_ID [4]
3
0
2
LED_LINK
LED_SPEED
MII_CRS
IGNORE
2.2K
IGNORE
2.2K
2.2K
1
2.2K
2.2K
MII_COL
2.2K
MII_RX_ERR
MII_RX<3..0>
IGNORE
2.2K
3.3V_IN
IGNORE
2.2K
2.2K
IGNORE
2.2K
IGNORE
LED_ACTIVE
J105
2
J106
2
J107
2
J101
2
R160
1
2
R150
1
2
R146
1
2
R133
1
2
R122
1
2
R172
1
2
R173
1
2
R174
1
2
R171
1
2
R158
1
2
11
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1
1
1
1
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PART NO:
COPYRIGHT (C) TI 2006
USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION
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THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY
INSTRUMENTS
TEXAS
DRW PAGE:
1
IS EXPRESSLY FORBIDDEN.
DATE:
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REV:
8
F F
8
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B
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DESIGN PAGE:
ASSY NAME:
EDGE NUMBER:
ENGINEER:
JUMPER
JUMPER
JUMPER
JUMPER
IN
IN
IN
IN
IN
IN
IN
IN
MII_CONNECTORMALE
RXD<3..0>
TXD<3..0>
0
PN0212
AMP174218-2
5V_OUT
5V_OUT
5V_OUT
5V_OUT
3
2
1
RX_ER
TX_CLK
IGNORE
MC0002R
MDC
47UF
47UF
IGNORE
MC0002R
MC0002R
IGNORE
IGNORE
IGNORE
IGNOREIGNORE IGNORE IGNORE
IGNORE IGNORE IGNORE
IGNORE
MC0002R
IGNORE
MC0002R
CRS
COL
2
1
RX_CLK
TX_EN
RX_DV
3
0
IGNORE
MC0002R
MC0002R
IGNOREIGNORE
MC0002R
MC0002R
MDIO
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
P100
41
42
R111
1
2
R112
1
2
R113
1
2
R114
1
2
R115
1
2
R120
1
2
R121
1
2
R107
1
2
R108
1
2
R109
1
2
R110
1
2
R116
1
2
R117
1
2
R118
1
2
R119
1
2
TP30MIL111
TP30MIL112
TP30MIL113
TP30MIL114
TP30MIL117
TP30MIL116
TP30MIL115
TP30MIL118
C100
1
2
C101
1
2
TP30MIL119
TP30MIL107
TP30MIL102
TP30MIL103
TP30MIL104
TP30MIL105
TP30MIL106
R106
1
2
R105
1
2
TP30MIL109 TP30MIL110
11
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Wed May 20 17:07:33 2009
7
1 1 1 1 111
11111111
1 1
OF
OF
PART NO:
COPYRIGHT (C) TI 2006
USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION
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TEXAS
DRW PAGE:
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DESIGN PAGE:
ASSY NAME:
EDGE NUMBER:
ENGINEER:
TP30MIL
1
TP30MIL
1
TP30MIL
1
TP30MIL
1
TP30MIL
1
TP30MIL
1
TP30MIL
1
TP30MIL
1
TP30MIL
1
OUT
+
+
TP30MIL
1
TP30MIL
1
TP30MIL
1
TP30MIL
1
TP30MIL
1
TP30MIL
1
TP30MIL
1
TP30MIL
1
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
GND_PIN42
GND_PIN41
PIN40
PIN39
PIN38
PIN37
PIN36
PIN35
PIN34
PIN33
PIN32
PIN31
PIN30
PIN29
PIN28
PIN27
PIN26
PIN25
PIN24
PIN23
PIN22
PIN21
PIN20
PIN19
PIN18
PIN17
PIN16
PIN15
PIN14
PIN13
PIN12
PIN11
PIN10
PIN9
PIN8
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
RJ45_RA
MAGNETICS
CHA
CHB
MAGNETICS
I81
1UF
I82
49.9
XFMRP_B
XFMRM_A
XFMRP_A
MECHANICAL
MC0002R
I76
I80
10NF
10NF
I78
I77
10NF
10NF10NF
10NF
I73
I72
I71
10NF
I51
TH
49.9
49.9
1.8V_CT_INPUT
75
75
6116526-1
0
75
75
PN0021R
I61
I60
I62
10NF
10NF
10NF
HMTSW-101-07-TM-S-240
10NF
49.9
0
XFMRM_B
1.8V_CT_INPUT
I84
I83
1UF
I87
1UF
I85
100NF
100NF
I88
100NF
I47
10NF
I86
1UF
100NF
I41
HX1188NL
R177
1
2
R167
1
2
R166
1
2
R169
1
2
R165
1
2
R163
1
2
TP30MIL108
T100
U105
10
9
1
2
3
4
5
6
7
8
R180
1
2
C147
1
2
R181
1
2
R189
1
2
C152
1
2
R192
1
2
C153
1
2
C155
1
2
C150
1
2
C151
1
2
C154
1
2
C156
1
2
C149
1
2
C158
1
2
C157
1
2
C148
1
2
C143
1
2
C145
1
2
C138
1
2
C136
1
2
C144
1
2
C146
1
2
C142
1
2
C141
1
2
11
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Wed May 20 17:07:15 2009
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INSTRUMENTS
TEXAS
DRW PAGE:
1
IS EXPRESSLY FORBIDDEN.
DATE:
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REV:
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8
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DESIGN PAGE:
ASSY NAME:
EDGE NUMBER:
ENGINEER:
IN
GND_PIN10
GND_PIN9
I/0_PIN8
I/0_PIN7
I/0_PIN6
I/0_PIN5
I/0_PIN4
I/0_PIN3
I/0_PIN2
I/0_PIN1
H1102
TX_P16
TX_P15
TX_P14
NC_P13
RX_P8
TX_P3
RX_P10
RX_P11
NC_P12 NC_P5
NC_P4
RX_P7
RX_P6
TX_P2
TX_P1
RX_P9
IN
TP30MIL
1
IN
IN
IN
IN
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Texas Instruments TLK100 Internal Voltages EVM User guide

Texas Instruments
Brand
Texas Instruments
Model
TLK100 Internal Voltages EVM
Type
User guide
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