Texas Instruments DP83867ERGZ EVM User guide

DP83867ERGZ EVM User's Guide

User's Guide

Literature Number: SNLU190

October 2015

Contents

1 Introduction......................................................................................................................... 4

1.1 Purpose.................................................................................................................... 4

1.2 Key Features.............................................................................................................. 4

1.3 Description ................................................................................................................ 4

1.4 Applications ............................................................................................................... 4

1.5 Operation – Quick Setup................................................................................................ 5

2 Board Setup Details ............................................................................................................. 6

2.1 Block Diagram............................................................................................................ 6

2.2 Power Supply Options................................................................................................... 7

2.3 Serial Management and MAC Interfaces ............................................................................. 7

2.4 LED Options .............................................................................................................. 7

2.5 Bootstrap Options/Jumpers............................................................................................. 8

2.6 JTAG Interface ........................................................................................................... 8

2.7 Clock Options............................................................................................................. 8

2.8 Capacitive Coupling...................................................................................................... 9

2.9 Schematics .............................................................................................................. 10

2.10 Layout.................................................................................................................... 15

2.11 Board Assembly ........................................................................................................ 23

2.12 Board Marking (Silk).................................................................................................... 25

2.13 Bill of Materials (BOM)................................................................................................. 27

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User's Guide

SNLU190–October 2015

DP83867ERGZ User's Guide

The DP83867ERGZ RGMII EVM (DP83867ERGZ-R-EVM) supports 1000/100/10 Mb/s and is compliant

with the IEEE 802.3 standard. This reference design supports RGMII interfaces.

The DP83867ERGZ-R-EVM includes three onboard status LEDs, 5V connectors with onboard LDOs, and

is JTAG accessible. The EVM is capable of providing a 125MHz reference clock from an onboard 25MHz

crystal. Serial management interface, MDIO/MDC, is supported and can be used to access PHY registers

for additional features. There are 4-level straps, which allow for system configurations without the need to

directly access PHY registers. External power supplies can be connected to each specified voltage rail for

additional system evaluation. The EVM supports Wake-on-LAN, Start of Frame Detect IEEE 1588 Time

Stamp and configurable I/O voltages.

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Introduction

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1 Introduction

1.1 Purpose

This user guide details the characteristics, operation, and use of the Industrial Ethernet DP83867ERGZ

EVM. The EVM enables Texas Instruments customers to quickly design and market systems using the

DP83867ERGZ . This document also includes schematic diagrams, a printed-circuit board layout, board

assembly, board marking drawings, and a bill of materials.

1.2 Key Features

• 1000BASE-T, 100BASE-TX and 10BASE-T IEEE 802.3 compliant

• RGMII MAC interfaces

• SFD IEEE 1588 Time Stamp

• JTAG interface

• Three status LEDs

• Low Power Modes

– Active Sleep

– Passive Sleep

– IEEE Power Down

– Deep Power Down

• Wake-on-LAN

• Variable I/O voltage range: 1.8V, 2.5V and 3.3V

• 1000BASE-T error free data transfer over 125 meters on CAT5 cable

1.3 Description

The Industrial Ethernet DP83867ERGZ EVM has an RJ45 connector with integrated magnetics, jumper

configurable straps for easy evaluation and can be operated from a single supply (5V DC jack, J10).

Customers are encouraged to use a design similar to the EVM circuit to expedite their product

development. Serial management interface pins allow customers to also access additional features by

directly controlling PHY registers.

1.4 Applications

• Industrial – Factory Automation

• Wireless Communications Infrastructure

– Base Stations

– Small Cell

– Microwave Backhaul

• Wireline Communications

• Test and Measurements

• Network Printers and Servers

• Consumer Electronics

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Introduction

Figure 1. DP83867ERGZ RGMII EVM

1.5 Operation – Quick Setup

• Turn ON the PHY by plugging in a 5V DC source 5V and GND on the EVM. Alternatively, the EVM can

be powered up through USB connector.

• Plug a CAT5, CAT5E or CAT6 cable into the integrated RJ45 connector (J13)

• Connect the far end of the Ethernet cable to a link partner

• Connect a MAC interface to J2 and J3

• LED Indication

– The 5V LED (LD7) will be illuminated if the 5V supply is connected

– Look for the LINK LED to light up on the DP83867ERGZ EVM after the PHY links with a connected

partner.

– If the link partner supports 1000M mode and a 1000M link is established, then the 1000M LINK

LED will light up

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DP83867ERGZ

DUT

5-V

Connector

25-MHz Crystal or Oscillator

LEDs

LED SPEED

LED ACT

LED LINK

JTAG

Boot Resistors/

Jumpers

2.5-V

Regulator

25-MHz CLK OUT

RJ45

BUS RGMII

2.5 V

RESET

&XVWRPHU¶V0$&

RGMII

BUS RGMII

Headers

Sled

1.0-V

LDO

1.0 V

1.8 V

5 V

Strap Pins

Resistors Options

Ext 1.8 V

5 V

Discrete

Magnetic/

Capacitive

coupling

Board Setup Details

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2 Board Setup Details

2.1 Block Diagram

Figure 2. DP83867ERGZ EVM Block Diagram

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Board Setup Details

2.2 Power Supply Options

The DP83867ERGZ EVM power is supplied by a single 5V DC jack. This option uses onboard LDOs to

provide 2.5V and 1.0V voltage rails.

The DP83867ERGZ EVM can be operated from external supplies. Connect external supplies to P2:

• Pin 1 – AUX_IOVDD_EXT

• Pin 3 – VDDIO_EXT

• Pin 5 – VDDA2P5_EXT

• Pin 7 – VDDA1P8_AB and VDDA1P8_CD

• Pin 9 – VDDA_1V0_EXT

Do the following to enable external power operation:

• Remove R71, R74, R81

• Populate R67, R68, R70, R77, R79

2.3 Serial Management and MAC Interfaces

The DP83867ERGZ EVM supports serial management (MDIO/MDC) and RGMII MAC interfaces. Serial

management interface is accessible though J3. MDIO is located at pin 37 and MDC is located at pin 39.

Ground connection between the DP83867ERGZ EVM and serial interface controller is required for proper

operation. DP83867ERGZ supports both clause 22 and clause 45 in the IEEE 802.3 specification.

NOTE: The default PHY_ID is ‘0’. PHY_ID can be changed via strap options found in the datasheet.

MAC interface pins are located on J9 and J8. RGMII/GMII/MII configurations are located in the datasheet

and can be configured by bootstrapping or direct register access through the serial management interface.

Refer to the DP83867ERGZ datasheet (SNLS504) for specific pin requirements for each MAC interface.

2.4 LED Options

DP83867ERGZ supports up to four LEDs, Link/Speed/ACT/MLED indications. The DP83867ERGZ EVM

has three onboard status LEDs that can be controlled by direct register access using the serial

management interface. LED pins can operate as either current sources (when connected to pull-down) or

current sinks (when connected to pull-up).

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Board Setup Details

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2.5 Bootstrap Options/Jumpers

Some DP83867ERGZ configurations are done through bootstrap options. Options can be selected with

resistor population.

The DP83867ERGZ EVM supports the following resistor configurations:

• PHY_ID[4:0]

• SPEED_SEL

• Mirror Enable

• Auto-Negotiation Disable

• RGMII Clock Skew RX[2:0]

• RGMII Clock Skew TX[2:0]

2.6 JTAG Interface

The DP83867ERGZ EVM has JTAG accessible though P1:

• Pin 2 – TRSTN

• Pin 4 – TMS

• Pin 6 – CLK

• Pin 8 – TDO

• Pin 10 – TDI

2.7 Clock Options

The DP83867ERGZ EVM supports three different clock options:

• 25MHz crystal (Default)

• 25MHz oscillator configured by onboard modifications

• External 25MHz reference clock connected to pin 39 on J2 or J12 MCX connector

2.7.1 Default Configuration

The DP83867ERGZ EVM default configuration has a 25MHz crystal. In this mode and external crystal

resonator is connected across pins XO and XI.

The crystal must be 25MHz ±50ppm-tolerance crystal reference.

2.7.2 25MHz Oscillator Configuration

The DP83867ERGZ can also operate with a 25MHz external CMOS-level oscillator source connected to

pin XI only.

Refer to the data sheet (SNLS504) for OSC requirement specifications.

In order to operate with a 25MHz OSC, the following modifications are required:

• U2 OSC should be mounted – Epson SG-210STF 25MHz ±50ppm

• Populate R57 and R59 with 0 Ohm resistors

• Remove R51, R54

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Board Setup Details

2.7.3 External Configuration

External clock can be supplied to the DP83867ERGZ by using pin 39 on J9 or J12 MCX connector.

The external clock must meet the DP83867ERGZ datasheet requirements and to be within 25MHz

±50ppm-tolerance. For external clock configuration, X_O should be left floating.

Refer to the data sheet (SNLS504) for capacitor divider recommendations.

The following changes are required to route an external clock to the DP83867ERGZ for a 1.8V clock

source:

• Populate R57, R58 with 0 Ohm resistors.

• Remove R51, R54.

2.8 Capacitive Coupling

The EVM can be operated in capacitive coupling mode instead of the magnetic coupling mode. The

following changes are required for capacitive coupling.

• Populate C17, C19, C20, C22, C 23, C25, C26, C28, R99-R106.

• Remove R91-R98 & T1.

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VDDIO

Power_Supply

VDDIO_AUX

VDDA2P5

VDDA1P8_AB

VDDA1P8_CD

VDDA1V0

VDDIO

AUX_VDDIO

VDDA2V5

VDDA1V8_AB

VDDA1V8_CD

VDDA1V0

VDDIO

AUX_VDDIO

VDDA2P5

VDDA1P8_AB

VDDA1P8_CD

VDDA1V0

DP83867RGZ_DUT

DM_A

DP_A

DM_B

DP_B

DM_C

DP_C

DM_D

DP_D

LED_0

LED_1

LED_2

CLKOUT

GTX_CLK

INT_PWDN

MDC

MDIO

GPIO_1

RX_D0

RX_D1

RX_D2

RX_D3

RX_CTRL

GPIO_0

RX_CLK

TX_D0

TX_D1

TX_D2

TX_D3

TX_CLK

TX_CTRL

JTAG_CLK

JTAG_TRSTN

JTAG_TDI

JTAG_TDO

JTAG_TMS

Power Supply

DP83867RGZ DUT

Magnetics

MAGNETICS_AFE

ROOM=MAG_DUT

DM_A

DP_A

DM_B

DP_B

DM_C

DP_C

DM_D

DP_D

LED_0

LED_1

LED_2

CLKOUT

GTX_CLK

INT_PWDN

MDC

MDIO

TD_A_N

TD_A_P

TD_B_N

TD_B_P

TD_C_N

TD_C_P

TD_D_N

TD_D_P

GPIO_1

RX_D0

RX_D1

RX_D2

RX_D3

RX_CTRL

GPIO_0

RX_CLK

TX_D0

TX_D1

TX_D2

TX_D3

TX_CLK

TX_CTRL

JTAG_CLK

JTAG_TRSTN

JTAG_TDI

JTAG_TDO

JTAG_TMS

RESET_N

EXT_REF_CLK

GPIO_1

RX_D0

RX_D1

RX_D2

RX_D3

RX_CTRL

GPIO_0

LED_0

LED_1

LED_2

TXD0

TXD1

AUX_IOVDD

RESET_N

EXT_REF_CLK

LED_0

LED_1

LED_2

TX_D0

TX_D1

AUX_IOVDD

DUT CONFIGURATION

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15

17

19

21

23

25

27

29

31

33

35

37

39

16

18

20

22

24

26

28

30

32

34

36

38

40

J2

TSW-120-07-G-D

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15

17

19

21

23

25

27

29

31

33

35

37

39

16

18

20

22

24

26

28

30

32

34

36

38

40

J3

TSW-120-07-G-D

GND GND

GND

GPIO_1

GPIO_0

RX_CTRL

RX_D3

RX_D2

RX_D1

RX_D0

RX_CLK

INT_PWDN

LED_0

LED_1

LED_2

0 R15EXT_RESET_N

EXT_REF_CLK

FID1

DNP

FID2

DNP

FID3

DNP

M1

M2 M3

M4

GND

GND GND

ERTH_GND

0 R2

DNP

0 R1

DNP

MDIOMDC

GTX_CLK

0 R16

0 R18

TX_CTRL

GTX_CLK

TX_D3

TX_D2

TX_D0

TX_D1

MDIO

MDC

0 R17

RESET_N_H

25M_EXT

RX_CTRL

Net Label

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

25 26

27 28

29 30

31 32

33 34

35 36

37 38

39 40

41

42

43

44

J1

QTE-020-01-L-D-A

TX_D3

TX_D1

TX_CTRL

RX_D3

RX_D1

TX_D2

TX_D0

RX_D2

RX_D0

RX_CLK

0

R3

DNP

0 R4

DNP

0 R6

DNP

0 R8

DNP

0 R10

DNP

0 R12

DNP

0

R5

DNP

0 R7

DNP

0 R9

DNP

0 R11

DNP

0 R13

DNP

0 R14

DNP

4700pF

C68

4700pF

C67

4700pF

C66

Board Setup Details

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2.9 Schematics

Figure 3. Schematic (1 of 5)

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750

R69

5V_SUPPLY

GND

5V_SUPPLY

10µF

C33

100pF

C36

GND

OUT

1

FB

2

GND

3

EN

4

NC

5

IN

6

7

U5 TPS73501DRVR

5V_SUPPLY

GND

45.3k

R76

10µF

C50

VDDA2P5_EXT

100pF

C44

100pF

C55

100µF

C41

100µF

C52

GND

VDDA2P5

VDDIO

VDDIO_EXT

AUX_IOVDD_EXT

IN

1

IN

2

PG

3

BIAS

4

EN

5

GND

6

SS

7

FB

8

OUT

9

OUT

10

EP

11

U6

TPS74701DRCR

5V_SUPPLY

10µF

C56

GND

100µF

C62

GND

10.0k

R80

10µF

C57

100pF

C61

GND

VDDA_1V0_EXT

VDDA1V0

VDDA_1V0_DUT

1 2

3 4

5 6

7 8

9 10

P2

TSW-105-07-G-D

GND

VDDA1P8_AB

VDDA1P8_CD

AUX_IOVDD_EXT

VDDIO_EXT

VDDA2P5_EXT

VDDA_1V0_EXT

5V INPUT

EXTERNAL SUPPLIES

GND

1000pF

C49

1

2

Green

LD7

QTLP630C4TR

220µF

C32

1µF

C51

4.7µF

C65

27pF

C64

0.1µF

C58

0.01µF

C53

0.01µF

C42

0.01µF

C34

0.01µF

C59

1000pF

C54

1000pF

C43

1000pF

C60

1µF

C63

0.01µF

C35

0

R70

DNP

0

R79

DNP

0 R67

0 R68

0

R72

0

R82

0

R71

0

R74

0

R77

DNP

0

R81

0

R78

GND

5V

48.7k

R73

1µF

C37

0.1µF

C39

1000pF

C45

100pF

C47

GND

VDDA1P8_EXT

0.1µF

C40

1000pF

C46

100pF

C48

GND

1µF

C38

VDDA1P8_EXTAUX_IOVDD_EXT

4.53k

R85

1.13k

R83

Close to P2

Close to LDO

0

R86

DNP

AUX_IOVDD

VBUS

1

D-

2

D+

3

GND

4

5

7

6

8

9

10

11

J14

5V_SUPPLY

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Board Setup Details

Figure 4. Schematic (2 of 5)

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1.00MR66

DNP

1.00MR65

DNP

4700pFC30

DNP

4700pFC31

DNP

ERTH_GND GND

2

3

4

1

5

6

7

8

9

10

11

12

J13

1-406541-1

TCT1

1

TD1+

2

TD1-

3

TCT2

4

TD2+

5

TD2-

6

TCT3

7

TD3+

8

TD3-

9

TCT4

10

TD4+

11

TD4-

12

MX4-

13

MX4+

14

MCT4

15

MX3-

16

MX3+

17

MCT3

18

MX2-

19

MX2+

20

MCT2

21

MX1-

22

MX1+

23

MCT1

24

T1

HX5008NL

TD_4_N

TD_4_P

TD_3_N

TD_3_P

TD_2_N

TD_2_P

TD_1_N

TD_1_P

TD_4CAP_N

TD_4CAP_P

TD_3CAP_N

TD_3CAP_P

TD_2CAP_N

TD_2CAP_P

TD_1CAP_N

TD_1CAP_P

TP_CH4_N

TP_CH4_P

TP_CH3_N

TP_CH3_P

TP_CH2_N

TP_CH2_P

TP_CH1_N

TP_CH1_P

TP_CH4_N

TP_CH4_P

TP_CH3_N

TP_CH3_P

TP_CH2_N

TP_CH2_P

TP_CH1_N

TP_CH1_P

D1+

1

D1-

2

NC

6

NC

7

NC

9

NC

10

D2+

4

D2-

5

GND

3

GND

8

U3

TPD4E05U06DQAR

D1+

1

D1-

2

NC

6

NC

7

NC

9

NC

10

D2+

4

D2-

5

GND

3

GND

8

U4

TPD4E05U06DQAR

ERTH_GND

GND

TD_1_N

TD_1_P

TD_2_N

TD_2_P

TD_4_N

TD_4_P

TD_3_N

TD_3_P

75.0

R63

75.0

R64

75.0

R62

75.0

R61

0.01µF

C29

ERTH_GND

0.1µF

C24

0.1µF

C18

0.1µF

C27

0.1µF

C21

GND

0

R87

DNP

0

R89

DNP

0

R88

DNP

0

R90

DNP

0.033µF

C19

DNP

0.033µF

C17

DNP

0.033µF

C20

DNP

0.033µF

C22

DNP

0.033µF

C23

DNP

0.033µF

C25

DNP

0.033µF

C26

DNP

0.033µF

C28

DNP

Board Setup Details

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Figure 5. Schematic (3 of 5)

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GND

CLKOUT

XO

XI

INT_PWDN

MDIO

MDC

LED_2

LED_1

LED_0

JTAG_TMS

JTAG_CLK

JTAG_TDO

JTAG_TDI

RBIAS

TD_D_N

TD_D_P

TD_C_N

TD_C_P

TD_B_N

TD_B_P

TD_A_N

TD_A_P

VDDA1P8_AB

VDDA1P8_CD

VDDA1V0

VDDIO

VDDA2P5

GTX_CLK

TX_CTRL

TX_D0

TX_D1

TX_D2

TX_D3

RX_CTRL

GPIO_0

RX_CLK

RX_D0

RX_D1

RX_D3

GPIO_1

GND

VDDIO VDDA2P5

GND

VDDA1V0

GND

JTAG_TMS

JTAG_CLK

JTAG_TDO_OUT

JTAG_TDI

AUX_IOVDD

100pF

C14

GND

4.7k

R46

CLOSE TO CHIP

25M_REF

1

2

25MHz

XTAL1

ABM3-25.000MHZ-D2W-T

GND

XO

XI

EXT_REF_CLK 25M_REF

CLOSE TO CHIP

0.01µF

C6

GND

RESET_N

2.2k

R43

GND

RESET_N

2.2kR47

2.2k

R48

2.2kR52

2.2kR53

2.2kR56

AUX_IOVDD

MDIO

INT_PWDN

JTAG_TMS

JTAG_CLK

JTAG_TDO

JTAG_TDI

1000pF

C13

1000pF

C10

1000pF

C11

1000pF

C3

1000pF

C5

VDD

4

STANDBY

1

GND

2

OUT

3

25 MHz

U2

SG-210STF25.000000MHZY

0.01µF

C12

1.00M

R55

0 R50

0

R57

0 R49

DNP

0 R59

DNP

0 R51

0 R54

GND

TP1

CLK_OUT

18

COL/GPIO_1

40

PAD

49

GTX_CLK

29

INT/PWDN

44

JTAG_CLK

20

JTAG_TDI

23

JTAG_TDO

21

JTAG_TMS

22

LED_0

47

LED_1

46

LED_2

45

MDC

16

MDIO

17

RBIAS

12

RX_CLK

32

RX_D0/SGMII_COP

33

RX_D1/SGMII_CON

34

RX_D2/SGMII_SOP

35

RX_D3/SGMII_SON

36

RX_DV/RX_CTRL

38

RX_ER/GPIO_0

39

RESET

43

TD_M_A

2

TD_M_B

5

TD_M_C

8

TD_M_D

11

TD_P_A

1

TD_P_B

4

TD_P_C

7

TD_P_D

10

TX_D0/SGMII_SIN

28

TX_D1/SGMII_SIP

27

TX_D2

26

TX_D3

25

TX_EN/TX_CTRL

37

VDD1P0

31

VDD1P0

42

VDD1P0

24

VDD1P0

6

VDDA1P8

48

VDDA1P8

13

VDDA2P5

9

VDDA2P5

3

VDDIO

41

VDDIO

19

VDDIO

30

XI

15

XO

14

U1

DP83867RGZR

VDDA1V0

11.0k

R45

CLOSE TO CHIP

1

2

3

4

S1

4-1437565-1

1µF

C1

1µF

C4

1µF

C8

27pF

C15

27pF

C16

1

2

J10

HTSW-102-07-G-S

1

2

J8

HTSW-102-07-G-S

1

2

J7

HTSW-102-07-G-S

1

2

J9

HTSW-102-07-G-S

1

2

3

4

5

J11

MCX–J–P–H–ST–SM1

GND

1

2

3

4

5

J12

MCX–J–P–H–ST–SM1

GND

0.1µF

C2

0.1µF

C9

PLACE CLOSE TO CHIP

0

R44

EXT_RESET_N

GND

100

R42

22

R41

JTAG_TDO_OUT

0 R58

DNP

GND

Keep capacitor close to device pin

1 2

3 4

5 6

7 8

P1

Place trace on inner layers

keep R59 close to IC

RX_D2

0

R91

0

R92

0

R93

0

R94

0

R95

0

R96

0

R97

0

R98

TD_1_P

TD_1_N

TD_2_P

TD_2_N

TD_3_P

TD_3_N

TD_4_P

TD_4_N

0

R99

0

R100

goes to transformer

0

R101

0

R102

0

R103

0

R104

0

R105

0

R106

TD_1CAP_P

TD_1CAP_N

TD_2CAP_P

TD_2CAP_N

TD_3CAP_P

TD_3CAP_N

TD_4CAP_P

TD_4CAP_N

AUX_IOVDD

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Board Setup Details

Figure 6. Schematic (4 of 5)

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1

2

3

J4

470

R19

470

R24

GND

MIRROR_EN

1

2

3

J5

11.0k

R30

470

R28

470

R34

GND

1

2

3

J6

11.0k

R38

470

R37

470

R40

GND

AUX_IOVDD

2.49k

R23

DNP

6.04k

R21

DNP

AUX_IOVDD

GND

GPIO_1

GPIO_0

RX_CTRL

LED STRAP PINS

CONFIGURATION PINS

RGMII_CLK_SKEW_TX[2] / SPEED_SEL

RGMII_CLK_SKEW_TX[0] /

RGMII_CLK_SKEW_TX[1]

ANEG_DIS / EEE_DIS

RGMII_CLK_SKEW_RX[0]

RGMII_CLK_SKEW_RX[1] / RGMII_CLK_SKEW_RX[2]

1 2

Green

LD2

QTLP630C4TR

12

Green

LD1

QTLP630C4TR

12

Green

LD3

QTLP630C4TR

1 2

Green

LD4

QTLP630C4TR

12

Green

LD5

QTLP630C4TR

1 2

Green

LD6

QTLP630C4TR

PHY_ADD[0] / PHY_ADD[1]

PHY_ADD[2] / PHY_ADD[3]

0

R31

DNP

0

R33

DNP

0

R36

DNP

0

R35

DNP

GND

RX_D0

RX_D2

2.49k

R22

2.49k

R32

2.49k

R39

LED_0

LED_1

6.04k

R20

LED 0

LED_2

LED 1

LED 2

0

R26

DNP

0

R29

DNP

0

R25

DNP

0

R27

DNP

GND

Connect pins 1 and 2 for Modes1, 2 and 3

Connect pins 2 and 3 for Mode 4

Resistor Values must be changed to change Modes, refer to datasheet for proper values

SH-J4

SH-J5

SH-J6

Assembly Note

ZZ1

Place SH-J4 on pins 1 and 2

Assembly Note

ZZ2

Place SH-J5 on pins 1 and 2

Assembly Note

ZZ3

Place SH-J6 on pins 1 and 2

Board Setup Details

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Figure 7. Schematic (5 of 5)

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Board Setup Details

2.10 Layout

Figure 8. Top Solder

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Board Setup Details

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Figure 9. Top Layer

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Board Setup Details

Figure 10. Signal Layer 1

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Board Setup Details

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Figure 11. Signal Layer 2

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Board Setup Details

Figure 12. Signal Layer 3

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Board Setup Details

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Figure 13. Signal Layer 4

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Texas Instruments DP83867ERGZ EVM User guide

Texas Instruments DP83867ERGZ EVM User guide

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