Intel LXD972M User manual

Intel
Brand
Intel
Model
LXD972M
Category
Network transceiver modules
Type
User manual

Intel LXD972M is a single-port 10/100 Mbps PHY transceiver that supports 3.3V operation and has an optional 2.5V I/O voltage. It consumes only 300 mW of power, has low power consumption, and features LED indicators for major functions. With its configurable settings and JTAG boundary scan port, this device is suitable for various applications.

Intel LXD972M is a single-port 10/100 Mbps PHY transceiver that supports 3.3V operation and has an optional 2.5V I/O voltage. It consumes only 300 mW of power, has low power consumption, and features LED indicators for major functions. With its configurable settings and JTAG boundary scan port, this device is suitable for various applications.

Intel
®
LXD972M Transceiver
Demo Board (Board Rev A1)
Preliminary User’s Guide
October 2004
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
2 Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL
®
PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN
INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS
ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT.
Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel
®
LXD972M Transceiver Demo Board (Board Rev A1) may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2004, Intel Corporation.
Preliminary User’s Guide 3
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Contents
Contents
1.0 Introduction......................................................................................................................................5
1.1 About this Demo Board Kit ...................................................................................................5
1.2 Related Documents..............................................................................................................5
1.3 Features of Intel
®
LXD972M Demo Board............................................................................6
2.0 Using the Intel
®
LXD972M Demo Board .........................................................................................7
2.1 Equipment Requirements .....................................................................................................7
2.2 Typical Test Setup................................................................................................................8
2.3 Quick-Start Checklists ..........................................................................................................9
2.4 Configurations.....................................................................................................................11
2.4.1 Optional Test Setup, Using Two Intel
®
LXD972M Demo Boards ..........................11
2.4.2 Power Supply Voltage Source and Clock Options.................................................12
2.4.3 MDIO Configuration Options..................................................................................13
2.4.4 LED Configuration Options....................................................................................13
2.4.5 CFG Pin Configuration Options .............................................................................14
2.5 JTAG Test Signals..............................................................................................................14
3.0 Intel
®
LXD972M Demo Board Schematics....................................................................................15
4.0 Bill of Materials ..............................................................................................................................20
Figures
1 Typical Test Setup .......................................................................................................................8
2Intel
®
LXD972M Transceiver Demo Board ................................................................................10
3 Optional Test Setup ...................................................................................................................11
4 Schematic: Intel
®
LXD972M Transceiver Demo Board Power Control ......................................16
5 Schematic: Intel
®
LXD972M Transceiver Demo Board MII Port.................................................17
6 Schematic: Intel
®
LXD972M Transceiver Demo Board Twisted-Pair Port..................................18
7 Schematic: Intel
®
LXD972M Transceiver Demo Board Configuration........................................19
Tables
1 Related Documents......................................................................................................................5
2 Quick-Start Checklist for Jumper Settings....................................................................................9
3 Quick-Start Checklist for Switch Settings .....................................................................................9
4 Power Supply Voltage Source Connector Options.....................................................................12
5 Magnetic Center-Tap Voltage Source Configuration Options.....................................................12
6 Analog Power Supply (VCCA) Configuration Options................................................................12
7 Clock Configuration Options.......................................................................................................13
8 MDIO Configuration Options.......................................................................................................13
9 Jumper Configuration Settings for LED/CFG Pins......................................................................14
10 JTAG Test Signal Descriptions...................................................................................................14
11 Bill of Materials ...........................................................................................................................20
Contents
4 Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Revision History
Revision Number 002
Revision Date: October 2004
Page Description
5 Section 1.1, “About this Demo Board Kit”. Text added.
6 Section 1.3, “Features of Intel
®
LXD972M Demo Board”. Text changed.
7 Section 2.1, “Equipment Requirements”. Text changed.
9
Section 2.3, “Quick-Start Checklists”. Text changed.
Text changed in Table 2 “Quick-Start Checklist for Jumper Settings”.
Text changed in Table 3 “Quick-Start Checklist for Switch Settings”.
Figure 2 “Intel
®
LXD972M Transceiver Demo Board” changed.
12
Section 2.4.2, “Power Supply Voltage Source and Clock Options”.
Text changed in Table 4 “Power Supply Voltage Source Connector Options” changed.
13
Section 2.4.3, “MDIO Configuration Options”. Text changed.
Text changed in Table 4 “Power Supply Voltage Source Connector Options” changed.
13 Section 2.4.4, “LED Configuration Options”. Text changed.
14 Section 2.4.5, “CFG Pin Configuration Options”. Text changed and new table added.
15 Section 3.0, “Intel
®
LXD972M Demo Board Schematics”. Schematics changed.
20 Section 4.0, “Bill of Materials”. Text in Table 11 “Bill of Materials” changed.
Revision Number 001
Revision Date: July 2004
Page Description
Initial release.
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
Preliminary User’s Guide 5
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
1.0 Introduction
This document describes the typical hardware set-up procedures for the Intel
®
LXD972M
Transceiver Demo Board (called hereafter the LXD972M Demo Board). The LXD972M Demo
Board is a platform for evaluation of the Intel LXT972M Single-Port 10/100 Mbps PHY
Transceiver (called hereafter the LXT972M Transceiver).
The LXD972M Demo Board allows system designers to test the following:
• 10 Mbps and 100 Mbps link performance
• Auto-negotiation
• Register functionality
The LXD972M Demo Board requires only a single 3.3V power supply.
1.1 About this Demo Board Kit
This Demo Board kit includes the following:
• LXD972M Demo Board
• Intel
®
LXD972M Transceiver Demo Board (Board Rev A1) User’s Guide
1.2 Related Documents
Table 1 lists related documentation.
Table 1. Related Documents
Document Document Number
Intel
®
LXT972M Single-Port 10/100 Mbps PHY Transceiver Datasheet 302875
Intel® LXT971A, LXT972A, LXT972M Single-Port 10/100 Mbps PHY Transceivers
Specification Update
249354
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
6 Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
1.3 Features of Intel
®
LXD972M Demo Board
• 3.3V operation, with option for 2.5V I/O voltage
• Low power consumption (300 mW typical)
• Quick setup and clear visibility of application settings for complete system demonstration
• Auto-negotiation protocol compliant. Compatible with systems not supporting auto-
negotiation.
• LED indicators for major functions
• JTAG boundary scan port
• Configurable through MDIO port or hardware jumpers
• Standard half-duplex or full-duplex operation at 10 Mbps or 100 Mbps
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
Preliminary User’s Guide 7
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
2.0 Using the Intel
®
LXD972M Demo Board
This document includes information on the following items concerning using the LXD972M Demo
Board:
• Section 2.1, “Equipment Requirements” on page 7
• Section 2.2, “Typical Test Setup” on page 8
• Section 2.3, “Quick-Start Checklists” on page 9
• Section 2.4, “Configurations” on page 11
• Section 2.5, “JTAG Test Signals” on page 14
• Chapter 3.0, “Intel
®
LXD972M Demo Board Schematics”
• Chapter 4.0, “Bill of Materials”
2.1 Equipment Requirements
The LXD972M Demo Board is populated with all components needed for twisted-pair evaluation.
However, the following additional equipment is also required:
• SmartBits Advanced Multi-port Performance Test Box configured with firmware version 4.39
or newer
• PC with Smart Windows (version 6.0 or newer) installed
• One MII Cable (male to male)
• One external NIC card
• One Category 5 Unshielded Twisted-Pair (UTP) crossover cable
• External power supply
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
8 Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
2.2 Typical Test Setup
Figure 1 shows a typical test setup for standard operation of the LXD972M Demo Board.
The LXD972M Demo Board plugs into a SmartBits Advanced Performance Test Box through a
standard 40-pin MII cable (not included with the LXD972M Demo Board). The LXD972M Demo
Board RJ-45 jack connects to the RJ-45 card in the SmartBits test box through a Twisted-Pair
cable. Operation can be set for evaluation of 10 Mbps, 100 Mbps, and auto-negotiation capabilities.
Figure 1. Typical Test Setup
RS-232
Twisted Pair
Crossover
Cable
SmartBits
Advanced Multi-port
Performance
Tester
MII
Cards
Computer with
Smart Windows
MII Cables
MII
Connectors
LXT972M
LXD972M
RJ-45 Card
or
External NIC Cards
B3570-03
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
Preliminary User’s Guide 9
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
2.3 Quick-Start Checklists
Use the quick-start checklists in this section to set up the LXD972M Demo Board, shown in Figure
2, “Intel
®
LXD972M Transceiver Demo Board” on page 10.
The following quick-start setup procedure sets all ports to the default condition, which includes
Auto-Negotiation enabled, advertising dual-speed, and full-duplex/half-duplex capabilities.
1. Set the jumpers as listed in Table 2.
The following jumpers are defined as follows: LED1 has the functionality of LED/CFG1,
LED2 has the functionality of LED/CFG2, and CFG has the functionality of LED/CFG3 as
defined by the LXT972M Transceiver datasheet.
2. Set SW1 switches as listed in Table 3.
3. Connect the MII port of the LXD972M Demo Board to the Smartbits test box through the MII
connector/cable. A male-to-male cable is required to interface the Smartbits test box to the
LXD972M Demo Board and is available from Newark* (.5m cable - Newark 91F9746).
4. Connect the twisted-pair port through a Twisted-Pair crossover cable to the RJ-45 card in the
SmartBits test box.
5. Power up the Smartbits test box.
6. When the LXD972M Demo Board is configured according to desired test settings, apply the
desired power connections per Table 4 options in Section 2.4.2, “Power Supply Voltage Source
and Clock Options” on page 12 and press Reset switch S2.
7. Proceed with testing.
Table 2. Quick-Start Checklist for Jumper Settings
Jumper Label Setting Configuration
JP1,
JP2,
JP3
LED1,
LED2,
CFG
Pins 1, 2 Jumper
"Sets Port Configuration to 111 for Auto-Negotiation,
10/100 Mbps, Full-Duplex. For details, see Section
2.4.5, “CFG Pin Configuration Options” on page 14.
JP12 VCCA Jumpered
Routes power from VCCD connector (BN4) through
JP12 to the VCCA input.
JP16 MDIO Pins 2, 3 Jumper Routes MDIO through MII 40-pin Connector P1.
JP17 MDC Pins 2, 3 Jumper Routes MDC through MII 40-pin Connector P1.
JP18 Clock Select
Pins 1, 2 Open Disables output of clock oscillator Y2.
Pins 3, 4
Pins 5, 6
Jumper
Jumper
Connects crystal across XI and XO to enable Y1.
JP19 Reset Pins 1,2 Jumper Connects reset button
Table 3. Quick-Start Checklist for Switch Settings
Switch / Label Setting Configuration
SW1-1 / ID EN Off Not applicable for LXT972M Transceiver.
SW1-2 / ADDR0 Off Sets ADDR0 = 0 (“Off” position)
SW1-3 / ADDR1 Off Sets ADDR1 = 0 (“Off” position)
SW1-4 / LINKHOLD / RBIAS Off Not applicable for LXT972M Transceiver.
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
10 Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Note: In Figure 2, the format of the Board ID on the LXD972M Transceiver Demo Board can be either
one of the following:
• For leaded: LXD972M Rev.A1
• For lead-free: LXD972MLF Rev.A1
In Figure 2, the format of the Serial Number on the LXD972M Transceiver Demo Board can be
either one of the following:
• For leaded: 972M-xxxx-A1
• For lead-free: 972MLF-xxxx-A1
Figure 2. Intel
®
LXD972M Transceiver Demo Board
SERIAL #
BOARD ID
B3798-001
SILKSCREEN TOP
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
Preliminary User’s Guide 11
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
2.4 Configurations
2.4.1 Optional Test Setup, Using Two Intel
®
LXD972M Demo Boards
Figure 3 shows an optional test setup using two LXD972M Demo Boards. Each Demo Board plugs
into a SmartBits Advanced Performance Test Box through standard 40-pin MII cables. The two
LXD972M Demo Boards are linked through a Twisted-Pair crossover cable connected to the RJ-45
jack on each board. Operation can be set for evaluation of 10 Mbps, 100 Mbps, and auto-
negotiation capabilities.
Figure 3. Optional Test Setup
RS-232
Twisted-Pair
Crossover
Cable
SmartBits
Advanced Multi-port
Performance
Tester
MII
Cards
Computer with
Smart Windows
MII Cable
RJ-45
MII
Connector
LXT972M
LXD972M
RJ-45
MII
Connector
LXT972M
LXD972M
B3572-05
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
12 Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
2.4.2 Power Supply Voltage Source and Clock Options
Table 4 lists banana lead power connectors (BNn) for the LXD972M Demo Board. For details on
the power supplies, see the schematic in Chapter 3.0, “Intel
®
LXD972M Demo Board
Schematics”.
Table 5 lists internal and external jumper settings to configure the power supply source for the
transmit magnetic center-tap voltage.
Table 6 lists the LXT972M Demo Board analog power supply (VCCA) configuration options.
Table 4. Power Supply Voltage Source Connector Options
Reference
Designators
Signal Supply Description
BN1 VCC
+3.3V.
For components on the LXD972M Demo Board other than LXT972M Transceiver.
BN2 GND Ground
BN3 VCCIO
+3.3V or +2.5V.
I/O voltage for the LXT972M Transceiver.
BN4 VCCD
+3.3V.
LXT972M digital power. If JP12 jumper is on, analog power is provided for the
LXT972M Transceiver.
Table 5. Magnetic Center-Tap Voltage Source Configuration Options
Desired
Power Supply Source
Setting Description
3.3V Power Supply from
VCCA
J um p er
JP4
Use Jumper JP4 to apply 3.3V power from VCCA for center-tap
operation.
Alternate Power Supply
Op en
JP4
Use Jumper JP4 to supply either 2.5V or 3.3V power supply for
center-tap operation. Connect the power supply to pin 2 of JP4.
Table 6. Analog Power Supply (VCCA) Configuration Options
Desired
Configuration
Setting Description
Analog
3.3V Power
Supply to VCCA
Jumper
JP12
Use Jumper JP12 to route power from the VCCD Power Connector
(BN4) through JP12 to the VCCA input of the LXT972M Transceiver.
External Power
Supply to VCCA
Open
JP12
1. Remove jumper from JP12 to disable for VCCA input.
2. Apply external power from an alternate power supply through
pin 2 of JP12. For power supply requirements, see the LXT972M
Transceiver datasheet.
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
Preliminary User’s Guide 13
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Table 7 lists clock configuration options.
2.4.3 MDIO Configuration Options
The default configuration of the MDIO and MDC signals is to route the MDIO through the MII
connector to the SmartBits Test Box by installing jumpers JP16 and JP17.
Note: The RJ-11 feature is not supported. As a result, do not jumper the MDIO and MDC signals to the
RJ-11 connector.
Table 8 lists the desired MDIO configuration settings.
2.4.4 LED Configuration Options
The LXD972M Demo Board provides three programmable LEDs. Each LED can display one of
several available status conditions as selected by the LED Configuration Register (Address 20).
Programmable LEDs (LED/CFG1, LED/CFG2, LED/CFG3) are set in default mode and are
programmable with the MDIO pin. Register address 20 also provides optional LED pulse
stretching up to 100 ms. Register bits 20.3:2 select one of three possible stretch times. (For details,
see the LXT972M Transceiver datasheet.)
Note: The active LED state is determined by the CFG pin function. When the LED/CFG pin is pulled
High, the LED becomes active Low. When the LED/CFG pin is pulled Low, the LED becomes
active High.
Table 7. Clock Configuration Options
Desired
Configuration
JP18 Settings Description
Enable Crystal
Oscillator Y1
Pins 1
1
, 2 Open
Remove jumper from pins 1 and 2 to disable the clock oscillator Y2
output.
Pins 3, 4
Jumper
Place a jumper on pins 3 and 4 and pins 5 and 6, which connects a
crystal across XI and XO to enable Y1.
Pins 5, 6
Enable Clock
Oscillator Y2
Pins 1, 2 Jumper
Place a jumper on pins 1 and 2, which enables the output of clock
oscillator Y2.
Pins 3, 4
Open
Remove jumper from pins 3 and 4, and remove jumper from pins 5
and 6, which disables a crystal connection across XI and XO to Y1.
Pins 5, 6
1. Pin 1 is located on the lower-right corner of JP18.
Table 8. MDIO Configuration Options
Desired Configuration Jumper Setting Description
Route MDIO and MDC
through MII
JP16 Jumper Pins 2, 3 Routes MDIO through 40-pin MII Connector P1
JP17 Jumper Pins 2, 3 Routes MDC through 40-pin MII Connector P1
Route MDIO and MDC
through RJ-11
JP16 Jumper Pins 1, 2 Routes MDIO through RJ-11 Connector J2
JP17 Jumper Pins 1, 2 Routes MDC through RJ-11 Connector J2
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
14 Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
2.4.5 CFG Pin Configuration Options
Three control jumpers pull the associated port configuration pins High or Low to select the desired
mode (auto-negotiation, speed, and duplex). When auto-negotiation is enabled with LED/CFG1
(JP1) = 1, then LED/CFG2 (JP2), and LED/CFG3 (JP3) are used to configure default advertising
characteristics of the LXD972M Demo Board. The desired modes and jumper configuration
settings are listed in Table 9. For specific register definitions and functions, see the LXT972M
Transceiver datasheet.
2.5 JTAG Test Signals
The boundary scan test port is accessed through JP14 for board level testing. Table 10 lists the
JTAG test signal descriptions.
Table 9. Jumper Configuration Settings for LED/CFG Pins
Mode Jumper Settings
Auto-
Negotiation
Speed Duplex
JP1
LED/CFG1
Setting
JP2
LED/CFG2
Setting
JP3
LED/CFG3
Setting
Disabled
10
Half
Jumper
Pins 2 & 3
Jumper
Pins 2 & 3
Jumper
Pins 2 & 3
Full Pins 2 & 3 Pins 2 & 3 Pins 1 & 2
100
Half Pins 2 & 3 Pins 1 & 2 Pins 2 & 3
Full Pins 2 & 3 Pins 1 & 2 Pins 1 & 2
Enabled
100
Half Pins 1 & 2 Pins 2 & 3 Pins 2 & 3
Full /
Half
Pins 1 & 2 Pins 2 & 3 Pins 1 & 2
10/100
Half Pins 1 & 2 Pins 1 & 2 Pins 2 & 3
Full /
Half
Pins 1 & 2 Pins 1 & 2 Pins 1 & 2
Table 10. JTAG Test Signal Descriptions
JP14 Pin
Number
Symbol Description
1TRST_LTest Reset. Test reset input sourced by testing device.
3TCK
Test Clock. Test clock input sourced by testing device.
5TMS
Test Mode Select.
7TDO
Test Data Output. Test data driven with respect to the falling edge of TCK.
8TDI
Test Data Input. Test data sampled with respect to the rising edge of TCK.
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
Preliminary User’s Guide 15
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
3.0 Intel
®
LXD972M Demo Board Schematics
This section includes schematics for the LXD972M Demo Board:
• Figure 4, “Schematic: Intel
®
LXD972M Transceiver Demo Board Power Control” on page 16
• Figure 5, “Schematic: Intel
®
LXD972M Transceiver Demo Board MII Port” on page 17
• Figure 6, “Schematic: Intel
®
LXD972M Transceiver Demo Board Twisted-Pair Port” on
page 18
• Figure 7, “Schematic: Intel
®
LXD972M Transceiver Demo Board Configuration” on page 19
Note: Page 1 of 5 of the schematics is not included (the title page of the schematics).
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
16 Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Figure 4. Schematic: Intel
®
LXD972M Transceiver Demo Board Power Control
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
POWER
IN
JTAG PORT
LXT972M: 3.3V
X=DO NOT INSTALL
LXT972M: R73
AND C53 ARE
NOT POPULATED
LXT972M: 2.5V/3.3V
LXT972M: 3.3V
GND
VCC
VCCIO
VCCD
Intel(R) LXD972M Transceiver Demo Board CONTROL/POWER
A1
LXD972M LQFP48C DV/DEMO
Intel Corporation
9750 Goethe Road
Sacramento, CA 95827
B
25Monday, September 20, 2004
Title
Size Document Number Rev
Date: Sheet
of
MDIO
MDC
ADDR0
RESET
ADDR1
VCCA
TDI
TRST
TCK
TMS
TDO
MDIO
MDC
VCCA
MDIO_1
MDC_1
GND
VCC
GNDGND
GND
GND
GND
VCC
GND
GND
VCC
GND
GND GND
GND
GND
GND
GND
GND
VCC
VCCIO
VCCIO
VCCD
VCCIO
VCCD
VCCIO
GND
VCCD
VCCIO VCCD
GND
BN2
1
SW1
SW DIP-4
1
2
3
4
8
7
6
5
R83 50 1%
C4
.001uF
+
C57
100uF
JP18
HEADER 3X2
12
34
56
J2
RJ11
1
2
3
4
5
6
JP17
HEADER 3_1
1
2
3
+
C36
100uF
U2A
LXT972M_LQFP48C
38
13
39
6
29
16
4 2
32
31
5
3
24
25
9
30
12
7
8
11
10
23
22
21
20
19
GNDD
GNDA
VCCD
VCCIO
VCCIO
VCCA
RESET REFCLK/XI
MDC
MDIO
GNDIO
XO
CE/TEST0
GNDIO/TEST1
GNDIO
GNDIO
RBIAS
NC
NC
ADDR1
ADDR0
TRST
TCK
TMS
TDO
TDI
C6
0.1uF
+
C54
10uF
TP39
1
C33
18pF 25V
Y1
25MHz
C53X
R82
X
R66
4.7k
R61
4.7k
U5A
74LVX14
1 2
C51
0.1uF
R62
4.7k
R73
X
R67
10K
+
C55
100uF
S2
RESET
+
C34
10uF
TP34
1
C3
0.1uF
C7
.001uF
TP36
1
TP40
1
R69
22.1K 1%
JP12
2-pin
C52
.001uF
C10
0.1uF
U5B
74LVX14
3 4
R65
100K
JP14
HEADER 4X2
12
34
56
78
BN3
1
+
C31
10uF
R60
4.7k
JP16
HEADER 3_1
1
2
3
D2
LED
R72
220
JP19
2-pin
D1
1N914
BN1
1
+
C56
10uF
TP35
1
R58
4.7k
BN4
1
C32
18pF 25V
FB4
FERRITE
R68
100
C12
.001uF
XIN
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
Preliminary User’s Guide 17
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Figure 5. Schematic: Intel
®
LXD972M Transceiver Demo Board MII Port
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
X=DO NOT INSTALL
Intel(R) LXD972M Transceiver Demo Board MII PORT
A1
LXD972M LQFP48C DV/DEMO
Intel Corporation
9750 Goethe Road
Sacramento, CA 95827
B
35Monday, September 20, 2004
Title
Size Document Number Rev
Date: Sheet
of
R0
TC
R1
R2
RV
T2
RC
RE
T1
T0
T3
TN
CR
CL
R3
MDIO_1
MDC_1
LED/CFG2
LED/CFG3
LED/CFG1
TPFOP
TPFON
TPFIP
TPFIN
GND
GND
VCC
GND
GND
VCC
GND
VCC
GND
VCC
GND
VCC
GND
R80
X
TP26
1
R27 50 1%
R34
22
U2B
LXT972M_LQFP48C
33
34
35
36
37
40
41
42
43
44
45
46
47
48
1
28
27
26
15
14
18
17
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_CLK
RX_ER
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
COL
CRS
LED/CFG1
LED/CFG2
LED/CFG3
TPFON0
TPFOP0
TPFIN
TPFIP
R38
22
R79
X
R31 50 1%
R43
50 1%
U3
SN74LVC244A
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
2010
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCCGND
R41
50 1%
R30
22
R47 50 1%
R81
X
U1
SN74LVC244A
2
4
6
8
11
13
15
17
1
19
18
16
14
12
9
7
5
3
2010
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1G
2G
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCCGND
R78
X
TP15
1
R25 50 1%
P1
MII 40 PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TP27
1
R42
50 1%
TP16
1
TP41
1
R45 22
R24 50 1%
TP24
1
R37
22
TP42
1
TP28
1
R29 50 1%
TP17
1
TP43
1
R36
22
TP29
1
R35
50 1%
R33 50 1%
R44
50 1%
TP18
1
R26
22
R77
X
TP30
1
TP19
1
TP22
1
TP25
1
R48 22
R28
22
R40
50 1%
R46 50 1%
TP20
1
R23 50 1%
R32
22
C14
0.1uF
TP21
1
C15
0.1uF
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
18 Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Figure 6. Schematic: Intel
®
LXD972M Transceiver Demo Board Twisted-Pair Port
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
TP PORT
TX CT VOLTAGE SET
Intel(R) LXD972M Transceiver Demo Board TP PORT
A1
LXD972M LQFP48C DV/DEMO
Intel Corporation
9750 Goethe Road
Sacramento, CA 95827
B
45Monday, September 20, 2004
Title
Size Document Number Rev
Date: Sheet
of
IP
IN
OP
ON
VCCA
TPFON
TPFIP
TPFOP
TPFIN
GND
GND
R4
50 1%
C59
0.001uF 2KV
JP4
JUMPER 1X1
R7
50 1%
DTP3
DIFF TP
+
|
C47
0.001uF 2KV
C18
0.001uF 2KV
DTP4
DIFF TP
+
|
R9
50 1%
C44
270pF
DTP1
DIFF TP
+
|
T1
Halo TG110-S050N5
9
11
14
15
16
6
7
2
1
3
8
10
R13
50 1%
R8
50 1%
C58
0.001uF 2KV
R12
50 1%
R5
50 1%
DTP2
DIFF TP
+
|
C48
0.001uF 2KV
C17
0.01uF
R6
50 1%
J1
RJ45
1
2
3
4
5
6
7
8
C49
0.01uF
FB5
FERRITE
C43
270pF
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
Preliminary User’s Guide 19
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
Figure 7. Schematic: Intel
®
LXD972M Transceiver Demo Board Configuration
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
DISTRIBUTE, LABEL AS "GND"
LED1
X=DO NOT INSTALL
LED2
CFG
Intel(R) LXD972M Transceiver CAPS, LED CONFIG., MISC. A1
LXD972M LQFP48C DV/DEMO
Intel Corporation
9750 Goethe Road
Sacramento, CA 95827
B
55Monday, September 20, 2004
Title
Size Document Number Rev
Date: Sheet
of
VCCX
LED/CFG1
LED/CFG2
LED/CFG3
GND
VCCIO
GND
VCCIO
GND
VCCIO
GND
GND
GND
VCC
GND
GND
GND
C37
20pF
D6
LED
J3 SMB
1
2
3
4
5
R76
50 1%
D3
LED
TP37
1
TP2
1
C16
0.1uF
JP2
HEADER 3 PIN
1
2
3
D5
LED
TP3
1
R2
180
C50
0.1uF
JP3
HEADER 3 PIN
1
2
3
FB6
X
D8
LED
FB3
FERRITE
D4
LED
TP38
1
R3
180
TP5
1
R75
X
D7
LED
JP1
HEADER 3 PIN
1
2
3
R70
50 1%
R1
180
Y2
25MHzCRYSTAL OSC
1
78
14
NC
GNDOUT
VCC
TP4
1
R74
0
XIN
Intel
®
LXD972M Transceiver Demo Board (Board Rev A1)
20 Preliminary User’s Guide
Document Number: 303125
Revision Number: 002
Revision Date: October 22, 2004
4.0 Bill of Materials
Table 11 lists the bill of materials for the LXD972M Demo Board Rev A1.
Table 11. Bill of Materials (Sheet 1 of 3)
Board Reference
Designator
Description Manufacturer Part Number Quantity
BN1-4
CONN BANANA NUT
SILVER (BANANA_NUT)
EF JOHNSON 108-0740-001 4
C1, C2, C5, C8, C9, C11,
C13, C38-C42, C45, C46
LABELS NOT USED IN SCHEMATIC.
C3, C6, C10, C14-16,
C50-51
HEADER 3X1 (SIP\3P) BERG 08055C104KATMA 8
C4, C7, C12, C52
HEADER 4X2
(HEADER2X4)
BERG ECU-V1H102JCX 4
C17, C49
CAP 0.01uF X7R 10%
(0805)
AVX 08055C103KATMA 2
C53 (NOT INSTALLED) NOT INSTALLED X 1
C18, C47-48, C58-59
CAP 1000pF 20% 2KV X7R
(1812)
AVX 1812GC102KAT1A 5
C31, C34, C54, C56
CAP 10uF 6.3V TANT
(CASEA)
PANASONIC ECS-TOJY106R 4
C32-33 CAP 18pF 50V 5% (0805) PANASONIC ECU-V1H180JCN 2
C36, C55, C57 CAP 100uF 6.3V (CASED) PANASONIC ECE-V0JA101P 3
C37 CAP 20PF 50V 5% (1206) PANASONIC ECU-V1H200JCM 1
C43-44 CAP 270pF NPO (1206) AVX 12061A271JATTA 2
D1
DIODE RECTIFIER DL4001
1A 50V MELF SMD
DIODES INC. DL4001-13 1
D2-D8
DIODE LED GREEN SS
TYPE LOW CUR SMD
(LED\SMD\SS)
PANASONIC LNJ308G8LRA 7
DTP1-4, JP4, JP12, JP19 HEADER 2X1 (SIP\2P) BERG 68000-240-2 7
FB1, FB2 LABELS NOT USED IN SCHEMATIC.
FB3-5
FBEAD 60 OHM@100MHZ
0.10OHM@DC 1.5A (1210)
(BEAD3225)
STEWARD MI1210K600R-00 3
FB6 (NOT INSTALLED) NOT INSTALLED X 1
J1
CONN MOD JACK 8-8
LOW PROFILE
AMP 555164-1 1
J2
CONN MOD JACK 6-6
RJ11 UNSHIELDED
BLOCK RJ11-6L-B
CORCOM RJ11-6L-B 1
J3
CONN SMB VERTICAL PC
MOUNT (SMB\SM)
JOHNSON
COMPONENTS
131-3711-201 1
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Intel LXD972M User manual

Intel
Brand
Intel
Model
LXD972M
Category
Network transceiver modules
Type
User manual

Intel LXD972M is a single-port 10/100 Mbps PHY transceiver that supports 3.3V operation and has an optional 2.5V I/O voltage. It consumes only 300 mW of power, has low power consumption, and features LED indicators for major functions. With its configurable settings and JTAG boundary scan port, this device is suitable for various applications.

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