Xilinx LogiCORE IP User manual

Brand: Xilinx

Model: LogiCORE IP

Type: User manual

LogiCORE™ IP

Video Scaler v4.0

User Guide

UG805 March 1, 2011

Video Scaler v4.0 User Guide www.xilinx.com UG805 March 1, 2011

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Revision History

The following table shows the revision history for this document.

Date Version Revision

04/24/09 1.0 Initial Xilinx release.

09/16/09 2.0 Updated for core release version 2.0.

04/19/10 2.1 Updated for core release version 2.1.

09/21/10 3.0 Updated for core release version 3.0.

03/01/11 4.0 Updated for core release version 4.0.

UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide

Table of Contents

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Schedule of Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Schedule of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Preface: About This Guide

Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Typographical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Chapter 1: Introduction

About the Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Recommended Experience. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Additional Core Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Providing Feedback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 2: Overview

Chapter 3: Implementation

Basic Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

I/O Buffering, Clock Domains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 4: Video I/O Interface and Timing

Data Source: Live Video. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Input Data and Timing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

General Input Handshaking Principles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Hblank_in Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Vblank_in Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Frame_rst Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Active_video_in Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Data Source: Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Output Data and Timing Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide

Chapter 5: Scaler Architectures

Architecture Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Single-Engine for Sequential YC Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

4:2:0 Special Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Dual-Engine for Parallel YC Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Triple-Engine for RGB/4:4:4 Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

GUI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Chapter 6: Control Interface

Control Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Constant (Fixed) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

General Purpose Processor (GPP) Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Coefficient Delivery for GPP Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

EDK pCore Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Parameter Modification in CORE Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Scaler Software Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Coefficient Delivery for EDK pCore Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Chapter 7: Scaler Aperture

Input Aperture Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Cropping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Chapter 8: Coefficients

Coefficient Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Coefficient Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Examples of Coefficient Set Generation and Loading . . . . . . . . . . . . . . . . . . . . . . . . 44

Example 1: Num_h_taps = num_v_taps = 8; max_phases = 4 . . . . . . . . . . . . . . . . . . . 44

Example 2: Num_h_taps = num_v_taps = 8;

max_phases = 5, 6, 7 or 8; num_h_phases = num_v_phases = 4 . . . . . . . . . . . . . . . 47

Example 3: Num_h_taps = 9; num_v_taps = 7;

max_phases = num_h_phases = num_v_phases = 4 . . . . . . . . . . . . . . . . . . . . . . . . . 49

Coefficient Preloading Using a .coe File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Generating .coe Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Extracting Coefficients From xscaler_coefs.c File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Format for .coe Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Coefficient Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Chapter 9: Performance

Live Video Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Appendix A: Use Cases

Typical Uses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide

Appendix B: Programmer Guide

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Filter Coefficient Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Video Scaler Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

System Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Proposed API function calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

L0 API Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

L1 API Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

L2 API Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

Example Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Pass Thru . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Down Sample by 2 in Horizontal and Vertical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Appendix C: System Level Design

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Example System General Configuration.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Control Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

VDMA0 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

VDMA1 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

VDMA2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Video Scaler Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

MPMC Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Scaler READ-port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

Scaler WRITE-port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Cropping from Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

OSD Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

EDK MHS File Text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

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UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide

Schedule of Figures

Chapter 1: Introduction

Chapter 2: Overview

Chapter 3: Implementation

Figure 3-1: High Level View of the Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 3-2: Simplified Top Level Block Diagram, Indicating Clock-domains . . . . . . . . 22

Chapter 4: Video I/O Interface and Timing

Figure 4-1: Scaler 8-bit 4:2:2 Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4-2: Scaler 8-bit 4:2:0 Input Chroma Validation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 4-3: VBlank, HBlank, Frame_rst, LineCount Screenshot,

with Frame Reset Line Number = 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 4-4: Interface Timing for Memory Source Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 4-5: Scaler Output Timing (8-bits YC4:2:2/4:2:0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 4-6: Scaler 4:2:0 Output Validation (8-bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Chapter 5: Scaler Architectures

Figure 5-1: Internal Data Path Bitwidths for Single-Engine YC Mode . . . . . . . . . . . . . . . 29

Figure 5-2: Internal Data Path Bitwidths for Dual-Engine YC Mode . . . . . . . . . . . . . . . . 30

Figure 5-3: Internal Data Path Bitwidths for Triple-Engine RGB/4:4:4 Architecture . . . 30

Figure 5-4: Auto Select in GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 5-5: CORE Generator GUI Information Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Chapter 6: Control Interface

Figure 6-1: Typical EDK-based System Showing Interrupt Structure. . . . . . . . . . . . . . . . 38

Chapter 7: Scaler Aperture

Figure 7-1: Hblank_in at Falling Edge of VBlank_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 7-2: Active_video_in in Relation to First Active Sample . . . . . . . . . . . . . . . . . . . . . 40

Figure 7-3: Cropping from the Input Image . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Chapter 8: Coefficients

Figure 8-1: Coefficient Write-Format on coef_data_in(31:0) . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 8-2: Coefficient Loading Mechanism, Including External FIFO . . . . . . . . . . . . . . 43

Figure 8-3: Coefficient Loading Procedure – One Phase (8-tap filter shown) . . . . . . . . . 44

UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide

Chapter 9: Performance

Appendix A: Use Cases

Figure A-1: Format Down-scaling. Example 720p to 640x480,

HSF = 2

x 1280/640; VSF = 2

x 720/480 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure A-2: Format Up-scaling. Example 640x480 to 720p,

HSF = 2

x 640/1280; 2

x VSF = 480/720 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure A-3: Zoom (Up-scaling), HSF = 2

x 480/1280; VSF = 2

x 270/720 . . . . . . . . . . . . 72

Figure A-4: Shrink (Down-scaling). Example for Picture-in-Picture (PinP),

HSF = 2

x 1280/480; VSF = 2

x 720/270 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Figure A-5: Zoom (Up-scaling) reading from External Memory,

HSF = 2

x 480/1280; VSF = 2

x 270/720 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Appendix B: Programmer Guide

Figure B-0: Video Scaler Flow Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Figure B-0: System Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Appendix C: System Level Design

Figure C-1: Simplified System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

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Schedule of Tables

Chapter 1: Introduction

Table 1-1: Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Chapter 2: Overview

Chapter 3: Implementation

Chapter 4: Video I/O Interface and Timing

Chapter 5: Scaler Architectures

Chapter 6: Control Interface

Chapter 7: Scaler Aperture

Chapter 8: Coefficients

Table 8-1: Example 1 Decimal Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 8-2: Example 1 Normalized Integer Coefficients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 8-3: Example 1 Coefficient Set Download Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 8-4: Example 2 Coefficient Set Download Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 8-5: Example 9-Tap Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 8-7: Example 3 Coefficient Set Download Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 8-6: Example 7-Tap Coefficients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 8-8: Coefficient “Binning” in SW Driver (xscaler_coefs.c) . . . . . . . . . . . . . . . . . . . . 52

Table 8-9: Ordering of Coefficients in .coe File for Different Coefficient Sharing

Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 8-10: .coe File Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Table 8-11: .coe File Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 8-12: .coe File Example 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Chapter 9: Performance

Table 9-1: Target Maximum Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 9-2: Throughput Calculations for Different Chroma Formats . . . . . . . . . . . . . . . . . 63

UG805 March 1, 2011 www.xilinx.com Video Scaler v4.0 User Guide

Appendix A: Use Cases

Appendix B: Programmer Guide

Table B-1: Video Scaler Registers Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Table B-2: control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table B-3: reserved Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table B-4: status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Table B-5: status_done Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table B-6: horizontal_shrink_factor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table B-7: vsf Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Table B-8: aperture_horz Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table B-9: aperture_vert Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table B-10: output_size Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Table B-11: num_phases Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table B-12: coeff_sets Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table B-13: start_hpa_y Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

Table B-14: start_vpa_y Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table B-15: start_hpa_c Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table B-16: start_vpa_c Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table B-17: Coefficient_write_set_address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

Table B-18: coef_values Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Table B-19: Coefficient Set and Bank Read Address Register. . . . . . . . . . . . . . . . . . . . . . . 82

Table B-20: Coefficient Phase and Tap Read Address Register. . . . . . . . . . . . . . . . . . . . . . 83

Table B-21: Coefficient Memory Readback Output Register. . . . . . . . . . . . . . . . . . . . . . . . 83

Table B-22: Version Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table B-23: Software Reset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Table B-24: Global Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table B-25: Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

Table B-26:

Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Table B-27: Pass Through Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Table B-28: Down Sample Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Appendix C: System Level Design

Video Scaler v4.0 User Guide www.xilinx.com 11

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Preface

About This Guide

The LogiCORE™ IP Video Scaler v4.0 User Guide provides information about generating the

Video Scaler core, customizing and simulating the core using the provided example

design, and running the design files through implementation using the Xilinx tools.

Guide Contents

This manual contains the following chapters:

• Chapter 1, Introduction introduces the Xilinx Video Scaler core and provides related

information, including recommended design experience, additional resources,

technical support, and submitting feedback to Xilinx.

• Chapter 2, Overview illustrates examples of video scaler applications.

• Chapter 3, Implementation elaborates on the internal structure in the core and

describes interfacing.

• Chapter 4, Video I/O Interface and Timing describes how to drive the input timing

signals so the scaler can be operated correctly. It also describes the data output signals

and their relation to the output data.

• Chapter 5, Scaler Architectures describes Single-engine for sequential YC processing,

Dual Engine for parallel YC processing, and Triple engine for parallel RGB/4:4:4

processing.

• Chapter 6, Control Interface discusses the three control interface options available to

the user in CORE Generator™ software: EDK pCore, GPP and Constant.

• Chapter 7, Scaler Aperture explains how to define the scaler aperture using the

appropriate dynamic control registers.

• Chapter 8, Coefficients describes the coefficients used by both the Vertical and

Horizontal filter portions of the scaler, in terms of number, range, formatting and

download procedures.

• Chapter 9, Performance emphasizes the importance of available clock rate and

provides some worst-case conversion examples.

• Appendix A, Use Cases illustrates two likely usage scenarios for the video scaler.

• Appendix B, Programmer Guide provides a description of how to program and

control the data flow for the video scaler hardware pCore.

•"Appendix C, System Level Design provides an example design extracted from a

known, working EDK project, including other Video IP blocks.

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Preface: About This Guide

Additional Resources

To find additional documentation, see the Xilinx website at:

http://www.xilinx.com/support/documentation/index.htm

To search the Answer Database of silicon, software, and IP questions and answers, or to

create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support/mysupport.htm

Conventions

This document uses the following conventions. An example illustrates each convention.

Typographical

The following typographical conventions are used in this document:

Convention Meaning or Use Example

Courier font

Messages, prompts, and

program files that the system

displays

speed grade: - 100

Courier bold

Literal commands that you enter

in a syntactical statement

ngdbuild design_name

Helvetica bold

Commands that you select from

a menu

File  Open

Keyboard shortcuts Ctrl+C

Italic font

Variables in a syntax statement

for which you must supply

values

ngdbuild design_name

References to other manuals

See the User Guide for more

information.

Emphasis in text

If a wire is drawn so that it

overlaps the pin of a symbol, the

two nets are not connected.

Dark Shading

Items that are not supported or

reserved

This feature is not supported

Square brackets [ ]

An optional entry or parameter.

However, in bus specifications,

such as bus[7:0], they are

required.

ngdbuild [option_name]

design_name

Braces { }

A list of items from which you

must choose one or more

lowpwr ={on|off}

Vertical bar |

Separates items in a list of

choices

lowpwr ={on|off}

Angle brackets < >

User-defined variable or in code

samples

Video Scaler v4.0 User Guide www.xilinx.com 13

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Conventions

Online Document

The following conventions are used in this document:

Vertical ellipsis

Repetitive material that has

been omitted

IOB #1: Name = QOUT’

IOB #2: Name = CLKIN’

Horizontal ellipsis . . .

Repetitive material that has

been omitted

allow block block_name loc1

loc2 ... locn;

Notations

The prefix ‘0x’ or the suffix ‘h’

indicate hexadecimal notation

A read of address 0x00112975

returned 45524943h.

An ‘_n’ means the signal is

active low

usr_teof_n is active low.

Convention Meaning or Use Example

Blue text

Cross-reference link to a location

in the current document

See Chapter 3, Basic

Architecture for details.

See Additional Resources,

page 12,” for details.

Blue, underlined text

Hyperlink to a website (URL)

Go to www.xilinx.com

for the

latest speed files.

14 www.xilinx.com Video Scaler v4.0 User Guide

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Preface: About This Guide

Video Scaler v4.0 User Guide www.xilinx.com 15

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Chapter 1

Introduction

This chapter introduces the Video Scaler core and provides related information, including

recommended design experience, additional resources, technical support, and submitting

feedback to Xilinx. See www.xilinx.com/products/ipcenter/EF-DI-VID-SCALER.htm

About the Core

The Video Scaler core is a Xilinx CORE Generator™ IP core, included in the latest IP

Update on the Xilinx IP Center

. For detailed information about the core, see the Video

Scaler product page.

Recommended Experience

Although the Video Scaler core is a fully verified solution, the challenge associated with

implementing a complete design varies depending on the configuration and functionality

of the application. For best results, previous experience building high performance,

pipelined FPGA designs using Xilinx implementation software and UCF is recommended.

Contact your local Xilinx representative for a closer review and estimation for your specific

requirements

Additional Core Resources

For detailed information about video scaler technology and updates to the Video Scaler

core, see the following:

Documentation

From the Video Scaler product page:

• Video Scaler Data Sheet

• Video Scaler Release Notes

Technical Support

For technical support, visit www.xilinx.com/support. Questions are routed to a team of

engineers with expertise using the Video Scaler core.

Xilinx will provide technical support for use of this product as described in the

LogiCORE™ IP Video Scaler User Guide. Xilinx cannot guarantee timing, functionality, or

support of this product for designs that do not follow these guidelines.

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Chapter 1: Introduction

Providing Feedback

Xilinx welcomes comments and suggestions about the Video Scaler core and the

documentation supplied with the core.

Core

For comments or suggestions about the Video Scaler core, submit a WebCase from

www.xilinx.com/support

. Be sure to include the following information:

•Product name

• Core version number

• Explanation of your comments

Documentation

For comments or suggestions about this document, submit a WebCase from

www.xilinx.com/support

. Be sure to include the following information:

• Document title

•Document number

• Page number(s) to which your comments refer

• Explanation of your comments

Nomenclature

The following are defined for the purposes of this document:

Table 1-1: Nomenclature

Term Definition

Scaler Aperture The input data rectangle used to create the output data rectangle.

Filter Aperture The group of contributory data used in a filter to generate one

particular output. The number of elements in this group of data is

the number of taps. We define the filter aperture size using the

num_h_taps and num_v_taps parameters.

Coefficient Phase Each tap is multiplied by a coefficient to make its contribution to

the output pixel. The coefficients used are selected from a “phase”

of num_x_taps coefficients. The phase selection is dependent

upon the position of the output pixel in the input sampling grid

space. For each dimension of the filter, each coefficient phase

consists of num_h_taps or num_v_taps coefficients.

Channel For scaler purposes, all monochromatic video streams, for example

Y, Cb, Cr, R, G, B, are all considered separate channels.

Coefficient Phase Index An index given that selects the coefficient phase applied to one

filter aperture in a FIR. For an n-tap filter, this index points to n

coefficients.

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Nomenclature

Coefficient Bank A group of coefficients that will be applied to one video component

(Y or C) in one dimension (H or V) for a conversion of one frame. It

includes all phases. For an n-tap, m-phase filter, a coefficient bank

comprises nxm values. Each tap may be multiplied by any one of

m coefficients assigned to it, selected by the phase index, which is

applied to all taps.

Coefficient Set A group of four coefficient banks (VY, VC, HY, HC). One full set

should be written into the scaler before use.

Table 1-1: Nomenclature

Term Definition

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Chapter 1: Introduction

Video Scaler v4.0 User Guide www.xilinx.com 19

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Chapter 2

Overview

Video scaling is the process of converting an input color image of dimensions X

pixels by

lines to an output color image of dimensions X

out

pixels by Y

out

lines.

Within predefined limits, the Xilinx Video Scaler supports the modification of the X

, Y

out

, Y

out

input parameters during run-time on a frame basis. Furthermore, you may also

dynamically crop selected subject area from the input image prior to scaling that area. This

dynamic combination lends itself well to applications that require shrink and zoom

functionality.

The Xilinx Video Scaler supports real-time video inputs and memory interface inputs (that

is, a frame buffer). When connected to a real-time input source, the input clock and

horizontal and vertical (H/V) timing signals come directly from the input video stream. In

the case of a memory interface, standard memory handshaking signals may be used in

place of the H/V timing signals.

While maintaining image quality is usually of primary interest, it is subjective and heavily

dependent upon the end application. Moreover, image quality comes at a price in terms of

FPGA resources. Hence, while the core structure and architecture of the scaler is

maintained for all applications, flexibility is made paramount to enable users from all

applications to use this IP.

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Chapter 2: Overview

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