Section number Title Page
25.2 ADC signal descriptions...............................................................................................................................................341
25.2.1 Analog Power (VDDA).................................................................................................................................342
25.2.2 Analog Ground (VSSA).................................................................................................................................342
25.2.3 Analog Channel Inputs (ADx).......................................................................................................................342
25.3 Memory map and register definitions...........................................................................................................................342
25.3.1 ADC Status and Control Registers 1 (ADCx_SC1n).....................................................................................343
25.3.2 ADC Configuration Register 1 (ADCx_CFG1).............................................................................................347
25.3.3 ADC Configuration Register 2 (ADCx_CFG2).............................................................................................348
25.3.4 ADC Data Result Register (ADCx_Rn).........................................................................................................349
25.3.5 Compare Value Registers (ADCx_CVn).......................................................................................................350
25.3.6 Status and Control Register 2 (ADCx_SC2)..................................................................................................351
25.3.7 Status and Control Register 3 (ADCx_SC3)..................................................................................................353
25.3.8 ADC Offset Correction Register (ADCx_OFS).............................................................................................355
25.3.9 ADC Plus-Side Gain Register (ADCx_PG)...................................................................................................355
25.3.10 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)...........................................................356
25.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............................................................356
25.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............................................................357
25.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)............................................................357
25.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)............................................................358
25.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)............................................................358
25.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)............................................................359
25.4 Functional description...................................................................................................................................................359
25.4.1 Clock select and divide control......................................................................................................................360
25.4.2 Voltage reference selection............................................................................................................................360
25.4.3 Hardware trigger and channel selects............................................................................................................361
25.4.4 Conversion control.........................................................................................................................................362
25.4.5 Automatic compare function..........................................................................................................................368
25.4.6 Calibration function.......................................................................................................................................370
25.4.7 User-defined offset function..........................................................................................................................371
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
16 Freescale Semiconductor, Inc.