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KL0x
NXP KL0x Reference guide
Type
Reference guide
Brand
NXP
Size
5.03 MB
Pages
535
Language
English
View document
NXP KL0x Reference guide
Type
Reference guide
Brand
NXP
Size
4.78 MB
Pages
607
Language
English
View document
NXP KL0x Reference guide
Type
Reference guide
Brand
NXP
Size
6.83 MB
Pages
537
Language
English
Table of contents
Purpose
25
Audience
25
Numbering systems
25
Typographic notation
26
Special terms
26
ARM Cortex-M0+ core modules
31
System modules
32
Memories and memory interfaces
33
Clocks
33
Security and integrity modules
33
Analog modules
34
Timer modules
34
Communication interfaces
34
Human-machine interfaces
35
Interconnection overview
37
Analog reference options
38
ARM Cortex-M0+ core configuration
39
ARM Cortex M0+ core
40
Buses, interconnects, and interfaces
41
System tick timer
41
Debug facilities
41
Core privilege levels
41
Nested vectored interrupt controller (NVIC) configuration
42
Interrupt priority levels
42
Non-maskable interrupt
42
Interrupt channel assignments
43
Determining the bitfield and register location for configuring a particular interrupt
44
Asynchronous wake-up interrupt controller (AWIC) configuration
45
Wake-up sources
46
SIM configuration
46
System mode controller (SMC) configuration
47
VLLS2 not supported
48
PMC configuration
48
MCM configuration
48
Crossbar-light switch configuration
49
Crossbar-light switch master assignments
50
Crossbar switch slave assignments
50
Peripheral bridge configuration
51
Number of peripheral bridges
51
Memory maps
51
Computer operating properly (COP) watchdog configuration
52
COP clocks
52
COP watchdog operation
52
Clock gating
54
MCG configuration
54
MCG FLL modes
55
OSC configuration
55
OSC modes of operation with MCG
56
Flash memory configuration
56
Flash memory sizes
56
Flash memory map
57
Flash security
57
Flash modes
58
Erase all flash contents
58
FTFA_FOPT register
58
Flash memory controller configuration
58
SRAM configuration
59
SRAM sizes
60
SRAM ranges
60
SRAM retention in low power modes
61
12-bit SAR ADC configuration
61
ADC instantiation information
62
ADC0 connections/channel assignment
63
ADC analog supply and reference connections
63
ADC Reference Options
64
Alternate clock
64
CMP configuration
64
CMP instantiation information
65
CMP input connections
66
CMP external references
66
CMP trigger mode
66
Timer/PWM module configuration
67
TPM instantiation information
67
Clock options
68
Trigger options
68
Global timebase
69
TPM interrupts
69
Low-power timer configuration
69
LPTMR instantiation information
70
LPTMR pulse counter input options
70
LPTMR prescaler/glitch filter clocking options
71
SPI configuration
71
SPI instantiation information
72
I2C configuration
72
IIC instantiation information
73
UART configuration
73
UART0 overview
74
GPIO configuration
74
GPIO instantiation information
75
Pull devices and directions
75
Port control and interrupt summary
76
GPIO accessibility in the memory map
76
Alternate non-volatile IRC user trim description
78
Read-after-write sequence and required serialization of memory operations
80
Peripheral bridge (AIPS-Lite) memory map
80
Modules restricted access in user mode
84
Device clock summary
87
Clock divider values after reset
89
VLPR mode clocking
89
PMC 1-kHz LPO clock
91
COP clocking
91
LPTMR clocking
92
TPM clocking
92
UART clocking
93
Power-on reset (POR)
95
System reset sources
96
External pin reset (RESET_b)
96
RESET_b pin filter
96
Low-voltage detect (LVD)
97
Computer operating properly (COP) watchdog timer
97
Multipurpose clock generator loss-of-clock (LOC)
97
Stop mode acknowledge error (SACKERR)
98
Software reset (SW)
98
Lockup reset (LOCKUP)
98
MDM-AP system reset request
98
MCU resets
99
RESET_b pin
100
Debug resets
100
Resetting the Debug subsystem
100
Boot sources
101
FOPT boot options
101
Boot sequence
103
Partial Stop
105
Compute Operation
106
Peripheral Doze
107
Clock gating
107
Security interactions with Debug
114
MDM-AP Control Register
117
MDM-AP Status Register
118
Port control and interrupt module features
124
Clock gating
125
Signal multiplexing constraints
125
KL02 signal multiplexing and pin assignments
125
KL02 pinouts
126
Core modules
129
System modules
130
Clock modules
130
Memories and memory interfaces
130
Analog
130
Timer Modules
131
Communication interfaces
131
Human-machine interfaces (HMI)
132
Features
133
Modes of operation
134
Run mode
134
Wait mode
134
Stop mode
134
Debug mode
134
Pin control
142
Global pin control
143
External interrupts
143
Features
145
SIM
146
SIM_SOPT2
146
SIM_SOPT4
147
SIM_SOPT5
149
SIM_SOPT7
150
SIM_SDID
151
SIM_SCGC4
153
SIM_SCGC5
155
SIM_SCGC6
156
SIM_CLKDIV1
157
SIM_FCFG1
159
SIM_FCFG2
160
SIM_UIDMH
161
SIM_UIDML
161
SIM_UIDL
162
SIM_COPC
162
SIM_SRVCOP
163
SMC
167
SMC_PMPROT
167
SMC_PMCTRL
169
SMC_STOPCTRL
170
SMC_PMSTAT
171
Power mode transitions
172
Power mode entry/exit sequencing
175
Stop mode entry sequence
175
Stop mode exit sequence
176
Aborted stop mode entry
176
Transition to wait modes
176
Transition from stop modes to Debug mode
177
Run modes
177
RUN mode
177
Very-Low Power Run (VLPR) mode
177
Wait modes
178
WAIT mode
178
Very-Low-Power Wait (VLPW) mode
179
Stop modes
179
STOP mode
180
Very-Low-Power Stop (VLPS) mode
180
Very-Low-Leakage Stop (VLLSx) modes
180
Debug in low power modes
181
LVD reset operation
184
LVD interrupt operation
184
Low-voltage warning (LVW) interrupt operation
184
PMC
185
PMC_LVDSC1
186
PMC_LVDSC2
187
PMC_REGSC
188
RCM
191
RCM_SRS0
191
RCM_SRS1
193
RCM_RPFC
194
RCM_RPFW
195
Overview
198
Features
198
Modes of operation
199
BME decorated stores
200
Decorated store logical AND (AND)
202
Decorated store logical OR (OR)
203
Decorated store logical XOR (XOR)
204
Decorated store bit field insert (BFI)
205
BME decorated loads
207
Decorated load: load-and-clear 1 bit (LAC1)
210
Decorated Load: Load-and-Set 1 Bit (LAS1)
211
Decorated load unsigned bit field extract (UBFX)
212
Additional details on decorated addresses and GPIO accesses
213
Features
217
MCM
217
MCM_PLASC
218
MCM_PLAMC
219
MCM_PLACR
219
MCM_CPO
222
Overview
225
Features
228
Modes of operation
229
MTB_RAM Memory Map
230
MTB
230
MTB_POSITION
232
MTB_MASTER
233
MTB_FLOW
235
MTB_BASE
237
MTB_MODECTRL
237
MTB_TAGSET
238
MTB_TAGCLEAR
238
MTB_LOCKACCESS
239
MTB_LOCKSTAT
239
MTB_AUTHSTAT
239
MTB_DEVICEARCH
240
MTB_DEVICECFG
241
MTB_DEVICETYPID
241
MTB_PERIPHIDn
242
MTB_COMPIDn
242
MTB_DWT Memory Map
242
MTBDWT
243
MTBDWT_CTRL
244
MTBDWT_COMPn
245
MTBDWT_MASKn
245
MTBDWT_FCT0
247
MTBDWT_FCT1
249
MTBDWT_TBCTRL
250
MTBDWT_DEVICECFG
252
MTBDWT_DEVICETYPID
252
MTBDWT_PERIPHIDn
253
MTBDWT_COMPIDn
253
System ROM Memory Map
253
ROM
254
ROM_ENTRYn
255
ROM_TABLEMARK
256
ROM_SYSACCESS
256
ROM_PERIPHIDn
257
ROM_COMPIDn
257
Features
259
General operation
260
Arbitration
261
Arbitration During Undefined Length Bursts
261
Fixed-priority operation
261
Round-robin priority operation
262
Features
263
General operation
263
Access support
264
Features
265
Modes of Operation
268
MCG
268
MCG_C1
268
MCG_C2
269
MCG_C3
271
MCG_C4
271
MCG_C6
273
MCG_S
273
MCG_SC
274
MCG_ATCVH
276
MCG_ATCVL
276
MCG mode state diagram
276
MCG modes of operation
277
MCG mode switching
279
Low Power Bit Usage
280
MCG Internal Reference Clocks
280
MCG Internal Reference Clock
280
External Reference Clock
281
MCG Fixed frequency clock
281
MCG Auto TRIM (ATM)
281
MCG module initialization sequence
283
Initializing the MCG
283
Using a 32.768 kHz reference
285
MCG mode switching
286
OSC Module States
294
Off
295
Oscillator Start-Up
295
Oscillator Stable
296
External Clock Mode
296
OSC Module Modes
296
Low-Frequency, Low-Power Mode
297
Counter
297
Reference Clock Pin Requirements
297
Overview
299
Features
299
Features
304
Program Flash Memory Features
304
Other Flash Memory Module Features
304
Block Diagram
304
Glossary
305
Flash Configuration Field Description
306
Program Flash IFR Map
307
Program Once Field
307
Register Descriptions
308
FTFA
308
FTFA_FSTAT
309
FTFA_FCNFG
311
FTFA_FSEC
312
FTFA_FOPT
313
FTFA_FCCOBn
314
FTFA_FPROTn
315
Flash Protection
317
Interrupts
317
Flash Operation in Low-Power Modes
318
Wait Mode
318
Stop Mode
318
Functional Modes of Operation
319
Flash Reads and Ignored Writes
319
Read While Write (RWW)
319
Flash Program and Erase
319
Flash Command Operations
319
Command Write Sequence
320
Load the FCCOB Registers
320
Launch the Command by Clearing CCIF
320
Command Execution and Error Reporting
320
Flash Commands
322
Flash Commands by Mode
323
Margin Read Commands
324
Flash Command Description
325
Read 1s Section Command
325
Program Check Command
326
Read Resource Command
327
Program Longword Command
328
Erase Flash Sector Command
330
Suspending an Erase Flash Sector Operation
330
Resuming a Suspended Erase Flash Sector Operation
331
Aborting a Suspended Erase Flash Sector Operation
331
Read 1s All Blocks Command
332
Read Once Command
333
Program Once Command
334
Erase All Blocks Command
335
Triggering an Erase All External to the Flash Memory Module
336
Verify Backdoor Access Key Command
336
Security
338
Flash Memory Access by Mode and Security
338
Changing the Security State
338
Unsecuring the Chip Using Backdoor Key Access
339
Reset Sequence
340
Features
341
Block diagram
342
Analog Power (VDDA)
344
Analog Ground (VSSA)
344
Analog Channel Inputs (ADx)
344
Clock select and divide control
362
Voltage reference selection
362
Hardware trigger and channel selects
363
Conversion control
364
Initiating conversions
364
Completing conversions
365
Aborting conversions
365
Power control
366
Sample time and total conversion time
366
Conversion time examples
369
Typical conversion time configuration
369
Short conversion time configuration
369
Hardware average function
370
Automatic compare function
370
Calibration function
372
User-defined offset function
373
Temperature sensor
374
MCU wait mode operation
375
MCU Normal Stop mode operation
375
Normal Stop mode with ADACK disabled
376
Normal Stop mode with ADACK enabled
376
MCU Low-Power Stop mode operation
376
ADC module initialization example
377
Initialization sequence
377
Pseudo-code example
377
External pins and routing
379
Analog supply pins
379
Analog voltage reference pins
380
Analog input pins
381
Sources of error
381
Sampling error
381
Pin leakage error
382
Noise-induced errors
382
Code width and quantization error
383
Linearity errors
383
Code jitter, non-monotonicity, and missing codes
384
CMP functional modes
395
Disabled mode (# 1)
397
Continuous mode (#s 2A & 2B)
397
Sampled, Non-Filtered mode (#s 3A & 3B)
398
Sampled, Filtered mode (#s 4A & 4B)
399
Windowed mode (#s 5A & 5B)
401
Windowed/Resampled mode (# 6)
403
Windowed/Filtered mode (#7)
404
Power modes
404
Wait mode operation
404
Stop mode operation
405
Background Debug Mode Operation
405
Startup and operation
405
Low-pass filter
405
Enabling filter modes
406
Latency issues
407
Voltage reference source select
409
TPM Philosophy
411
Features
411
Modes of Operation
412
Block Diagram
412
TPM_EXTCLK — TPM External Clock
413
TPM_CHn — TPM Channel (n) I/O Pin
414
Clock Domains
424
Counter Clock Mode
424
Prescaler
424
Counter
425
Up Counting
425
Up-Down Counting
426
Counter Reset
427
Input Capture Mode
427
Output Compare Mode
428
Edge-Aligned PWM (EPWM) Mode
429
Center-Aligned PWM (CPWM) Mode
431
Registers Updated from Write Buffers
433
MOD Register Update
433
CnV Register Update
433
Reset Overview
433
TPM Interrupts
434
Timer Overflow Interrupt
434
Channel (n) Interrupt
434
Features
435
Modes of operation
435
Detailed signal descriptions
436
LPTMR power and reset
441
LPTMR clocking
441
LPTMR prescaler/glitch filter
441
Prescaler enabled
442
Prescaler bypassed
442
Glitch filter
442
Glitch filter bypassed
442
LPTMR compare
443
LPTMR counter
443
LPTMR hardware trigger
444
LPTMR interrupt
444
Features
445
Modes of operation
446
Block diagrams
446
SPI system block diagram
447
SPI module block diagram
447
SPSCK — SPI Serial Clock
449
MOSI — Master Data Out, Slave Data In
449
MISO — Master Data In, Slave Data Out
449
SS — Slave Select
449
General
457
Master mode
457
Slave mode
459
SPI clock formats
460
SPI baud rate generation
463
Special features
463
SS Output
463
Bidirectional mode (MOMI or SISO)
464
Error conditions
465
Mode fault error
465
Low-power mode options
466
SPI in Run mode
466
SPI in Wait mode
466
SPI in Stop mode
467
Reset
467
Interrupts
468
MODF
468
SPRF
468
SPTEF
469
SPMF
469
Asynchronous interrupt in low-power modes
469
Initialization sequence
469
Pseudo-Code Example
470
Features
473
Modes of operation
474
Block diagram
474
I2C protocol
484
START signal
485
Slave address transmission
485
Data transfers
486
STOP signal
486
Repeated START signal
486
Arbitration procedure
487
Clock synchronization
487
Handshaking
488
Clock stretching
488
I2C divider and hold values
488
10-bit address
489
Master-transmitter addresses a slave-receiver
490
Master-receiver addresses a slave-transmitter
490
Address matching
491
Resets
491
Interrupts
492
Byte transfer interrupt
492
Address detect interrupt
492
Stop Detect Interrupt
492
Exit from low-power/stop modes
493
Arbitration lost interrupt
493
Programmable input glitch filter
493
Address matching wakeup
494
Features
497
Modes of operation
498
Block diagram
498
Baud rate generation
514
Transmitter functional description
514
Send break and queued idle
515
Receiver functional description
516
Data sampling technique
517
Receiver wakeup operation
518
Idle-line wakeup
518
Address-mark wakeup
518
Match address operation
519
Additional UART functions
519
8-bit, 9-bit and 10-bit data modes
519
Loop mode
520
Single-wire operation
520
Interrupts and status flags
521
Features
523
Modes of operation
523
GPIO signal descriptions
524
Detailed signal description
524
General-purpose input
532
General-purpose output
533
IOPORT
533
View document
NXP KL0x Reference guide
Type
Reference guide
Brand
NXP
Size
7.59 MB
Pages
658
Language
English
View document
NXP KL0x Reference guide
Type
Reference guide
Brand
NXP
Size
8.05 MB
Pages
696
Language
English
View document
NXP KL0x Reference guide
Type
Reference guide
Brand
NXP
Size
6.85 MB
Pages
535
Language
English
View document