NXP KL0x Reference guide

Type
Reference guide
KL02 Sub-Family Reference Manual
Supports: MKL02Z8VFG4(R), MKL02Z16VFG4(R),
MKL02Z32VFG4(R), MKL02Z16VFK4(R), MKL02Z32VFK4(R),
MKL02Z16VFM4(R), and MKL02Z32VFM4(R)
Document Number: KL02P32M48SF0RM
Rev 3.1, July 2013
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................25
1.1.1 Purpose...........................................................................................................................................................25
1.1.2 Audience........................................................................................................................................................25
1.2 Conventions..................................................................................................................................................................25
1.2.1 Numbering systems........................................................................................................................................25
1.2.2 Typographic notation.....................................................................................................................................26
1.2.3 Special terms..................................................................................................................................................26
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................27
2.2 Kinetis L series.............................................................................................................................................................27
2.3 KL02 sub-family introduction......................................................................................................................................30
2.4 Module functional categories........................................................................................................................................31
2.4.1 ARM Cortex-M0+ core modules...................................................................................................................31
2.4.2 System modules.............................................................................................................................................32
2.4.3 Memories and memory interfaces..................................................................................................................33
2.4.4 Clocks.............................................................................................................................................................33
2.4.5 Security and integrity modules......................................................................................................................33
2.4.6 Analog modules.............................................................................................................................................34
2.4.7 Timer modules...............................................................................................................................................34
2.4.8 Communication interfaces.............................................................................................................................34
2.4.9 Human-machine interfaces............................................................................................................................35
2.5 Orderable part numbers.................................................................................................................................................35
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................37
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3.2 Module to module interconnects...................................................................................................................................37
3.2.1 Interconnection overview...............................................................................................................................37
3.2.2 Analog reference options...............................................................................................................................38
3.3 Core modules................................................................................................................................................................39
3.3.1 ARM Cortex-M0+ core configuration...........................................................................................................39
3.3.2 Nested vectored interrupt controller (NVIC) configuration...........................................................................42
3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration..............................................................45
3.4 System modules............................................................................................................................................................46
3.4.1 SIM configuration..........................................................................................................................................46
3.4.2 System mode controller (SMC) configuration...............................................................................................47
3.4.3 PMC configuration.........................................................................................................................................48
3.4.4 MCM configuration.......................................................................................................................................48
3.4.5 Crossbar-light switch configuration...............................................................................................................49
3.4.6 Peripheral bridge configuration.....................................................................................................................51
3.4.7 Computer operating properly (COP) watchdog configuration......................................................................52
3.5 Clock modules..............................................................................................................................................................54
3.5.1 MCG configuration........................................................................................................................................54
3.5.2 OSC configuration.........................................................................................................................................55
3.6 Memories and memory interfaces.................................................................................................................................56
3.6.1 Flash memory configuration..........................................................................................................................56
3.6.2 Flash memory controller configuration..........................................................................................................58
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3.6.3 SRAM configuration......................................................................................................................................59
3.7 Analog...........................................................................................................................................................................61
3.7.1 12-bit SAR ADC configuration.....................................................................................................................61
3.7.2 CMP configuration.........................................................................................................................................64
3.8 Timers...........................................................................................................................................................................67
3.8.1 Timer/PWM module configuration................................................................................................................67
3.8.2 Low-power timer configuration.....................................................................................................................69
3.9 Communication interfaces............................................................................................................................................71
3.9.1 SPI configuration...........................................................................................................................................71
3.9.2 I2C configuration...........................................................................................................................................72
3.9.3 UART configuration......................................................................................................................................73
3.10 Human-machine interfaces (HMI)................................................................................................................................74
3.10.1 GPIO configuration........................................................................................................................................74
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................77
4.2 System memory map.....................................................................................................................................................77
4.3 Flash memory map........................................................................................................................................................78
4.3.1 Alternate non-volatile IRC user trim description...........................................................................................78
4.4 SRAM memory map.....................................................................................................................................................79
4.5 Bit Manipulation Engine...............................................................................................................................................79
4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................79
4.6.1 Read-after-write sequence and required serialization of memory operations................................................80
4.6.2 Peripheral bridge (AIPS-Lite) memory map..................................................................................................80
4.6.3 Modules restricted access in user mode.........................................................................................................84
4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................84
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................85
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5.2 Programming model......................................................................................................................................................85
5.3 High-level device clocking diagram.............................................................................................................................85
5.4 Clock definitions...........................................................................................................................................................86
5.4.1 Device clock summary...................................................................................................................................87
5.5 Internal clocking requirements.....................................................................................................................................88
5.5.1 Clock divider values after reset......................................................................................................................89
5.5.2 VLPR mode clocking.....................................................................................................................................89
5.6 Clock gating..................................................................................................................................................................90
5.7 Module clocks...............................................................................................................................................................90
5.7.1 PMC 1-kHz LPO clock..................................................................................................................................91
5.7.2 COP clocking.................................................................................................................................................91
5.7.3 LPTMR clocking............................................................................................................................................92
5.7.4 TPM clocking.................................................................................................................................................92
5.7.5 UART clocking..............................................................................................................................................93
Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................95
6.2 Reset..............................................................................................................................................................................95
6.2.1 Power-on reset (POR)....................................................................................................................................95
6.2.2 System reset sources......................................................................................................................................96
6.2.3 MCU resets....................................................................................................................................................99
6.2.4 RESET_b pin ................................................................................................................................................100
6.2.5 Debug resets...................................................................................................................................................100
6.3 Boot...............................................................................................................................................................................101
6.3.1 Boot sources...................................................................................................................................................101
6.3.2 FOPT boot options.........................................................................................................................................101
6.3.3 Boot sequence................................................................................................................................................103
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Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................105
7.2 Clocking modes............................................................................................................................................................105
7.2.1 Partial Stop.....................................................................................................................................................105
7.2.2 Compute Operation........................................................................................................................................106
7.2.3 Peripheral Doze..............................................................................................................................................107
7.2.4 Clock gating...................................................................................................................................................107
7.3 Power modes.................................................................................................................................................................108
7.4 Entering and exiting power modes...............................................................................................................................109
7.5 Module operation in low-power modes........................................................................................................................110
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................113
8.2 Flash security................................................................................................................................................................113
8.3 Security interactions with other modules......................................................................................................................113
8.3.1 Security interactions with Debug...................................................................................................................114
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................115
9.2 Debug port pin descriptions..........................................................................................................................................115
9.3 SWD status and control registers..................................................................................................................................116
9.3.1 MDM-AP Control Register............................................................................................................................117
9.3.2 MDM-AP Status Register..............................................................................................................................118
9.4 Debug resets..................................................................................................................................................................120
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................120
9.6 Debug in low-power modes..........................................................................................................................................121
9.7 Debug and security.......................................................................................................................................................122
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Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................123
10.2 Signal multiplexing integration....................................................................................................................................123
10.2.1 Port control and interrupt module features....................................................................................................124
10.2.2 Clock gating...................................................................................................................................................125
10.2.3 Signal multiplexing constraints......................................................................................................................125
10.3 Pinout............................................................................................................................................................................125
10.3.1 KL02 signal multiplexing and pin assignments.............................................................................................125
10.3.2 KL02 pinouts..................................................................................................................................................126
10.4 Module Signal Description Tables................................................................................................................................129
10.4.1 Core modules.................................................................................................................................................129
10.4.2 System modules.............................................................................................................................................130
10.4.3 Clock modules................................................................................................................................................130
10.4.4 Memories and memory interfaces..................................................................................................................130
10.4.5 Analog............................................................................................................................................................130
10.4.6 Timer Modules...............................................................................................................................................131
10.4.7 Communication interfaces.............................................................................................................................131
10.4.8 Human-machine interfaces (HMI).................................................................................................................132
Chapter 11
Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................133
11.2 Overview.......................................................................................................................................................................133
11.2.1 Features..........................................................................................................................................................133
11.2.2 Modes of operation........................................................................................................................................134
11.3 External signal description............................................................................................................................................134
11.4 Detailed signal description............................................................................................................................................135
11.5 Memory map and register definition.............................................................................................................................135
11.5.1 Pin Control Register n (PORTx_PCRn).........................................................................................................138
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11.5.2 Global Pin Control Low Register (PORTx_GPCLR)....................................................................................140
11.5.3 Global Pin Control High Register (PORTx_GPCHR)...................................................................................141
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)..............................................................................................141
11.6 Functional description...................................................................................................................................................142
11.6.1 Pin control......................................................................................................................................................142
11.6.2 Global pin control..........................................................................................................................................143
11.6.3 External interrupts..........................................................................................................................................143
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................145
12.1.1 Features..........................................................................................................................................................145
12.2 Memory map and register definition.............................................................................................................................145
12.2.1 System Options Register 2 (SIM_SOPT2)....................................................................................................146
12.2.2 System Options Register 4 (SIM_SOPT4)....................................................................................................147
12.2.3 System Options Register 5 (SIM_SOPT5)....................................................................................................149
12.2.4 System Options Register 7 (SIM_SOPT7)....................................................................................................150
12.2.5 System Device Identification Register (SIM_SDID).....................................................................................151
12.2.6 System Clock Gating Control Register 4 (SIM_SCGC4)..............................................................................153
12.2.7 System Clock Gating Control Register 5 (SIM_SCGC5)..............................................................................155
12.2.8 System Clock Gating Control Register 6 (SIM_SCGC6)..............................................................................156
12.2.9 System Clock Divider Register 1 (SIM_CLKDIV1).....................................................................................157
12.2.10 Flash Configuration Register 1 (SIM_FCFG1).............................................................................................159
12.2.11 Flash Configuration Register 2 (SIM_FCFG2).............................................................................................160
12.2.12 Unique Identification Register Mid-High (SIM_UIDMH)............................................................................161
12.2.13 Unique Identification Register Mid Low (SIM_UIDML).............................................................................161
12.2.14 Unique Identification Register Low (SIM_UIDL)........................................................................................162
12.2.15 COP Control Register (SIM_COPC).............................................................................................................162
12.2.16 Service COP Register (SIM_SRVCOP)........................................................................................................163
12.3 Functional description...................................................................................................................................................164
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Chapter 13
System Mode Controller (SMC)
13.1 Introduction...................................................................................................................................................................165
13.2 Modes of operation.......................................................................................................................................................165
13.3 Memory map and register descriptions.........................................................................................................................167
13.3.1 Power Mode Protection register (SMC_PMPROT).......................................................................................167
13.3.2 Power Mode Control register (SMC_PMCTRL)...........................................................................................169
13.3.3 Stop Control Register (SMC_STOPCTRL)...................................................................................................170
13.3.4 Power Mode Status register (SMC_PMSTAT).............................................................................................171
13.4 Functional description...................................................................................................................................................172
13.4.1 Power mode transitions..................................................................................................................................172
13.4.2 Power mode entry/exit sequencing................................................................................................................175
13.4.3 Run modes......................................................................................................................................................177
13.4.4 Wait modes....................................................................................................................................................178
13.4.5 Stop modes.....................................................................................................................................................179
13.4.6 Debug in low power modes...........................................................................................................................181
Chapter 14
Power Management Controller (PMC)
14.1 Introduction...................................................................................................................................................................183
14.2 Features.........................................................................................................................................................................183
14.3 Low-voltage detect (LVD) system................................................................................................................................183
14.3.1 LVD reset operation.......................................................................................................................................184
14.3.2 LVD interrupt operation.................................................................................................................................184
14.3.3 Low-voltage warning (LVW) interrupt operation.........................................................................................184
14.4 I/O retention..................................................................................................................................................................185
14.5 Memory map and register descriptions.........................................................................................................................185
14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)..........................................................186
14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)..........................................................187
14.5.3 Regulator Status And Control register (PMC_REGSC)................................................................................188
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Chapter 15
Reset Control Module (RCM)
15.1 Introduction...................................................................................................................................................................191
15.2 Reset memory map and register descriptions...............................................................................................................191
15.2.1 System Reset Status Register 0 (RCM_SRS0)..............................................................................................191
15.2.2 System Reset Status Register 1 (RCM_SRS1)..............................................................................................193
15.2.3 Reset Pin Filter Control register (RCM_RPFC)............................................................................................194
15.2.4 Reset Pin Filter Width register (RCM_RPFW).............................................................................................195
Chapter 16
Bit Manipulation Engine (BME)
16.1 Introduction...................................................................................................................................................................197
16.1.1 Overview........................................................................................................................................................198
16.1.2 Features..........................................................................................................................................................198
16.1.3 Modes of operation........................................................................................................................................199
16.2 External signal description............................................................................................................................................199
16.3 Memory map and register definition.............................................................................................................................200
16.4 Functional description...................................................................................................................................................200
16.4.1 BME decorated stores....................................................................................................................................200
16.4.2 BME decorated loads.....................................................................................................................................207
16.4.3 Additional details on decorated addresses and GPIO accesses......................................................................213
16.5 Application information................................................................................................................................................214
Chapter 17
Miscellaneous Control Module (MCM)
17.1 Introduction...................................................................................................................................................................217
17.1.1 Features..........................................................................................................................................................217
17.2 Memory map/register descriptions...............................................................................................................................217
17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)..................................................................218
17.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)..............................................................219
17.2.3 Platform Control Register (MCM_PLACR)..................................................................................................219
17.2.4 Compute Operation Control Register (MCM_CPO).....................................................................................222
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Chapter 18
Micro Trace Buffer (MTB)
18.1 Introduction...................................................................................................................................................................225
18.1.1 Overview........................................................................................................................................................225
18.1.2 Features..........................................................................................................................................................228
18.1.3 Modes of operation........................................................................................................................................229
18.2 External signal description............................................................................................................................................229
18.3 Memory map and register definition.............................................................................................................................230
18.3.1 MTB_RAM Memory Map.............................................................................................................................230
18.3.2 MTB_DWT Memory Map.............................................................................................................................242
18.3.3 System ROM Memory Map...........................................................................................................................253
Chapter 19
Crossbar Switch Lite (AXBS-Lite)
19.1 Introduction...................................................................................................................................................................259
19.1.1 Features..........................................................................................................................................................259
19.2 Memory Map / Register Definition...............................................................................................................................259
19.3 Functional Description..................................................................................................................................................260
19.3.1 General operation...........................................................................................................................................260
19.3.2 Arbitration......................................................................................................................................................261
19.4 Initialization/application information...........................................................................................................................262
Chapter 20
Peripheral Bridge (AIPS-Lite)
20.1 Introduction...................................................................................................................................................................263
20.1.1 Features..........................................................................................................................................................263
20.1.2 General operation...........................................................................................................................................263
20.2 Functional description...................................................................................................................................................264
20.2.1 Access support...............................................................................................................................................264
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Chapter 21
Multipurpose Clock Generator (MCG)
21.1 Introduction...................................................................................................................................................................265
21.1.1 Features..........................................................................................................................................................265
21.1.2 Modes of Operation.......................................................................................................................................268
21.2 External Signal Description..........................................................................................................................................268
21.3 Memory Map/Register Definition.................................................................................................................................268
21.3.1 MCG Control 1 Register (MCG_C1).............................................................................................................268
21.3.2 MCG Control 2 Register (MCG_C2).............................................................................................................269
21.3.3 MCG Control 3 Register (MCG_C3).............................................................................................................271
21.3.4 MCG Control 4 Register (MCG_C4).............................................................................................................271
21.3.5 MCG Control 6 Register (MCG_C6).............................................................................................................273
21.3.6 MCG Status Register (MCG_S)....................................................................................................................273
21.3.7 MCG Status and Control Register (MCG_SC)..............................................................................................274
21.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH)..............................................................276
21.3.9 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)................................................................276
21.4 Functional Description..................................................................................................................................................276
21.4.1 MCG mode state diagram..............................................................................................................................276
21.4.2 Low Power Bit Usage....................................................................................................................................280
21.4.3 MCG Internal Reference Clocks....................................................................................................................280
21.4.4 External Reference Clock..............................................................................................................................281
21.4.5 MCG Fixed frequency clock .........................................................................................................................281
21.4.6 MCG Auto TRIM (ATM)..............................................................................................................................281
21.5 Initialization / Application information........................................................................................................................283
21.5.1 MCG module initialization sequence.............................................................................................................283
21.5.2 Using a 32.768 kHz reference........................................................................................................................285
21.5.3 MCG mode switching....................................................................................................................................286
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Chapter 22
Oscillator (OSC)
22.1 Introduction...................................................................................................................................................................289
22.2 Features and Modes......................................................................................................................................................289
22.3 Block Diagram..............................................................................................................................................................290
22.4 OSC Signal Descriptions..............................................................................................................................................290
22.5 External Crystal / Resonator Connections....................................................................................................................291
22.6 External Clock Connections.........................................................................................................................................292
22.7 Memory Map/Register Definitions...............................................................................................................................293
22.7.1 OSC Memory Map/Register Definition.........................................................................................................293
22.8 Functional Description..................................................................................................................................................294
22.8.1 OSC Module States........................................................................................................................................294
22.8.2 OSC Module Modes.......................................................................................................................................296
22.8.3 Counter...........................................................................................................................................................297
22.8.4 Reference Clock Pin Requirements...............................................................................................................297
22.9 Reset..............................................................................................................................................................................298
22.10 Low Power Modes Operation.......................................................................................................................................298
22.11 Interrupts.......................................................................................................................................................................298
Chapter 23
Flash Memory Controller (FMC)
23.1 Introduction...................................................................................................................................................................299
23.1.1 Overview........................................................................................................................................................299
23.1.2 Features..........................................................................................................................................................299
23.2 Modes of operation.......................................................................................................................................................300
23.3 External signal description............................................................................................................................................300
23.4 Memory map and register descriptions.........................................................................................................................300
23.5 Functional description...................................................................................................................................................300
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Chapter 24
Flash Memory Module (FTFA)
24.1 Introduction...................................................................................................................................................................303
24.1.1 Features..........................................................................................................................................................304
24.1.2 Block Diagram...............................................................................................................................................304
24.1.3 Glossary.........................................................................................................................................................305
24.2 External Signal Description..........................................................................................................................................306
24.3 Memory Map and Registers..........................................................................................................................................306
24.3.1 Flash Configuration Field Description...........................................................................................................306
24.3.2 Program Flash IFR Map.................................................................................................................................307
24.3.3 Register Descriptions.....................................................................................................................................308
24.4 Functional Description..................................................................................................................................................317
24.4.1 Flash Protection..............................................................................................................................................317
24.4.2 Interrupts........................................................................................................................................................317
24.4.3 Flash Operation in Low-Power Modes..........................................................................................................318
24.4.4 Functional Modes of Operation.....................................................................................................................319
24.4.5 Flash Reads and Ignored Writes....................................................................................................................319
24.4.6 Read While Write (RWW).............................................................................................................................319
24.4.7 Flash Program and Erase................................................................................................................................319
24.4.8 Flash Command Operations...........................................................................................................................319
24.4.9 Margin Read Commands...............................................................................................................................324
24.4.10 Flash Command Description..........................................................................................................................325
24.4.11 Security..........................................................................................................................................................338
24.4.12 Reset Sequence..............................................................................................................................................340
Chapter 25
Analog-to-Digital Converter (ADC)
25.1 Introduction...................................................................................................................................................................341
25.1.1 Features..........................................................................................................................................................341
25.1.2 Block diagram................................................................................................................................................342
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25.2 ADC signal descriptions...............................................................................................................................................343
25.2.1 Analog Power (VDDA).................................................................................................................................344
25.2.2 Analog Ground (VSSA).................................................................................................................................344
25.2.3 Analog Channel Inputs (ADx).......................................................................................................................344
25.3 Memory map and register definitions...........................................................................................................................344
25.3.1 ADC Status and Control Registers 1 (ADCx_SC1n).....................................................................................345
25.3.2 ADC Configuration Register 1 (ADCx_CFG1).............................................................................................349
25.3.3 ADC Configuration Register 2 (ADCx_CFG2).............................................................................................350
25.3.4 ADC Data Result Register (ADCx_Rn).........................................................................................................351
25.3.5 Compare Value Registers (ADCx_CVn).......................................................................................................352
25.3.6 Status and Control Register 2 (ADCx_SC2)..................................................................................................353
25.3.7 Status and Control Register 3 (ADCx_SC3)..................................................................................................355
25.3.8 ADC Offset Correction Register (ADCx_OFS).............................................................................................357
25.3.9 ADC Plus-Side Gain Register (ADCx_PG)...................................................................................................357
25.3.10 ADC Plus-Side General Calibration Value Register (ADCx_CLPD)...........................................................358
25.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)............................................................358
25.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)............................................................359
25.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)............................................................359
25.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)............................................................360
25.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)............................................................360
25.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)............................................................361
25.4 Functional description...................................................................................................................................................361
25.4.1 Clock select and divide control......................................................................................................................362
25.4.2 Voltage reference selection............................................................................................................................362
25.4.3 Hardware trigger and channel selects............................................................................................................363
25.4.4 Conversion control.........................................................................................................................................364
25.4.5 Automatic compare function..........................................................................................................................370
25.4.6 Calibration function.......................................................................................................................................372
25.4.7 User-defined offset function..........................................................................................................................373
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25.4.8 Temperature sensor........................................................................................................................................374
25.4.9 MCU wait mode operation.............................................................................................................................375
25.4.10 MCU Normal Stop mode operation...............................................................................................................375
25.4.11 MCU Low-Power Stop mode operation........................................................................................................376
25.5 Initialization information..............................................................................................................................................377
25.5.1 ADC module initialization example..............................................................................................................377
25.6 Application information................................................................................................................................................379
25.6.1 External pins and routing...............................................................................................................................379
25.6.2 Sources of error..............................................................................................................................................381
Chapter 26
Comparator (CMP)
26.1 Introduction...................................................................................................................................................................385
26.2 CMP features................................................................................................................................................................385
26.3 6-bit DAC key features.................................................................................................................................................386
26.4 ANMUX key features...................................................................................................................................................386
26.5 CMP, DAC and ANMUX diagram...............................................................................................................................387
26.6 CMP block diagram......................................................................................................................................................388
26.7 Memory map/register definitions..................................................................................................................................389
26.7.1 CMP Control Register 0 (CMPx_CR0).........................................................................................................389
26.7.2 CMP Control Register 1 (CMPx_CR1).........................................................................................................390
26.7.3 CMP Filter Period Register (CMPx_FPR).....................................................................................................392
26.7.4 CMP Status and Control Register (CMPx_SCR)...........................................................................................392
26.7.5 DAC Control Register (CMPx_DACCR)......................................................................................................393
26.7.6 MUX Control Register (CMPx_MUXCR)....................................................................................................394
26.8 Functional description...................................................................................................................................................395
26.8.1 CMP functional modes...................................................................................................................................395
26.8.2 Power modes..................................................................................................................................................404
26.8.3 Startup and operation.....................................................................................................................................405
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26.8.4 Low-pass filter...............................................................................................................................................405
26.9 CMP interrupts..............................................................................................................................................................408
26.10 Digital-to-analog converter...........................................................................................................................................408
26.11 DAC functional description..........................................................................................................................................409
26.11.1 Voltage reference source select......................................................................................................................409
26.12 DAC resets....................................................................................................................................................................409
26.13 DAC clocks...................................................................................................................................................................409
26.14 DAC interrupts..............................................................................................................................................................410
26.15 CMP Trigger Mode.......................................................................................................................................................410
Chapter 27
Timer/PWM Module (TPM)
27.1 Introduction...................................................................................................................................................................411
27.1.1 TPM Philosophy............................................................................................................................................411
27.1.2 Features..........................................................................................................................................................411
27.1.3 Modes of Operation.......................................................................................................................................412
27.1.4 Block Diagram...............................................................................................................................................412
27.2 TPM Signal Descriptions..............................................................................................................................................413
27.2.1 TPM_EXTCLK — TPM External Clock......................................................................................................413
27.2.2 TPM_CHn — TPM Channel (n) I/O Pin.......................................................................................................414
27.3 Memory Map and Register Definition..........................................................................................................................414
27.3.1 Status and Control (TPMx_SC).....................................................................................................................415
27.3.2 Counter (TPMx_CNT)...................................................................................................................................416
27.3.3 Modulo (TPMx_MOD)..................................................................................................................................417
27.3.4 Channel (n) Status and Control (TPMx_CnSC).............................................................................................418
27.3.5 Channel (n) Value (TPMx_CnV)...................................................................................................................419
27.3.6 Capture and Compare Status (TPMx_STATUS)...........................................................................................420
27.3.7 Configuration (TPMx_CONF).......................................................................................................................422
KL02 Sub-Family Reference Manual, Rev. 3.1, July 2013
18 Freescale Semiconductor, Inc.
Section number Title Page
27.4 Functional Description..................................................................................................................................................423
27.4.1 Clock Domains...............................................................................................................................................424
27.4.2 Prescaler.........................................................................................................................................................424
27.4.3 Counter...........................................................................................................................................................425
27.4.4 Input Capture Mode.......................................................................................................................................427
27.4.5 Output Compare Mode...................................................................................................................................428
27.4.6 Edge-Aligned PWM (EPWM) Mode.............................................................................................................429
27.4.7 Center-Aligned PWM (CPWM) Mode..........................................................................................................431
27.4.8 Registers Updated from Write Buffers..........................................................................................................433
27.4.9 Reset Overview..............................................................................................................................................433
27.4.10 TPM Interrupts...............................................................................................................................................434
Chapter 28
Low-Power Timer (LPTMR)
28.1 Introduction...................................................................................................................................................................435
28.1.1 Features..........................................................................................................................................................435
28.1.2 Modes of operation........................................................................................................................................435
28.2 LPTMR signal descriptions..........................................................................................................................................436
28.2.1 Detailed signal descriptions...........................................................................................................................436
28.3 Memory map and register definition.............................................................................................................................436
28.3.1 Low Power Timer Control Status Register (LPTMRx_CSR)........................................................................437
28.3.2 Low Power Timer Prescale Register (LPTMRx_PSR)..................................................................................438
28.3.3 Low Power Timer Compare Register (LPTMRx_CMR)...............................................................................440
28.3.4 Low Power Timer Counter Register (LPTMRx_CNR).................................................................................440
28.4 Functional description...................................................................................................................................................441
28.4.1 LPTMR power and reset................................................................................................................................441
28.4.2 LPTMR clocking............................................................................................................................................441
28.4.3 LPTMR prescaler/glitch filter........................................................................................................................441
28.4.4 LPTMR compare............................................................................................................................................443
28.4.5 LPTMR counter.............................................................................................................................................443
KL02 Sub-Family Reference Manual, Rev. 3.1, July 2013
Freescale Semiconductor, Inc. 19
Section number Title Page
28.4.6 LPTMR hardware trigger...............................................................................................................................444
28.4.7 LPTMR interrupt............................................................................................................................................444
Chapter 29
Serial Peripheral Interface (SPI)
29.1 Introduction...................................................................................................................................................................445
29.1.1 Features..........................................................................................................................................................445
29.1.2 Modes of operation........................................................................................................................................446
29.1.3 Block diagrams..............................................................................................................................................446
29.2 External signal description............................................................................................................................................449
29.2.1 SPSCK — SPI Serial Clock...........................................................................................................................449
29.2.2 MOSI — Master Data Out, Slave Data In.....................................................................................................449
29.2.3 MISO — Master Data In, Slave Data Out.....................................................................................................449
29.2.4 SS — Slave Select..........................................................................................................................................449
29.3 Memory Map and Register Descriptions......................................................................................................................450
29.3.1 SPI Control Register 1 (SPIx_C1).................................................................................................................450
29.3.2 SPI Control Register 2 (SPIx_C2).................................................................................................................452
29.3.3 SPI Baud Rate Register (SPIx_BR)...............................................................................................................453
29.3.4 SPI Status Register (SPIx_S).........................................................................................................................454
29.3.5 SPI Data Register (SPIx_D)...........................................................................................................................455
29.3.6 SPI Match Register (SPIx_M)........................................................................................................................456
29.4 Functional description...................................................................................................................................................457
29.4.1 General...........................................................................................................................................................457
29.4.2 Master mode...................................................................................................................................................457
29.4.3 Slave mode.....................................................................................................................................................459
29.4.4 SPI clock formats...........................................................................................................................................460
29.4.5 SPI baud rate generation................................................................................................................................463
KL02 Sub-Family Reference Manual, Rev. 3.1, July 2013
20 Freescale Semiconductor, Inc.
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NXP KL0x Reference guide

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Reference guide

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