NXP KL3x Reference guide

Type
Reference guide
KL36 Sub-Family Reference Manual
Supports: MKL36Z64VLH4, MKL36Z128VLH4, MKL36Z256VLH4,
MKL36Z256VMP4, MKL36Z64VLL4, MKL36Z128VLL4,
MKL36Z256VLL4, MKL36Z128VMC4, MKL36Z256VMC4
Document Number: KL36P121M48SF4RM
Rev. 3, July 2013
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Contents
Section number Title Page
Chapter 1
About This Document
1.1 Overview.......................................................................................................................................................................35
1.1.1 Purpose.........................................................................................................................................................35
1.1.2 Audience......................................................................................................................................................35
1.2 Conventions..................................................................................................................................................................35
1.2.1 Numbering systems......................................................................................................................................35
1.2.2 Typographic notation...................................................................................................................................36
1.2.3 Special terms................................................................................................................................................36
Chapter 2
Introduction
2.1 Overview.......................................................................................................................................................................37
2.1.1 Kinetis L series.............................................................................................................................................37
2.1.2 KL36 sub-family introduction.....................................................................................................................40
2.2 Module functional categories........................................................................................................................................41
2.2.1 ARM Cortex-M0+ core modules.................................................................................................................42
2.2.2 System modules...........................................................................................................................................42
2.2.3 Memories and memory interfaces................................................................................................................43
2.2.4 Clocks...........................................................................................................................................................43
2.2.5 Security and integrity modules....................................................................................................................44
2.2.6 Analog modules...........................................................................................................................................44
2.2.7 Timer modules.............................................................................................................................................44
2.2.8 Communication interfaces...........................................................................................................................45
2.2.9 Human-machine interfaces..........................................................................................................................46
2.3 Orderable part numbers.................................................................................................................................................46
Chapter 3
Chip Configuration
3.1 Introduction...................................................................................................................................................................47
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3.2 Module to module interconnects...................................................................................................................................47
3.2.1 Interconnection overview.............................................................................................................................47
3.2.2 Analog reference options.............................................................................................................................49
3.3 Core modules................................................................................................................................................................49
3.3.1 ARM Cortex-M0+ core configuration.........................................................................................................50
3.3.2 Nested vectored interrupt controller (NVIC) configuration.........................................................................52
3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............................................................56
3.4 System modules............................................................................................................................................................57
3.4.1 SIM configuration........................................................................................................................................57
3.4.2 System mode controller (SMC) configuration.............................................................................................58
3.4.3 PMC configuration.......................................................................................................................................58
3.4.4 Low-Leakage Wake-up Unit (LLWU) Configuration.................................................................................59
3.4.5 MCM configuration.....................................................................................................................................61
3.4.6 Crossbar-light switch configuration.............................................................................................................62
3.4.7 Peripheral bridge configuration...................................................................................................................63
3.4.8 DMA request multiplexer configuration......................................................................................................64
3.4.9 DMA Controller Configuration...................................................................................................................67
3.4.10 Computer operating properly (COP) watchdog configuration....................................................................67
3.5 Clock modules..............................................................................................................................................................70
3.5.1 MCG configuration......................................................................................................................................70
3.5.2 OSC configuration.......................................................................................................................................70
3.6 Memories and memory interfaces.................................................................................................................................71
3.6.1 Flash memory configuration........................................................................................................................71
3.6.2 Flash memory controller configuration........................................................................................................74
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3.6.3 SRAM configuration....................................................................................................................................74
3.6.4 System Register File Configuration.............................................................................................................77
3.7 Analog...........................................................................................................................................................................77
3.7.1 16-bit SAR ADC configuration...................................................................................................................78
3.7.2 CMP configuration.......................................................................................................................................81
3.7.3 12-bit DAC Configuration...........................................................................................................................83
3.8 Timers...........................................................................................................................................................................85
3.8.1 Timer/PWM module configuration..............................................................................................................85
3.8.2 PIT Configuration........................................................................................................................................87
3.8.3 Low-power timer configuration...................................................................................................................89
3.8.4 RTC configuration.......................................................................................................................................90
3.9 Communication interfaces............................................................................................................................................92
3.9.1 SPI configuration.........................................................................................................................................92
3.9.2 I2C configuration.........................................................................................................................................93
3.9.3 UART configuration....................................................................................................................................94
3.9.4 I2S configuration..........................................................................................................................................95
3.10 Human-machine interfaces (HMI)................................................................................................................................98
3.10.1 GPIO configuration......................................................................................................................................98
3.10.2 TSI Configuration........................................................................................................................................101
3.10.3 Segment LCD Configuration.......................................................................................................................102
Chapter 4
Memory Map
4.1 Introduction...................................................................................................................................................................105
4.2 System memory map.....................................................................................................................................................105
4.3 Flash memory map........................................................................................................................................................106
4.3.1 Alternate non-volatile IRC user trim description.........................................................................................106
4.4 SRAM memory map.....................................................................................................................................................107
4.5 Bit Manipulation Engine...............................................................................................................................................107
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4.6 Peripheral bridge (AIPS-Lite) memory map.................................................................................................................108
4.6.1 Read-after-write sequence and required serialization of memory operations..............................................108
4.6.2 Peripheral bridge (AIPS-Lite) memory map................................................................................................109
4.6.3 Modules restricted access in user mode.......................................................................................................112
4.7 Private Peripheral Bus (PPB) memory map..................................................................................................................112
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................115
5.2 Programming model......................................................................................................................................................115
5.3 High-level device clocking diagram.............................................................................................................................115
5.4 Clock definitions...........................................................................................................................................................116
5.4.1 Device clock summary.................................................................................................................................117
5.5 Internal clocking requirements.....................................................................................................................................119
5.5.1 Clock divider values after reset....................................................................................................................120
5.5.2 VLPR mode clocking...................................................................................................................................120
5.6 Clock gating..................................................................................................................................................................121
5.7 Module clocks...............................................................................................................................................................121
5.7.1 PMC 1-kHz LPO clock................................................................................................................................122
5.7.2 COP clocking...............................................................................................................................................122
5.7.3 RTC clocking...............................................................................................................................................123
5.7.4 LPTMR clocking..........................................................................................................................................123
5.7.5 TPM clocking...............................................................................................................................................124
5.7.6 SPI clocking.................................................................................................................................................124
5.7.7 I2C clocking.................................................................................................................................................125
5.7.8 UART clocking............................................................................................................................................125
5.7.9 I2S/SAI clocking..........................................................................................................................................125
5.7.10 SLCD clocking.............................................................................................................................................126
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Chapter 6
Reset and Boot
6.1 Introduction...................................................................................................................................................................129
6.2 Reset..............................................................................................................................................................................129
6.2.1 Power-on reset (POR)..................................................................................................................................130
6.2.2 System reset sources....................................................................................................................................130
6.2.3 MCU resets..................................................................................................................................................133
6.2.4 RESET_b pin ..............................................................................................................................................135
6.2.5 Debug resets.................................................................................................................................................135
6.3 Boot...............................................................................................................................................................................136
6.3.1 Boot sources.................................................................................................................................................136
6.3.2 FOPT boot options.......................................................................................................................................136
6.3.3 Boot sequence..............................................................................................................................................137
Chapter 7
Power Management
7.1 Introduction...................................................................................................................................................................139
7.2 Clocking modes............................................................................................................................................................139
7.2.1 Partial Stop...................................................................................................................................................139
7.2.2 DMA Wakeup..............................................................................................................................................140
7.2.3 Compute Operation......................................................................................................................................141
7.2.4 Peripheral Doze............................................................................................................................................142
7.2.5 Clock gating.................................................................................................................................................143
7.3 Power modes.................................................................................................................................................................143
7.4 Entering and exiting power modes...............................................................................................................................145
7.5 Module operation in low-power modes........................................................................................................................146
Chapter 8
Security
8.1 Introduction...................................................................................................................................................................151
8.1.1 Flash security...............................................................................................................................................151
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8.1.2 Security interactions with other modules.....................................................................................................151
Chapter 9
Debug
9.1 Introduction...................................................................................................................................................................153
9.2 Debug port pin descriptions..........................................................................................................................................153
9.3 SWD status and control registers..................................................................................................................................154
9.3.1 MDM-AP Control Register..........................................................................................................................155
9.3.2 MDM-AP Status Register............................................................................................................................156
9.4 Debug resets..................................................................................................................................................................158
9.5 Micro Trace Buffer (MTB)...........................................................................................................................................159
9.6 Debug in low-power modes..........................................................................................................................................159
9.7 Debug and security.......................................................................................................................................................160
Chapter 10
Signal Multiplexing and Signal Descriptions
10.1 Introduction...................................................................................................................................................................161
10.2 Signal multiplexing integration....................................................................................................................................161
10.2.1 Port control and interrupt module features..................................................................................................162
10.2.2 Clock gating.................................................................................................................................................163
10.2.3 Signal multiplexing constraints....................................................................................................................163
10.3 Pinout............................................................................................................................................................................163
10.3.1 KL36 Signal Multiplexing and Pin Assignments........................................................................................163
10.3.2 KL36 pinouts................................................................................................................................................167
10.4 Module Signal Description Tables................................................................................................................................171
10.4.1 Core modules...............................................................................................................................................171
10.4.2 System modules...........................................................................................................................................172
10.4.3 Clock modules..............................................................................................................................................172
10.4.4 Memories and memory interfaces................................................................................................................172
10.4.5 Analog..........................................................................................................................................................172
10.4.6 Timer Modules.............................................................................................................................................173
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10.4.7 Communication interfaces...........................................................................................................................174
10.4.8 Human-machine interfaces (HMI)...............................................................................................................176
Chapter 11
Port Control and Interrupts (PORT)
11.1 Introduction...................................................................................................................................................................177
11.2 Overview.......................................................................................................................................................................177
11.2.1 Features........................................................................................................................................................177
11.2.2 Modes of operation......................................................................................................................................178
11.3 External signal description............................................................................................................................................179
11.4 Detailed signal description............................................................................................................................................179
11.5 Memory map and register definition.............................................................................................................................179
11.5.1 Pin Control Register n (PORTx_PCRn).......................................................................................................185
11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................................................................................187
11.5.3 Global Pin Control High Register (PORTx_GPCHR).................................................................................188
11.5.4 Interrupt Status Flag Register (PORTx_ISFR)............................................................................................188
11.6 Functional description...................................................................................................................................................189
11.6.1 Pin control....................................................................................................................................................189
11.6.2 Global pin control........................................................................................................................................190
11.6.3 External interrupts........................................................................................................................................190
Chapter 12
System Integration Module (SIM)
12.1 Introduction...................................................................................................................................................................193
12.1.1 Features........................................................................................................................................................193
12.2 Memory map and register definition.............................................................................................................................193
12.2.1 System Options Register 1 (SIM_SOPT1)..................................................................................................195
12.2.2 SOPT1 Configuration Register (SIM_SOPT1CFG)....................................................................................195
12.2.3 System Options Register 2 (SIM_SOPT2)..................................................................................................196
12.2.4 System Options Register 4 (SIM_SOPT4)..................................................................................................198
12.2.5 System Options Register 5 (SIM_SOPT5)..................................................................................................199
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12.2.6 System Options Register 7 (SIM_SOPT7)..................................................................................................201
12.2.7 System Device Identification Register (SIM_SDID)...................................................................................202
12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4)............................................................................204
12.2.9 System Clock Gating Control Register 5 (SIM_SCGC5)............................................................................206
12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6)............................................................................208
12.2.11 System Clock Gating Control Register 7 (SIM_SCGC7)............................................................................210
12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1)...................................................................................210
12.2.13 Flash Configuration Register 1 (SIM_FCFG1)...........................................................................................212
12.2.14 Flash Configuration Register 2 (SIM_FCFG2)...........................................................................................213
12.2.15 Unique Identification Register Mid-High (SIM_UIDMH)..........................................................................214
12.2.16 Unique Identification Register Mid Low (SIM_UIDML)...........................................................................214
12.2.17 Unique Identification Register Low (SIM_UIDL)......................................................................................215
12.2.18 COP Control Register (SIM_COPC)...........................................................................................................215
12.2.19 Service COP Register (SIM_SRVCOP)......................................................................................................216
12.3 Functional description...................................................................................................................................................217
Chapter 13
System Mode Controller (SMC)
13.1 Introduction...................................................................................................................................................................219
13.2 Modes of operation.......................................................................................................................................................219
13.3 Memory map and register descriptions.........................................................................................................................221
13.3.1 Power Mode Protection register (SMC_PMPROT).....................................................................................222
13.3.2 Power Mode Control register (SMC_PMCTRL).........................................................................................223
13.3.3 Stop Control Register (SMC_STOPCTRL).................................................................................................224
13.3.4 Power Mode Status register (SMC_PMSTAT)...........................................................................................226
13.4 Functional description...................................................................................................................................................226
13.4.1 Power mode transitions................................................................................................................................226
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13.4.2 Power mode entry/exit sequencing..............................................................................................................229
13.4.3 Run modes....................................................................................................................................................232
13.4.4 Wait modes..................................................................................................................................................233
13.4.5 Stop modes...................................................................................................................................................234
13.4.6 Debug in low power modes.........................................................................................................................237
Chapter 14
Power Management Controller (PMC)
14.1 Introduction...................................................................................................................................................................239
14.2 Features.........................................................................................................................................................................239
14.3 Low-voltage detect (LVD) system................................................................................................................................239
14.3.1 LVD reset operation.....................................................................................................................................240
14.3.2 LVD interrupt operation...............................................................................................................................240
14.3.3 Low-voltage warning (LVW) interrupt operation.......................................................................................240
14.4 I/O retention..................................................................................................................................................................241
14.5 Memory map and register descriptions.........................................................................................................................241
14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)........................................................242
14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)........................................................243
14.5.3 Regulator Status And Control register (PMC_REGSC)..............................................................................244
Chapter 15
Low-Leakage Wakeup Unit (LLWU)
15.1 Introduction...................................................................................................................................................................247
15.1.1 Features........................................................................................................................................................247
15.1.2 Modes of operation......................................................................................................................................248
15.1.3 Block diagram..............................................................................................................................................249
15.2 LLWU signal descriptions............................................................................................................................................249
15.3 Memory map/register definition...................................................................................................................................250
15.3.1 LLWU Pin Enable 1 register (LLWU_PE1)................................................................................................251
15.3.2 LLWU Pin Enable 2 register (LLWU_PE2)................................................................................................252
15.3.3 LLWU Pin Enable 3 register (LLWU_PE3)................................................................................................253
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15.3.4 LLWU Pin Enable 4 register (LLWU_PE4)................................................................................................254
15.3.5 LLWU Module Enable register (LLWU_ME)............................................................................................255
15.3.6 LLWU Flag 1 register (LLWU_F1).............................................................................................................257
15.3.7 LLWU Flag 2 register (LLWU_F2).............................................................................................................258
15.3.8 LLWU Flag 3 register (LLWU_F3).............................................................................................................260
15.3.9 LLWU Pin Filter 1 register (LLWU_FILT1)..............................................................................................262
15.3.10 LLWU Pin Filter 2 register (LLWU_FILT2)..............................................................................................263
15.4 Functional description...................................................................................................................................................264
15.4.1 LLS mode.....................................................................................................................................................265
15.4.2 VLLS modes................................................................................................................................................265
15.4.3 Initialization.................................................................................................................................................265
Chapter 16
Reset Control Module (RCM)
16.1 Introduction...................................................................................................................................................................267
16.2 Reset memory map and register descriptions...............................................................................................................267
16.2.1 System Reset Status Register 0 (RCM_SRS0)............................................................................................268
16.2.2 System Reset Status Register 1 (RCM_SRS1)............................................................................................269
16.2.3 Reset Pin Filter Control register (RCM_RPFC)..........................................................................................270
16.2.4 Reset Pin Filter Width register (RCM_RPFW)...........................................................................................271
Chapter 17
Bit Manipulation Engine (BME)
17.1 Introduction...................................................................................................................................................................273
17.1.1 Overview......................................................................................................................................................274
17.1.2 Features........................................................................................................................................................274
17.1.3 Modes of operation......................................................................................................................................275
17.2 Memory map and register definition.............................................................................................................................275
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17.3 Functional description...................................................................................................................................................275
17.3.1 BME decorated stores..................................................................................................................................276
17.3.2 BME decorated loads...................................................................................................................................283
17.3.3 Additional details on decorated addresses and GPIO accesses....................................................................289
17.4 Application information................................................................................................................................................290
Chapter 18
Miscellaneous Control Module (MCM)
18.1 Introduction...................................................................................................................................................................293
18.1.1 Features........................................................................................................................................................293
18.2 Memory map/register descriptions...............................................................................................................................293
18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)................................................................294
18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC)............................................................295
18.2.3 Platform Control Register (MCM_PLACR)................................................................................................295
18.2.4 Compute Operation Control Register (MCM_CPO)...................................................................................298
Chapter 19
Micro Trace Buffer (MTB)
19.1 Introduction...................................................................................................................................................................301
19.1.1 Overview......................................................................................................................................................301
19.1.2 Features........................................................................................................................................................304
19.1.3 Modes of operation......................................................................................................................................305
19.2 External signal description............................................................................................................................................305
19.3 Memory map and register definition.............................................................................................................................306
19.3.1 MTB_RAM Memory Map...........................................................................................................................306
19.3.2 MTB_DWT Memory Map...........................................................................................................................319
19.3.3 System ROM Memory Map.........................................................................................................................329
Chapter 20
Crossbar Switch Lite (AXBS-Lite)
20.1 Introduction...................................................................................................................................................................335
20.1.1 Features........................................................................................................................................................335
20.2 Memory Map / Register Definition...............................................................................................................................335
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20.3 Functional Description..................................................................................................................................................336
20.3.1 General operation.........................................................................................................................................336
20.3.2 Arbitration....................................................................................................................................................337
20.4 Initialization/application information...........................................................................................................................338
Chapter 21
Peripheral Bridge (AIPS-Lite)
21.1 Introduction...................................................................................................................................................................339
21.1.1 Features........................................................................................................................................................339
21.1.2 General operation.........................................................................................................................................339
21.2 Functional description...................................................................................................................................................340
21.2.1 Access support.............................................................................................................................................340
Chapter 22
Direct Memory Access Multiplexer (DMAMUX)
22.1 Introduction...................................................................................................................................................................341
22.1.1 Overview......................................................................................................................................................341
22.1.2 Features........................................................................................................................................................342
22.1.3 Modes of operation......................................................................................................................................342
22.2 External signal description............................................................................................................................................343
22.3 Memory map/register definition...................................................................................................................................343
22.3.1 Channel Configuration register (DMAMUXx_CHCFGn)..........................................................................344
22.4 Functional description...................................................................................................................................................345
22.4.1 DMA channels with periodic triggering capability......................................................................................345
22.4.2 DMA channels with no triggering capability...............................................................................................347
22.4.3 Always-enabled DMA sources....................................................................................................................347
22.5 Initialization/application information...........................................................................................................................349
22.5.1 Reset.............................................................................................................................................................349
22.5.2 Enabling and configuring sources................................................................................................................349
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Chapter 23
DMA Controller Module
23.1 Introduction...................................................................................................................................................................353
23.1.1 Overview......................................................................................................................................................353
23.1.2 Features........................................................................................................................................................354
23.2 DMA Transfer Overview..............................................................................................................................................355
23.3 Memory Map/Register Definition.................................................................................................................................356
23.3.1 Source Address Register (DMA_SARn).....................................................................................................357
23.3.2 Destination Address Register (DMA_DARn).............................................................................................358
23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn).............................................................359
23.3.4 DMA Control Register (DMA_DCRn)........................................................................................................361
23.4 Functional Description..................................................................................................................................................365
23.4.1 Transfer Requests (Cycle-Steal and Continuous Modes)............................................................................365
23.4.2 Channel Initialization and Startup................................................................................................................365
23.4.3 Dual-Address Data Transfer Mode..............................................................................................................367
23.4.4 Advanced Data Transfer Controls: Auto-Alignment...................................................................................368
23.4.5 Termination..................................................................................................................................................369
Chapter 24
Multipurpose Clock Generator (MCG)
24.1 Introduction...................................................................................................................................................................371
24.1.1 Features........................................................................................................................................................371
24.1.2 Modes of Operation.....................................................................................................................................373
24.2 External Signal Description..........................................................................................................................................373
24.3 Memory Map/Register Definition.................................................................................................................................373
24.3.1 MCG Control 1 Register (MCG_C1)...........................................................................................................374
24.3.2 MCG Control 2 Register (MCG_C2)...........................................................................................................375
24.3.3 MCG Control 3 Register (MCG_C3)...........................................................................................................377
24.3.4 MCG Control 4 Register (MCG_C4)...........................................................................................................377
24.3.5 MCG Control 5 Register (MCG_C5)...........................................................................................................379
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24.3.6 MCG Control 6 Register (MCG_C6)...........................................................................................................380
24.3.7 MCG Status Register (MCG_S)..................................................................................................................381
24.3.8 MCG Status and Control Register (MCG_SC)............................................................................................383
24.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH)............................................................384
24.3.10 MCG Auto Trim Compare Value Low Register (MCG_ATCVL)..............................................................384
24.3.11 MCG Control 7 Register (MCG_C7)...........................................................................................................385
24.3.12 MCG Control 8 Register (MCG_C8)...........................................................................................................385
24.3.13 MCG Control 9 Register (MCG_C9)...........................................................................................................386
24.3.14 MCG Control 10 Register (MCG_C10).......................................................................................................386
24.4 Functional description...................................................................................................................................................387
24.4.1 MCG mode state diagram............................................................................................................................387
24.4.2 Low Power Bit Usage..................................................................................................................................392
24.4.3 MCG Internal Reference Clocks..................................................................................................................392
24.4.4 External Reference Clock............................................................................................................................393
24.4.5 MCG Fixed frequency clock .......................................................................................................................393
24.4.6 MCG PLL clock ..........................................................................................................................................393
24.4.7 MCG Auto TRIM (ATM)............................................................................................................................394
24.5 Initialization / Application information........................................................................................................................395
24.5.1 MCG module initialization sequence...........................................................................................................395
24.5.2 Using a 32.768 kHz reference......................................................................................................................397
24.5.3 MCG mode switching..................................................................................................................................398
Chapter 25
Oscillator (OSC)
25.1 Introduction...................................................................................................................................................................407
25.2 Features and Modes......................................................................................................................................................407
25.3 Block Diagram..............................................................................................................................................................408
25.4 OSC Signal Descriptions..............................................................................................................................................408
25.5 External Crystal / Resonator Connections....................................................................................................................409
25.6 External Clock Connections.........................................................................................................................................410
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25.7 Memory Map/Register Definitions...............................................................................................................................411
25.7.1 OSC Memory Map/Register Definition.......................................................................................................411
25.8 Functional Description..................................................................................................................................................412
25.8.1 OSC Module States......................................................................................................................................412
25.8.2 OSC Module Modes.....................................................................................................................................414
25.8.3 Counter.........................................................................................................................................................416
25.8.4 Reference Clock Pin Requirements.............................................................................................................416
25.9 Reset..............................................................................................................................................................................416
25.10 Low Power Modes Operation.......................................................................................................................................417
25.11 Interrupts.......................................................................................................................................................................417
Chapter 26
Flash Memory Controller (FMC)
26.1 Introduction...................................................................................................................................................................419
26.1.1 Overview......................................................................................................................................................419
26.1.2 Features........................................................................................................................................................419
26.2 Modes of operation.......................................................................................................................................................420
26.3 External signal description............................................................................................................................................420
26.4 Memory map and register descriptions.........................................................................................................................420
26.5 Functional description...................................................................................................................................................420
Chapter 27
Flash Memory Module (FTFA)
27.1 Introduction...................................................................................................................................................................423
27.1.1 Features........................................................................................................................................................424
27.1.2 Block Diagram.............................................................................................................................................424
27.1.3 Glossary.......................................................................................................................................................425
27.2 External Signal Description..........................................................................................................................................426
27.3 Memory Map and Registers..........................................................................................................................................426
27.3.1 Flash Configuration Field Description.........................................................................................................426
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27.3.2 Program Flash IFR Map...............................................................................................................................427
27.3.3 Register Descriptions...................................................................................................................................428
27.4 Functional Description..................................................................................................................................................436
27.4.1 Flash Protection............................................................................................................................................437
27.4.2 Interrupts......................................................................................................................................................437
27.4.3 Flash Operation in Low-Power Modes........................................................................................................438
27.4.4 Functional Modes of Operation...................................................................................................................438
27.4.5 Flash Reads and Ignored Writes..................................................................................................................438
27.4.6 Read While Write (RWW)...........................................................................................................................439
27.4.7 Flash Program and Erase..............................................................................................................................439
27.4.8 Flash Command Operations.........................................................................................................................439
27.4.9 Margin Read Commands.............................................................................................................................444
27.4.10 Flash Command Description........................................................................................................................445
27.4.11 Security........................................................................................................................................................458
27.4.12 Reset Sequence............................................................................................................................................460
Chapter 28
Analog-to-Digital Converter (ADC)
28.1 Introduction...................................................................................................................................................................461
28.1.1 Features........................................................................................................................................................461
28.1.2 Block diagram..............................................................................................................................................462
28.2 ADC signal descriptions...............................................................................................................................................463
28.2.1 Analog Power (VDDA)...............................................................................................................................464
28.2.2 Analog Ground (VSSA)...............................................................................................................................464
28.2.3 Voltage Reference Select.............................................................................................................................464
28.2.4 Analog Channel Inputs (ADx).....................................................................................................................465
28.2.5 Differential Analog Channel Inputs (DADx)...............................................................................................465
28.3 Memory map and register definitions...........................................................................................................................465
28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................................................................................466
28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...........................................................................................469
KL36 Sub-Family Reference Manual, Rev. 3, July 2013
18 Freescale Semiconductor, Inc.
Section number Title Page
28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...........................................................................................471
28.3.4 ADC Data Result Register (ADCx_Rn).......................................................................................................472
28.3.5 Compare Value Registers (ADCx_CVn).....................................................................................................473
28.3.6 Status and Control Register 2 (ADCx_SC2)................................................................................................474
28.3.7 Status and Control Register 3 (ADCx_SC3)................................................................................................476
28.3.8 ADC Offset Correction Register (ADCx_OFS)...........................................................................................478
28.3.9 ADC Plus-Side Gain Register (ADCx_PG).................................................................................................478
28.3.10 ADC Minus-Side Gain Register (ADCx_MG)............................................................................................479
28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPD).........................................................479
28.3.12 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)..........................................................480
28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP4)..........................................................480
28.3.14 ADC Plus-Side General Calibration Value Register (ADCx_CLP3)..........................................................481
28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP2)..........................................................481
28.3.16 ADC Plus-Side General Calibration Value Register (ADCx_CLP1)..........................................................482
28.3.17 ADC Plus-Side General Calibration Value Register (ADCx_CLP0)..........................................................482
28.3.18 ADC Minus-Side General Calibration Value Register (ADCx_CLMD).....................................................483
28.3.19 ADC Minus-Side General Calibration Value Register (ADCx_CLMS).....................................................483
28.3.20 ADC Minus-Side General Calibration Value Register (ADCx_CLM4).....................................................484
28.3.21 ADC Minus-Side General Calibration Value Register (ADCx_CLM3).....................................................484
28.3.22 ADC Minus-Side General Calibration Value Register (ADCx_CLM2).....................................................485
28.3.23 ADC Minus-Side General Calibration Value Register (ADCx_CLM1).....................................................485
28.3.24 ADC Minus-Side General Calibration Value Register (ADCx_CLM0).....................................................486
28.4 Functional description...................................................................................................................................................486
28.4.1 Clock select and divide control....................................................................................................................487
28.4.2 Voltage reference selection..........................................................................................................................487
28.4.3 Hardware trigger and channel selects..........................................................................................................488
28.4.4 Conversion control.......................................................................................................................................489
28.4.5 Automatic compare function........................................................................................................................497
28.4.6 Calibration function.....................................................................................................................................498
KL36 Sub-Family Reference Manual, Rev. 3, July 2013
Freescale Semiconductor, Inc. 19
Section number Title Page
28.4.7 User-defined offset function........................................................................................................................499
28.4.8 Temperature sensor......................................................................................................................................501
28.4.9 MCU wait mode operation...........................................................................................................................501
28.4.10 MCU Normal Stop mode operation.............................................................................................................502
28.4.11 MCU Low-Power Stop mode operation......................................................................................................503
28.5 Initialization information..............................................................................................................................................503
28.5.1 ADC module initialization example............................................................................................................503
28.6 Application information................................................................................................................................................505
28.6.1 External pins and routing.............................................................................................................................505
28.6.2 Sources of error............................................................................................................................................507
Chapter 29
Comparator (CMP)
29.1 Introduction...................................................................................................................................................................513
29.2 CMP features................................................................................................................................................................513
29.3 6-bit DAC key features.................................................................................................................................................514
29.4 ANMUX key features...................................................................................................................................................515
29.5 CMP, DAC and ANMUX diagram...............................................................................................................................515
29.6 CMP block diagram......................................................................................................................................................516
29.7 Memory map/register definitions..................................................................................................................................518
29.7.1 CMP Control Register 0 (CMPx_CR0).......................................................................................................518
29.7.2 CMP Control Register 1 (CMPx_CR1).......................................................................................................519
29.7.3 CMP Filter Period Register (CMPx_FPR)...................................................................................................521
29.7.4 CMP Status and Control Register (CMPx_SCR).........................................................................................521
29.7.5 DAC Control Register (CMPx_DACCR)....................................................................................................522
29.7.6 MUX Control Register (CMPx_MUXCR)..................................................................................................523
29.8 Functional description...................................................................................................................................................524
29.8.1 CMP functional modes.................................................................................................................................524
29.8.2 Power modes................................................................................................................................................533
29.8.3 Startup and operation...................................................................................................................................534
KL36 Sub-Family Reference Manual, Rev. 3, July 2013
20 Freescale Semiconductor, Inc.
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NXP KL3x Reference guide

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