Broadcom ACPL-C740 Evaluation Kit Board: Isolated Sigma-Delta Modulator User guide

Broadcom
Brand
Broadcom
Model
ACPL-C740 Evaluation Kit Board: Isolated Sigma-Delta Modulator
Type
User guide
User Guide
Broadcom ACPL-C740-EvalKit-UG100
January 4, 2019
Description
The Broadcom ACPL-C740 isolated sigma-delta (Σ-Δ) modulator converts an analog input signal into a high-speed (20 MHz
typical) single-bit data stream by means of a sigma-delta over-sampling modulator. The time average of the modulator data
is directly proportional to the input signal voltage. The modulator uses an internal speed of 20 MHz. The modulator data are
encoded and transmitted across the isolation boundary where they are recovered and decoded into a high-speed data
stream of digital ones and zeros. The original signal information is represented by the density of ones in the data output.
The input signal information is contained in the modulator output data stream, represented by the density of ones and zeros.
The density of ones is proportional to the input signal voltage, as shown in Figure 1. A differential input signal of 0V ideally
produces a data stream of ones 50% of the time and zeros 50% of the time. A differential input of –200 mV corresponds to
an 18.75% density of ones, and a differential input of +200 mV is represented by an 81.25% density of ones in the data
stream. A differential input of +320 mV or higher results in ideally all ones in the data stream, while an input of –320 mV or
lower results in all zeros, ideally. Table 1 shows this relationship.
Figure 1: Modulator Output vs. Analog Input
Table 1: Input Voltage with Ideal Corresponding Density of 1s at Module Data Output, and ADC Code
Analog Input Voltage Input Density of 1s Density of 0s ADC Code (16-bit unsigned decimation)
+Full-Scale +320 mV 100% 0% 65,535
+Recommended Input Range +200 mV 81.25% 18.75% 53,248
Zero 0 mV 50% 50% 32,768
–Recommended Input Range –200 mV 18.75% 81.25% 12,288
–Full-Scale –320 mV 0% 100% 0
+FS (ANALOG INPUT)
0V (ANALOG INPUT)
TIME
MODULATOR OUTPUT
ANALOG INPUT
–FS (ANALOG INPUT
)
ACPL-C740 Evaluation Kit Board
Isolated Sigma-Delta Modulator
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
A digital filter converts the single-bit data stream from the modulator into a multi-bit output word similar to the digital output
of a conventional A/D converter. With this conversion, the data rate of the word output is also reduced (decimation). A Sinc3
filter is recommended to work together with the ACPL-C740. With a 20-MHz internal clock frequency, 256 decimation ratio,
and 16-bit word settings, the output data rate is 78 kHz (20 MHz/256). This filter can be implemented in an ASIC, FPGA, or
DSP.
In this evaluation board, a Sinc3 filter is implemented using the Xilinx Spartan XC3S250E FPGA. The FPGA hardware is
designed in a Verilog/VHDL environment. The major building blocks are the Digital Filter and USB interface control, as
shown in Figure 2. The design is synthesized and implemented using the Xilinx Tool to a bitstream file. This bitstream file
can be loaded to FPGA through USB, a step already done for each evaluation board kit.
Figure 2: Digital Filter and USB Interface Control
Preparation and Setup
Each complete ACPL-C740 evaluation kit shipment includes the following items:
ACPL-C740 evaluation board
Cable with USB/mini-USB terminations
Softcopy folder containing drivers and application software programs. The softcopy folder contains the following
document or software programs:
– ACPL-C740 Xilinx FPGA Evbd Kit User Guide.pdf: Evaluation board user guide
– CDM21228_Setup.exe: FTDI USB chipset driver for Windows 32-bit and 64-bit operating systems. For other
operating systems, download from the manufacturer's website (http://www.ftdichip.com/Drivers/VCP.htm)
– dig_filter.exe: Broadcom application GUI software
– DigFil_200mvINcmosOUT.bit: FPGA bitfile
– Sinc3_verilog.txt: Sinc3 filter codes in Verilog
– Sinc3_VHDL.txt: Sinc3 filter codes in VHDL
– Sine wave files: Sine waves configured to different frequencies 500 Hz, 1000 Hz, and 2000 Hz that can be played
from any audio player
1. Save the softcopy folder to a PC directory location. See the appendix for descriptions of the major components on the
evaluation board, the schematic diagrams, and PCB layout.
2. Connect the FPGA-EVBD board to the PC using the provided USB cable.
3. Turn on switch SW1. The red 5VIN LED lights up, indicating the presence of a USB connection.
4. Install the CDM21228_Setup.exe USB chipset driver file. The driver installs two ports: USB Serial Converter A and USB
Serial Converter B.
ACPL-C740
FPGA
Digital
Filter
USB
interface
Chip
USB
interface
control
Clock detection
mclk
mdat
A
n
alog Input
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
5. To verify that the installation is successful, open the Device Manager. Under Universal Serial bus controllers, the two
ports USB Serial Converter A and USB Serial Converter B should appear.
6. Each time the evaluation board SW1 is turned on, the board goes through a series of power-on sequences. When
completed, the green DONE LED comes on to indicate completion of the power-on sequences.
7. Connect the C740-SDM-EVBD board to the FPGA-EVBD. Once connected, LED1 to LED4 light up in an undefined
sequence to indicate that the board connections are properly done.
The C740-SDM-EVBD and FPGA-EVBD boards are shown, respectively, below:
8. Go to the PC directory and run the dig_filter.exe application program. Refer to the application GUI screen capture as
shown in Figure 3. If the evalboard is connected and SW1 switched on, a Broadcom-System message appears on the
right of the Search button. If SW1 is not turned on, an error message appears, as shown below.
Click OK and the application GUI appears. The message System not connected!! displays instead.
9. Switch on SW1. Go to the application GUI, and click Search. Now, the message changes to Broadcom-System to
indicate that the connection is established.
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
Application GUI
The application GUI has three displays: two showing the signal in the time domain and frequency domain, and a third
showing SNR and SNDR historical plots. The time domain signal can be displayed in terms of ADC count or voltage level
(mV) by checking the Display (mV).
Figure 3: Application GUI Example
To the right of the displays, real-time minimum, maximum, and average signal levels are shown in the time domain in terms
of either mV or ADC count. SNR, SNDR, 2nd harmonic, and 3rd harmonic levels are displayed in the frequency domain.
1. Click Start to begin capturing the input signal. The configured board frequency is captured under the Frequency box and
the type of sigma-delta modulator in terms of input range and output signal type displays in the Board/Product.
2. Save the signal, FFT, and SNR/SNDR history data into text files that are readable and compatible to Microsoft Excel by
selecting the Datalog (signal, fft, and snr/sndr history) box. The snr.txt, signal.txt, and fft.txt files are stored in the same
file directory as the application GUI.
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
3. If there is an updated FPGA bitfile or a newly configured bitstream file, this can be can be uploaded by clicking Load
FPGA Bit File on the top-left corner of the application GUI. When the bitfile is being uploaded, the green DONE LED
goes off and the red UPLOAD LED displays. When uploading is completed, the red UPLOAD LED goes off, while the
green DONE LED displays again to signal completion. The FPGA LOAD Completed! pop-up appears, as shown below.
4. For quick help, click Help from the top-right corner of the application GUI, then select the setup guide. The help guide
also describes the calibration procedure to zero the offset.
Measurement
There are a few ways to apply an input signal to the evaluation board:
Apply input current signal with a shunt resistor.
Example: Select the shunt resistor value is shown below:
If maximum RMS current through the motor = 30A, 20% overloads during normal operation, then, peak current is 51A
(30 × 1.414 × 1.2). The recommended maximum input voltage for ACPL-C740 is ±200 mV.
Shunt resistor value = V/I = 200 mV/51A ≈ 4 mΩ
Power dissipation = I
2
× R = (30)
2
× 4 mΩ = 3.6W
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
The shunt resistor mounting pad is designed to accommodate various shunt resistor package types. The Kelvin
connection PCB trace connects from the center of the pad to the inputs of ACPL-C740 through the anti-aliasing filters
(AAFs). Connecting from the center of the pads is usually the optimum location for most shunt resistor designs. The
evaluation board also provides pads P1 and P2 for soldering thick cables to the motor driving board.
Apply an input voltage signal without a shunt resistor.
Connect the audio cable with the audio 3.5-mm jack connected to either a PC, smart phone, tablet, MP3 player, or any
kind of audio player device. Then, connect the crocodile clips to the shunt resistor mounting pads.
Check the 1 kHz sine test signal and supply a 1 kHz sine wave voltage signal to the evaluation board. Other methods
include playing any of the three provided sine wave files on a music player software program from the audio player
devices described previously. Adjust the volume until the signal level is near ±200 mV or ±20,000 ADC counts for best
SNR/SNDR performance.
The performance of SNR/SNDR is dependent on a few factors:
– The evaluation board
– The sigma-delta modulator used, in this case, the ACPL-C740
– Input signal frequency used
– The decimation ratio, which can be set at the application GUI to 256, 128, or 64.
– The input signal level. The ACPL-C740 recommended input voltage range is from –200 mV to 200 mV. To achieve
the best SNR/SNDR, design the maximum input signal range nearest ±200 mV (using the selection of the input
current range and shunt resistor value).
– The input signal source.
Table 2 shows a comparison of the SNR/SNDR performance between audio signal sources coming from a laptop.
Table 2: SNR/SNDR Comparison
Filter
Configuration
Signal Source from Audio Jack of Laptop
Signal Freq. = 500 Hz Signal Freq. = 1000 Hz Signal Freq. = 2000 Hz
SNR(dB) SNDR(dB) SNR(dB) SNDR(dB) SNR(dB) SNDR(dB)
Sinc3 DR = 64 not enough sampling sinewave cycles 66 64 61 59
Sinc3 DR = 128 76 73 74 73 70 63
Sinc3 DR = 256 77 75 78 77 73 63
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
Figure 4: Measurement Setup
Lab bench test: Apply input voltage signal from a function generator with one shunt resistor mounted on the input of
evaluation board.
A more accurate method to measure the performance of the ACPL-C740 evaluation board is to connect a 1-shunt
resistor, then supply the voltage signal from a function generator that can drive sufficient current through the 1-shunt
resistor until an input signal level of ±200 mV is reached. One such function generator is the ultra low distortion DS360
function generator from Standford Research Systems.
Table 3 shows the SNR/SNDR performance using this method.
If such a function generator is not available, it is best to connect an actual shunt resistor and connect to the current-sensing
system directly.
Table 3: SNR/SNDR Performance
Filter
Configuration
Signal Source from Audio Jack of Laptop
Signal Freq. = 500 Hz Signal Freq. = 1000 Hz Signal Freq. = 2000 Hz
SNR(dB) SNDR(dB) SNR(dB) SNDR(dB) SNR(dB) SNDR(dB)
Sinc3 DR = 64 not enough sampling sinewave cycles 75 72 72 71
Sinc3 DR = 128 81 77 79 76 79 76
Sinc3 DR = 256 82 78 82 78 81 77
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
Isolated DC-DC Converter
The isolated DC-DC converter circuitry is designed based on the push-pull transformer method to provide isolated Vdd1=5V
for the Broadcom ACPL-C740 sigma-delta modulator from the 5V power supply directly from the micro-USB type B
connector of the FPGA-EVBD board. The design incorporates the push-pull transformer driver, PE22100 from pSemi, which
is built in a small form factor of 2 x 2 x 0.5 mm
3
QFN package and can operate from –40°C to +125°C. The device consists
of an on-chip oscillator where switching frequency can be set by an external capacitor. The oscillator output is divided by
two in frequency to create anti-phase clock signals that drive two power switches. In this design, Cset of the PE22100 is
selected as 100 pF, which results in a switching frequency of around 200 kHz. This frequency is outside the operating
bandwidth of the ACPL-C740 sigma-delta modulator and the Sinc3 filter FFT bandwidth used for filtering and decimating the
sigma-delta bitstream from the ACPL-C740.
The PE22100 drives the Wurth push-pull transformer coil (PN 750313638). The transformer coil can withstand isolation
voltage of Viso = 5 kVrms per 1 min., and built into a package with creepage and clearance distance of 8 mm. The
transformer coil operates at an ambient temperature from –40°C to +125°C. The two outputs of the transformer coil are then
combined after the Schottky diodes. The output voltage must be regulated through a 5V/5V LDO regulator. The plot below
shows measurement conversion efficiency versus output load current.
Figure 5: Vout and Conversion Efficiency of the Isolated DC-DC Converter
For further technical support and pricing enquiries, contact pSemi at sales_europe@psemi.com or Wurth at midcom@we-
online.com.
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
PCB Modifications
1. Vdd1 is supplied from the 5V/5V isolated DC-DC converter using the push-pull transformer method. Vdd1 can also be
supplied externally. To do that, ensure that R1 is disconnected.
2. The ACPL-C740 Vdd2 is supplied from the 3.3V regulator. To check the performance or troubleshoot the ACPL-C740
component only at Vdd2 = 5V, short Pin 1 and Pin2 of the J5 connector on the C740-SDM-EVBDv2 board. The Vdd2 is
then supplied directly from the USB power, 5VCC.
Note that R18 must be removed on the FPGA-EVBD board.
3. Green LED1–4 signals the detection of ACPL-C740. To modify the FPGA, use these LED indicators for other functions.
4. The H1 and H2 connector pins are physically connected to the FPGA. To modify the FPGA, use these connector pins
for input (I/P) or input/output (I/O).
Troubleshooting
If the green DONE LED does not come on after switching on SW1, reset the FPGA by pressing SW2 once. If the problem
arises, perform a full board reset by pressing SW3 once.
Each evaluation board is functionally checked and tested. before being sent to the customer. If a problem continues to arise,
consult a Broadcom Application Engineer. If need be, Broadcom will send a new board.
Appendix
Figure 6: PCB Description
ACPL-C740
Isolated Sigma-
Delta Modulator
pSemi PE22100
transformer driver
Shunt
Resistor
Mounting
SW1 board turn
on switch
Xilinx Spartan
XC3S250E
FPGA
SW2 reset
FPGA to
default setting
USB
Connector
Interface
SW3 board
power on
sequence reset
Xilinx JTAG
Interface
ACPL-C40 Low
Voltage Side
Connections
I/P pins
physically
connected to
FPGA
I/O pins
physically
connected to
FPGA
LED “5VIN”
indicates
presence
of USB
connection
USB UART /
FIFO IC
EEPROM to
store USB
chipset
settings
Nonvolatile flash
memory to store
FPGA bitfile
LED “DONE”
indicates power
on sequence
complete
LED “HB”
application
software is
running
LED “UPLOAD”
indicates FPGA
bitfile is being
uploaded
Undefined LED
2,3,4 Indicators
LED1-4 indicates
that FPGA detects
ACPL-C740
C740-SDM-Evbdv2
FPGA-Evbd
Wurth 750313638
transformer coil
A
blic S-1200B50
5V-5V voltage
regulator
Isolated DC -DC Converter
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
Figure 7: PCB Description
C740-SDM-EVBD Schematic Diagram
Figure 8: C740-SDM-EVBD Schematic Diagram
3.3V
Regulator
2.5V
Regulator
1.2V
Regulator
+
10 uF
C1
0.1 uF
C2
0.1 uF
C13
22 nF
C10
10RR5
10RR6
0RR1
1 uF
DNM
C14
DNM
0R
R7
VDD2
MDAT
MCLK
DNM
0R
R3
DNM
10m
Rsm
DNM
10m
Rshunt
100 nF
C12
RUBBER
FOOTER
RF1
Vdd1
+
10 uF
C15
VDD1
1
VIN+
2
VIN-
3
GND1
4
GND2
5
MDAT
6
MCLK
7
VDD2
8
U1
ACPL-C740
0RR8
GND1
GND1 GND2
P1
RSHUNT+
P2
RSHUNT-
0RR9
0RR10
RUBBER
FOOTER
RF2
RUBBER
FOOTER
RF3
RUBBER
FOOTER
RF4
GND2
5VCC
1
2
3
4
5
6
7
8
J5
Header pin 1x8 RA
+
10 uF
C11
OUTA
1
GND
2
CSET
3
EN
4
VREG
5
RSET
6
VDD
7
GND
8
OUTB
9
OUTB
10
SGND
11
OUTA
12
U9
PE22100
VIN
1
VSS
2
EN
3
NC
4
VOUT
5
U10
S-1200B50
1
2
H3
2
1
3
1:1.3
4
5
6
T1
750313638
Vdd1
GND1
1 uF
DNM
C3
+
10 uF
C4
D1
MBR0520L
D2
MBR0520L
GND1
100 nF
C9
+
10 uF
C8
470 nF
C7
100 pF
C6
5VCC
GND2
82K
R2
GND2
0RR4
1 uF
C5
GND2
GND2
8 mm Isolation
GND2
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
C740-SDM-EVBD PCB Layout
Figure 9: C740-SDM-EVBD PCB Top Layer
Figure 10: C740-SDM-EVBD PCB Second Layer
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
Figure 11: C740-SDM-EVBD PCB Third Layer
Figure 12: C740-SDM-EVBD PCB Bottom Layer
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
FPGA-EVBD Schematic Diagram
Figure 13: FPGA-EVBD Schematic Diagram (Part 1)
3V3OUT
6
USBDM
8
USBDP
7
RSTOUT#
5
XTIN
43
XTOUT
44
RESET#
4
EECS
48
EESK
1
EEDA TA
2
TEST
47
AGND
45
GND
9
GND
18
GND
25
GND
34
AD0
24
AD1
23
AD2
22
AD3
21
AD4
20
AD5
19
AD6
17
AD7
16
AC0
15
AC1
13
AC2
12
AC3
11
SI/WUA
10
BD0
40
BD1
39
BD2
38
BD3
37
BD4
36
BD5
35
BD6
33
BD7
32
BC0
30
BC1
29
BC2
28
BC3
27
SI/WUB
26
PWREN
41
AVCC
46
VCC
3
VCC
42
VCCIOA
14
VCCIOB
31
U2
FT2232D
GND2
GND2
VCC
8
NC
7
ORG
6
GND
5
CS
1
SK
2
DIN
3
DOUT
4
U3
93C56B
GND2
2.2KR410KR7
SW2
B3S-1000
EEPROM, 2 MHz, 128x16
FTDI_SI
27R17
27R16
FTDI_WR
FTDI_RD
FTDI_TXE
FTDI_RXF
FTDI_D0
FTDI_D1
FTDI_D2
FTDI_D3
FTDI_D4
FTDI_D5
FTDI_D6
FTDI_D7
SPI_PROG
150 5%
R13
GND2
FPGA_RESET
SPI_INIT
SPI_CSO_B
SPI_DIN
SPI_MOSI
SPI_CLK
10K 5%
R28
3V3X
0.1 uF
C39
GND2
3V3X
2.2K
R5
I/O Set at
3.3V
0.01 uF
C8
GND2
0.1 uF
C6
Downloading
FPGA Code
For FPGA configuration via
SPI only.
1
2
FB2
1 2
FB1
470
R1
0.1 uF
C2
GND2
27
R2
GND2
GND2
47 pF
C11
GND2
27
R3
1.5KR6
0.47 uFC12
+
C34
GND2
0.1 uF
C3
GND2
0.01 uF
C1
GND2
1
2
DNM
J1
GND2
PORTVCC
5VIN
0.1 uF
C5
0.1 uF
C10
GND2
+
C33
GND2
VCCSW
USER_IN0
USER_IN1
USER_IN2
USER_IN3
USER_IN4
USER_IN5
USER_IN6
USER_IN7
USER_IN8
USER_IO0
USER_IO1
USER_IO2
USER_IO3
USER_IO4
USER_IO5
USER_IO6
USER_IO7
USER_IO8
USER_IO9
USER_IO10
USER_IO11
USER_IO12
USER_IO16
USER_IO17
USER_IO18
USER_IO19
USER_IO20
USER_IO21
USER_IO22
USER_IO23
USER_IO24
USER_IO25
USER_IO26
USER_IO27
USER_IO28
GND2
500mA 240-2390-2
MI0805K601R-10
5VCC
6 MHz GND2
GND2
SW3
B3S-1000
GND2
5VCC
USER_IO13
GND2
4.7KR24
4.7K
R23
5VCC
1
2
3
SW1
EG1218
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
DNM
USER_IO
H1
CR1
0.033 uF
C4
0.033 uF
C7
5VIN
UPLOAD
R22
10K
R40
0R
1
2
3
4
5
6
7
8
9
DNM
USER IN
H2
GND2
MCLK
MDAT
VDD2
5VCC
USER_IO0
USER_IN0
3V3X
0RR18
0RR19
0RR20
1
2
3
4
5
6
7
8
J5
Heade
r socket 1x8 RA
D-
D+
GND
5
ID
4
D+
3
D-
2
Vbus
1
Shi el d
SH
C
N1
ZX62D-AB-5P8(30)
D
G
S
Q2
IRLM L6402
RUBBER
FOOTER
RF1
RUBBER
FOOTER
RF2
RUBBER
FOOTER
RF3
RUBBER
FOOTER
RF4
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
Figure 14: FPGA-EVBD Schematic Diagram (Part 2)
2V5 3V3X
0
C
0
C
GND2
2
Broadcom ACPL-C740-EvalKit-UG100
15
ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
FPGA-EVBD PCB Layout
Figure 15: FPGA-EVBD PCB Top Layer
Figure 16: FPGA-EVBD PCB Second Layer
Broadcom ACPL-C740-EvalKit-UG100
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ACPL-C740 Evaluation Kit Board User Guide Isolated Sigma-Delta Modulator
Figure 17: FPGA-EVBD PCB Third Layer
Figure 18: FPGA-EVBD PCB Bottom Layer
Broadcom, the pulse logo, Connecting everything, Avago Technologies, Avago, and the A logo are among the trademarks
of Broadcom and/or its affiliates in the United States, certain other countries, and/or the EU.
Copyright © 2019 Broadcom. All Rights Reserved.
The term “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. For more information, please visit www.broadcom.com.
Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability,
function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does
not assume any liability arising out of the application or use of this information, nor the application or use of any product or
circuit described herein, neither does it convey any license under its patent rights nor the rights of others.
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Broadcom ACPL-C740 Evaluation Kit Board: Isolated Sigma-Delta Modulator User guide

Broadcom
Brand
Broadcom
Model
ACPL-C740 Evaluation Kit Board: Isolated Sigma-Delta Modulator
Type
User guide
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