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  3. EVBD-ACSL-7210 PROFIBUS / SPI Evaluation Board for ACSL-7210 Dual-Channel (Bidirectional) 25 MBd CMOS Buffered Input Digital Optocoupler

Broadcom EVBD-ACSL-7210 PROFIBUS / SPI Evaluation Board for ACSL-7210 Dual-Channel (Bidirectional) 25 MBd CMOS Buffered Input Digital Optocoupler User guide

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EVBD-ACSL-7210 PROFIBUS / SPI Evaluation Board
ACSL-7210 Dual-Channel (Bidirectional) 25 MBd
CMOS Buered Input Digital Optocoupler
User Guide
Product Description
Avago’s ACSL-7210 optocoupler utilizes the latest CMOS
IC technology to achieve outstanding speed and low
power performance of minimum 25 MBd data rate.
Available in SO-8 package, the basic building blocks of
each channel in ACSL-7210 are a CMOS LED driver IC, a
high speed LED and a CMOS detector IC. A CMOS logic
input signal controls the LED driver IC, which supplies cur-
rent to the LED. The detector IC incorporates an integrated
photodiode, a high speed trans-impedance amplier, and
a voltage comparator with an output driver.
Functional Diagram
Features
• Dual-Channel (Opposite direction orientation)
• 3.3 V and 5 V CMOS Compatibility
• High Speed: DC to 25 MBd
• CMOS output and buer input
• Operating temperature: –40°C to +105°C
• Safety and Regulatory Approvals:
- UL 1577 – 3750 Vrms for 1 minute
- IEC/EN/DIN EN 60747-5-5
About the Evaluation Board
The ACSL-7210 PROFIBUS / SPI evaluation board is con-
gurable for either PROFIBUS (RS-485) or SPI communica-
tion. The board will accept both 3.3V and 5V power sup-
plies.
When congured for PROFIBUS communication, the
ACSL-7210 bi-directional optocoupler provides isolation
for both the transmitting and receiving channels. Isolation
for the Tx Enable signal is provided by the ACPL-M61L, ul-
tra low power 10MBd CMOS digital optocoupler. A stan-
dard RS-485 transceiver (max. data rate of 20Mbps) is in-
cluded on the board.
For SPI interface, the ACSL-7210 is used for serial data in/
out isolation. Isolation for the clock signal is provided by
ACPL-077L, low power 25MBd CMOS digital optocoupler.
Figures 1 and 2 shows the jumper settings for PROFIBUS
and SPI operation. Figure 3 shows the schematic diagram
of the evaluation board.
ACSL-7210
8
5
6
VO
A
VDD
2
GND
2
VO
B
Shield
1
VDD
1
GND
1
4
7
VI
A
VI
B
3
2
TRUTH TABLE (POSITIVE LOGIC)
Input side
V
DD
state
Output side
V
DD
state V
I
LED V
O
Power
Supplied
Power
Supplied
HIGH OFF HIGH
LOW ON LOW
No Power Power
Supplied
X OFF HIGH
2
Board Connection and Operation
PROFIBUS Operation (Refer to Figure 1)
1. Short i) lower 2 pins of J1, ii) lower 2 pins of J4, and iii) upper 2 pins of J5.
2. The jumpers on J2 and J3 should be connected.
3. Connect a 3.3/5V power supply to VDD1 and GND1.
4. Connect a 3.3/5V power supply to VDD2 and GND2.
5. Connect the RS-485 dierential lines to SMA connectors +(485) and –(485).
6. Connect SMA connectors TX_EN(485), TX(485) and Rx(485) to microcontroller.
Figure 1. Conguration for PROFIBUS (RS-485) Operation
Short lower
2 pins of J1
Short lower 2 pins of J4,
and upper 2 pins of J5
Jumpers on J2 and J3
should be connected.
3
Figure 2. Conguration for SPI Operation
SPI Operation (Refer to Figure 2)
1. Short i) upper 2 pins of J1, ii) upper 2 pins of J4, and iii) lower 2 pins of J5.
2. J2 and J3 should be left open.
3. Connect a 3.3/5V power supply to VDD1 and GND1.
4. Connect a 3.3/5V power supply to VDD2 and GND2.
5. The master device should be connected to SCK(SPI_M), MOSI(SPI_M), and MISO(SPI_M).
6. The slave device should be connected to SCK(SPI_S), MOSI(SPI_S), and MISO(SPI_S).
Short upper
2 pins of J1
Short upper 2 pins of J4,
and lower 2 pins of J5
J2 and J3 should
be left open
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved.
AV02-4309EN - September 30, 2013
Figure 3. Schematic Diagram for ACSL-7210 Evaluation Board
VDD1
1
VI
2
NC
3
GND1
4
GND2
5
VO
6
NC
7
VDD2
8
U4
ACPL-077L
VDD1
1
VOA
2
VIB
3
GND1
4
GND2
5
VOB
6
VIA
7
VDD2
8
U1
ACSL-7210
AN
1
CA
3
GND
4
VO
5
VDD
6
U2
ACPL-M61L
RO
1
RE_
2
DE
3
DI
4
GND
5
A
6
B
7
VCC
8
U3
RS485 Trans
C1
100n
VDD2
C5
100n
C6
100n
C4
100n
R1
510
C2
100n
VDD2
VDD2
C3
100n
2 1
3
J1
R2
360
1
2
1
2
VDD1
VDD1
VDD1
VDD1
VDD2
TP1
TP2
TP3
TP4
TP5
TP6
1
2
J3
1 2
J2
21
3
J5
21
3
J4
VDD2
TP7
TP8
TP10 TP12
TP11 TP13
TP9
VDD1
GND1
VDD2
GND2
RX(485)/MISO(SPI_M)
TX(485)/MOSI(SPI_M)
TX_EN(485)/SCK(SPI_M)
SCK(SPI_S)
-(485)/MOSI(SPI_S)
+(485)/MISO(SPI_S)
/