Freescale Semiconductor C29x User manual

C29x PCIe Card User Guide

Document Number: C29xPCIeUG

Rev 0, 10/2013

C29x PCIe Card User Guide, Rev. 0, 10/2013

2 Freescale Semiconductor, Inc.

Contents

Section number Title Page

Chapter 1

Introduction

1.1 Acronyms..........................................................................................................................................................................7

1.2 Related Documentation.....................................................................................................................................................7

1.3 Architectural Overview.....................................................................................................................................................8

1.4 Board Drawing and Top View..........................................................................................................................................10

Chapter 2

PCIe Use Cases

2.1 PCIe Endpoint Mode.........................................................................................................................................................13

2.2 Standalone Host Mode......................................................................................................................................................14

2.3 PKCAL/SKMM Mode......................................................................................................................................................16

2.4 Secure Boot Mode.............................................................................................................................................................16

Chapter 3

Clocks, Resets, and Power Control

3.1 Clocks...............................................................................................................................................................................19

3.2 Resets................................................................................................................................................................................20

3.3 Power Block Diagram.......................................................................................................................................................21

Chapter 4

On-Board Resources

4.1 DDR Memories.................................................................................................................................................................23

4.2 IFC....................................................................................................................................................................................24

4.2.1 NOR Flash Memory.............................................................................................................................................24

4.2.2 NAND Flash Memory..........................................................................................................................................25

4.3 SerDes...............................................................................................................................................................................26

4.4 Ethernet.............................................................................................................................................................................27

4.4.1 eTSEC1................................................................................................................................................................27

4.4.2 eTSEC2................................................................................................................................................................27

4.5 eSPI...................................................................................................................................................................................28

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Section number Title Page

4.6 RS-232..............................................................................................................................................................................28

Chapter 5

Board Connectors, LED, and Push Button

5.1 Connectors........................................................................................................................................................................31

5.2 Headers.............................................................................................................................................................................31

5.3 Jumpers.............................................................................................................................................................................31

5.4 JTAG/COP Connector......................................................................................................................................................32

5.5 LED...................................................................................................................................................................................33

5.6 Push Button.......................................................................................................................................................................34

Chapter 6

POR Configuration

6.1 POR Settings in Different Boot Location Modes.............................................................................................................40

6.1.1 NOR Flash POR Settings.....................................................................................................................................40

6.1.2 NAND Flash POR Settings..................................................................................................................................41

6.1.3 SPI Flash POR Settings........................................................................................................................................42

Chapter 7

CPLD Specification

7.1 Key Features.....................................................................................................................................................................43

7.2 CPLD Memory Map/Register Definition.........................................................................................................................43

7.2.1 Chip ID1 Register (CPLD_CHIPID1).................................................................................................................44

7.2.2 Chip ID2 Register (CPLD_CHIPID2).................................................................................................................45

7.2.3 Hardware Version Register (CPLD_HWVER)...................................................................................................45

7.2.4 Software Version Register (CPLD_SWVER).....................................................................................................46

7.2.5 Reset Control Register (CPLD_RSTCON)..........................................................................................................46

7.2.6 Flash Control and Status Register (CPLD_FLHCSR).........................................................................................47

7.2.7 Watchdog Control and Status Register (CPLD_WDCSR)..................................................................................48

7.2.8 Watchdog Kick Register (CPLD_WDKICK)......................................................................................................48

7.2.9 Fan Control and Status Register (CPLD_FANCSR)...........................................................................................49

7.2.10 Panel LED Control and Status Register (CPLD_LEDCSR)................................................................................49

7.2.11 Miscellanies Control and Status Register (CPLD_MISCCSR)...........................................................................50

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Section number Title Page

7.2.12 Boot Configuration Override Register (CPLD_BOOTOR).................................................................................50

7.2.13 Boot Configuration Register 1 (CPLD_BOOTCFG1).........................................................................................51

7.2.14 Boot Configuration Register 2 (CPLD_BOOTCFG2).........................................................................................51

7.2.15 Boot Configuration Register 3 (CPLD_BOOTCFG3).........................................................................................52

7.2.16 Boot Configuration Register 4 (CPLD_BOOTCFG4).........................................................................................53

Chapter 8

Programming U-Boot

8.1 Programming U-Boot on a Board having no U-Boot Installed........................................................................................55

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Chapter 1

Introduction

The C29x PCIe is a PCIe card with a Freescale C29x crypto coprocessor system-on-chip

(SoC)/processor.

1.1 Acronyms

The table below lists and explains the acronyms used in this document.

Table 1-1. Acronyms

Term Description

COP Common On-Chip Processor

CTS Clear-To-Send

DIP Dual In-Line Package

ECC Elliptic Curve Cryptography

EP Endpoint

eTSEC Enhanced Three-Speed Ethernet Controller

I

2

C Inter-Integrated Circuit

IFC Integrated Flash Controller

POR Power-On-Reset

RC Root Complex

RGMII Reduced Gigabit Media Independent Interface

RMII Reduced Media Independent Interface

RTS Ready-To-Send

SerDes Serializer/Deserializer

SoC System-On-Chip

SPI Serial Peripheral Interface

UART Universal Asynchronous Receiver/Transmitter

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1.2 Related Documentation

The table below lists and explains the additional documents that you can refer to, for

more information about C29x PCIe.

Table 1-2. Related documentation

Document Description

C29x Crypto Coprocessor Family

Reference Manual

Defines the functionality of the Freescale C29x family. Freescale C29x family consists

of three highly integrated security processors, optimized for public key acceleration and

secure key management. Each family member combines a Power Architecture

processor core with a high performance security engine, network and high-speed serial

interfaces, DDR and non-volatile memory controllers.

C29x Crypto Offload User Guide Explains the procedure to build, configure, and use different software components for

the Freescale C29x crypto coprocessor device.

C29x PCIe Card Getting Started

Guide

Explains C29x PCIe board settings and physical connections needed to boot the board.

Freescale C29x Crypto Coprocessor

Family Product Brief

Provides an overview of the Freescale C29x family of crypto coprocessor features, and

examples of C29x usage.

1.3 Architectural Overview

The figure below shows the block diagram of C29x.

Architectural Overview

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C29x

Security Fuse Processor

Security Monitor

IFC

Power Management

eSDHC

2x DUART

2x I2C

eSPI, GPIO

Power Architecture

e500-v2 Core

TM

32 KB

D-Cache

32 KB

I-Cache

512 KB

Platform Cache

32-bit

DDR3/3L

Memory

Controller

SEC1

SEC2

SEC3

Coherent System Bus

512 KB

Platfrom

SRAM

eTSEC

4-lane 5 GHz SerDes

PCle

DMA

Real Time Debug

JTAG

Figure 1-1. C29x block diagram

The figure below shows the block diagram of the C29x PCIe card.

Magnetics

RS232

RJ45

(Console)

RJ45 x2 (Ethernet)

MDI

RS232

XCVR

UART

GE PHY

VSC8641

MDIO

RGMII

DUART

RGMII

C29x

IFC

I2C

SerDes

JTAG

SPI

COP

Connector

PCle x4

EEPROM

S25FL 128

SPI IF

I2C IF

Thermal

Monitor

EEPROM

AT24C1024

CORE POWER

12V

PCle Finger

Power

Select

Circuit

12V

Power Jack

Super

Sequencer

Power

Regulators

1.0V

Configs

CPLD

NAND Flash

(4 GB)

NOR Flash

(64 MB)

DDR3

(512 MB)

32-bit

Reset

Watch Dog

GE PHY

VSC8641

MDI

Resets

12V

1.5V

GVDD

VTT

3.3V

2.5V

16-bit

8-bit 8-bit

LFC_Data(15:0)/Add(27:0)

TSEC1

DDR

TSEC2

Figure 1-2. C29x PCIe card block diagram

Chapter 1 Introduction

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The C29x PCIe card provides the following integrated functions:

• External interfaces

• One X4 PCIe Gen1 interface

• Two 1 Gb RGMII Ethernet ports

• One RJ45 serial console port that supports one UART up to 115200 bps for

console display

• One JTAG debug interface

• On-board memories

• 64 MB 16-bit NOR flash memory of S29GL512P11TFI0

• 4 GB 8-bit NAND flash memory of K9GBG08U0A

• 512 MB 32-bit DDR3 memory of MT41J128M16

• 16 Mb SPI EEPROM of S25FL128

• Power supplies

• External 12V DC power input

• 2x3 6-pin power connector for ATX power supply

• Headers

• Connector for ADM1069 (power-on control chipset) programming

• Connector for CPLD programming

• Connector for ZL6105 (digital power) programming

• POR configuration

• Supports critical POR settings through DIP switches available on the board

1.4 Board Drawing and Top View

The figure below shows C29x PCIe top side reference drawing.

Board Drawing and Top View

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Figure 1-3. Top side reference drawing

The C29x PCIe card measures 168 mm x 111 mm. It can be installed into a PCIe-x4,

PCIe-x8, or PCIe-x16 slot on the PCIe motherboard.

The figure below shows the top view of the C29x PCIe card.

Chapter 1 Introduction

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2x3 ATX Power

Connector

PCIe x4 Gold-finger

ON/OFF

Switch

Power

LED

UART

ETH1

TSEC2

ETH0

TSEC1

J16

J15

DIP

Switch

J18

for Fan

JTAG

Figure 1-4. C29x PCIe card top view

Board Drawing and Top View

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Chapter 2

PCIe Use Cases

This chapter talks about:

•

PCIe endpoint mode

• Standalone host mode

• PKCAL/SKMM mode

• Secure boot mode

2.1 PCIe Endpoint Mode

The figure below shows the C29x PCIe card, operating in the PCIe endpoint mode.

Figure 2-1. PCIe endpoint mode

Perform the following steps to use the C29x PCIe card in the PCIe endpoint mode:

1.

Connect the heat sink fan power line to J18.

2. Plug C29x PCIe into the PCIe slot on the motherboard. C29x PCIe supports x1, x2,

and x4 configurations.

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3. Connect 2x3 ATX power connector to the ATX power supply of the computer, if

ATX power supply is installed in the computer; otherwise, connect the 12V power

adapter.

4. Connect the RJ45 console line (RJ45 to DB9 cable used) to UART port.

5. Configure the serial port of the attached computer with the following values:

• Data rate: 115200 bps

• Number of data bits: 8

• Parity: None

• Number of stop bits: 1

• Flow control: Hardware/None

6. Connect network cable to TSEC1.

7. Power on host motherboard and put the power switch to ON position. Now, you will

see the boot up message on the computer console.

Following are the device configurations required for this use case by setting DIP switch:

• SW7[1] ON, cfg_cpu_boot=0

• SW7[5] ON, cfg_host_agt=0

The table below shows dual in-line package (DIP) switch settings of the C29x PCIe card

in PCIe endpoint mode (800 MHz core, 400 MHz platform, PCIe-x4 configuration).

Table 2-1. PCIe endpoint mode DIP switch settings

SW4[1..8] 0101 1000 ON OFF ON OFF OFF ON ON ON

SW5[1..8] 1111 0000 OFF OFF OFF OFF ON ON ON ON

SW6[1..8] 0000 1111 ON ON ON ON OFF OFF OFF OFF

SW7[1..8] 0001 0111 ON ON ON OFF ON OFF OFF OFF

SW8[1..8] 0000 1011 ON ON ON ON OFF ON OFF OFF

NOTE

If your host does not recognize the card when performing lspci,

then try changing the PCIe lane configuration.

2.2 Standalone Host Mode

The figure below shows the C29x PCIe card, operating in standalone host mode (without

the host computer).

Standalone Host Mode

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100~240V AC

Figure 2-2. Standalone host mode

Perform the following steps to use the C29x PCIe card in the standalone host mode:

1.

Remove PCIe bracker, and install four plastic posts.

2. Connect heat sink fan power line to J18.

3. Connect 12V power supply.

4. Connect RJ45 console line to UART port.

5. Configure the serial port of the attached computer with the following values:

• Data rate: 115200 bps

• Number of data bits: 8

• Parity: None

• Number of stop bits: 1

• Flow control: Hardware/None

6. Connect network cable to TSEC1.

7. Turn on ON/OFF switch to power on C29x PCIe. Now, you will see C29x PCIe boot

up message on the computer console.

Following are the device configurations required for this use case by setting DIP switch:

• SW7[1] OFF, cfg_cpu_boot=1

The table below shows DIP switch settings of the C29x PCIe board in the standalone

mode (800 MHz core, 400 MHz platform, PCIe-x4 configuration). As compared to the

end point mode, in the standalone mode, SW7[1] is in OFF position.

Chapter 2 PCIe Use Cases

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Table 2-2. Standalone host mode DIP switch settings

SW4[1..8] 0101 1000 ON OFF ON OFF OFF ON ON ON

SW5[1..8] 1111 0000 OFF OFF OFF OFF ON ON ON ON

SW6[1..8] 0000 1111 ON ON ON ON OFF OFF OFF OFF

SW7[1..8] 1001 1000 OFF ON ON OFF ON OFF OFF OFF

SW8[1..8] 0000 1011 ON ON ON ON OFF ON OFF OFF

2.3 PKCAL/SKMM Mode

PKCAL means Public Key Calculator, which is one use case of PCIe endpoint mode.

SKMM means Secure Key Management Module. In this document, SKMM only means

the core does NOT boot from internal SDRAM. In PKCAL mode, the board holds and

wait for the host to load the image into its internal SDRAM, then the host, which is

released, lets the board to run.

In SKMM mode, the board runs the u-boot and loads the Linux by itself while working in

PCIe end point mode. The host can communicate with PCIe interface. The PKCAL/

SKMM mode can be enabled by setting the SW8[8] switch. To enable the PKCAL mode,

set SW8[8] to 0. To enable the SKMM mode, set SW8[8] to 1.

The PKCAL mode can be started from the PCIe endpoint mode. In PKCAL mode, a

C29x processor only uses internal SDRAM, instead of DDR3/NOR flash/NAND flash.

Therefore, DDR/NOR flash/NAND flash should not be initialized in the source code. In

addition, the PKCAL mode requires the board to be booted from the PCIe slot.

For the PKCAL use case, the device boots from either the internal SRAM or the L2

SRAM. The device is in PCI Express agent mode and e500 is in boot hold off. Following

are the device configurations required for this use case by setting DIP switch:

• SW7[1] ON, cfg_cpu_boot=0

• SW7[5] ON, cfg_host_agt=0

• SW8[8] ON, test_sel_b=0

By default, the C29x PCIe card works in the SKMM mode.

PKCAL/SKMM Mode

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2.4 Secure Boot Mode

C29x supply Secure Boot mode to protect customer system. The customer can put

secured encoded u-boot and other image into flash, and put the secure key into C29x

silicon. If secured keys are matched, the image can be loaded and run. The secure boot

mode can be enabled by setting SW7[6] to ON and cfg_sb_dis to 0.

The secure boot mode can be started from the PCIe endpoint mode and standalone host

mode.

To start the secure boot mode from the PCIe endpoint mode, connect J15 and J16 (pin 1

and pin 2). The board will now support secure boot from NOR flash, NAND flash, or SPI

EEPROM.

To start the secure boot mode from the standalone host mode, connect J16 (pin 1 and pin

2), and install the battery. The board will now support secure boot from NOR flash,

NAND flash, or SPI EEPROM.

Following are the device configurations required for this use case by setting DIP switch:

• SW7[6] = ON, cfg_sb_dis=0

The table below lists the secure boot POR settings example in NOR flash boot mode (800

MHz core, 800 MHz DDR, PCIe-x4 agent).

Table 2-3. Secure POR settings

SW4[1..8] 0101 1000 ON OFF ON OFF OFF ON ON ON

SW5[1..8] 1111 1000 OFF OFF OFF OFF OFF ON ON ON

SW6[1..8] 0000 1111 ON ON ON ON OFF OFF OFF OFF

SW7[1..8] 0001 0011 ON ON ON OFF ON ON OFF OFF

SW8[1..8] 0000 1011 ON ON ON ON OFF ON OFF OFF

Chapter 2 PCIe Use Cases

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Secure Boot Mode

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Chapter 3

Clocks, Resets, and Power Control

3.1 Clocks

The figure below shows the C29x PCIe input clocks.

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TCK/TSTCLK

SYSCLK

(66 MHz - 100 MHz)

(207 MHz - 400 MHz)

RTC/CORE_BYPASS_CLK

COP

DDR_CLK

DDR PHY

PLL

(800 MHz - 1300 MHz)

SDHC_CLK

SPI_CLK

IIC[1-2]_SCL

PLL

Lynx(x4)

SD_REF_CLK_B

(100 MHz or 125 MHz)

SD_REF_CLK

(100 MHz or 125 MHz)

EC_GTX_CLK125

EC_MDC

TSEC_GTX_CLK

TSEC_RX_CLK

eTSEC

DDR

/4, 8, /16

MCK_B

MCK

LCK[0:1]

(10 MHz - 100 MHz)

IFC

SAP

tck_nog

tck

PLL

e500 Core

Complex

L2

idcp_ipg_clk

div

PLL

SPI

eSDHC

I2C

CAAMs,

Other IPs

PCI-EX

div

Figure 3-1. C29x PCIe input clocks

In the above figure:

•

SYSCLK is a 66.67 MHz primary clock

• DDR_CLK is 100 MHz external clock

• SD_REFCLK is 100 MHz, required for PCIe interface

• TSEC_RX_CLK is 125 MHz, required for GE port

• CPLD_REFCLK is 32.768 kHz, required for CPLD to work

Resets

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